Implementing VHDL Designs Using Xilinx ISE: A Brief Tutorial

Implementing VHDL Designs Using Xilinx ISE: A Brief Tutorial

This tutorial shows how to create, implement, simulate, and synthesize VHDL designs for implementation in FPGA chips using Xilinx ISE 9.2i and ModelSim: Xilinx Edition III v6.2g.

1. Launch Xilinx ISE from either the shortcut on your desktop or from your start menu under Programs Xilinx ISE 9.2i Project Navigator.

2. Start a new project by clicking File New Project.

3. In the resulting window, verify the Top-Level Source Type is VHDL. Change the Project Location to a suitable directory and give it what ever name you choose, e.g. lab3.

4. The next window shows the details of the project and the target chip. We will be synthesizing designs into real chips so it is important to match the target chip with the particular board/chip you will be using. Labs will be done in a Spartan3 XC3S400 chip that comes in a FT256 package with a speed grade of 4 as shown.

5. Since we are starting a new design the next couple of pop-up windows arent relevant, just click Next and Next and Finish .

6. You should now be in the main Project Navigator window. Select Project New Source from the menu.

7. In the resulting pop-up window specify a VHDL Module source and give the file a name. I tend to just use the same name as the project itself, e.g. Lab 3. Click Next.

8. The next pop-up window allows you to specify your inputs and outputs through the Wizard if you so desire. In this tutorial we will build a 2 x 1 multiplexer so we can specify the inputs and outputs as shown below. Here, the default entity and architecture names have also been changed. Once all inputs and outputs are entered click Next and click Finish.

9. The project will usually open with the design summary tab active in the right hand side of your window. We want to go to the VHDL code so you need to click the *.vhd tab for your design.

10. You can see that the Wizard has used STD_LOGIC as the default type for your signals and also filled in the basic entity and architecture details for you.

11. Now you can fill in the rest of your code for your design. In this case, we can do the multiplexer as shown below. Make sure to frequently save your code.

12. Once the code is entered we can proceed with a simulation of the design or we can synthesize the code for implementation and download onto an FPGA. Let us proceed with the simulation first. In the upper left-hand side of the ISE environment there is a Sources subwindow which has a drop down box as shown below. Note that the drop down box currently shows Synthesis/Implementation. Change this to Behavioral Simulation.

13. Highlight your *.vhd file in the Sources subwindow and then expand the ModelSim Simulator selection in the Processes subwindow as shown below. Click on Simulate Behavioral Model to launch the ModelSim simulator.

14. ModelSim should successfully launch and will open several subwindows by default. For now we just need the Wave and Transcript subwindows, so close the other subwindows and you should see the following:

15. To conduct the simulation you basically only need to know two commands, force and run. Force is used to set the value of any input variable. Then Run the simulation for a specific amount of time. To use a Force command, in the transcript window simply type Force, space, logic variable you wish to set, space, the value you wish to assign (0 or 1). For example, force b 0. Then type run 1000 to run the simulation for 1000 picoseconds. Alternatively, you could type run 1 ns. Change the various inputs one or more at a time and do additional run steps.

16. If you would like to clean things up or begin the simulation over, type restart at the transcript prompt and then click Restart in the resulting pop-up window. You can print the waveforms (Timing Diagram) to any printer or you can do a Shift + Print Screen to copy the waves to the Windows Clipboard so that you can paste and edit the image in a graphics program if you desire.

17. It is convenient to automatically toggle your inputs high and low when testing your circuits. Use can use the force command to do this as well, for example

force a 0 1 ns, 1 2 ns -r 2 ns

says to assign a value of 0 to input a from the current moment to 1 ns from now (force a 0 1 ns). Then from 1 ns to 2 ns from the current moment input a will have a value of 1 (, 1 2 ns). Finally, this pattern will repeat itself every 2 ns (-r 2 ns). For this tutorial circuit, for instance, then you could establish repeating waveforms of different periods that will automatically cycle through every combination of input values. One possibility would be to type

force i0 0 1 ns, 1 2 ns -r 2 nsforce i1 0 2 ns, 1 4 ns -r 4 nsforce a 0 4 ns, 1 8 ns -r 8 nsrun 48 ns

which would result in the timing diagram shown below.

18. Now lets look at the flow for actually synthesizing and implementing the design in the FPGA prototyping boards. Close ModelSim and go back to the Xilinx ISE environment. In the Sources subwindow change the selection in the dropdown box from Behavioral Simulation to Synthesis/Implementation.

19. To properly synthesize the design we need to specify which pins on the chip all the inputs and outputs should be assigned to. In general, of course, we could assign the signals just about any way we want. Since we will be using specific prototype boards, we need to make sure our pins assignments match the switches, buttons, and LEDs so we can test our design. The Spartan 3E boards have the following connections:

20. To assign specific pins, expand the User Constraints selection under the Process subwindow and double-click on Assign Package Pins.

21. A new application called Xilinx PACE should be launched.

22. In the Design Object List subwindow you should see a listing of all the input and output signals from our design.

Here is where we can specify which pin locations we want for each signal. Simply enter the pins numbers from the tables shown in Step 19 above, making sure to use capital letters like F, G, H etc in front of the pin specification. Lets assign our signals as

A F12 (SW 1 - Slider Switch 1)I0 G12 (SW 2 - Slider Switch 2)I1 H14 (SW 3 - Slider Switch 3)Y K12 (LD 0 - LED 0)

Now save your constraints by selecting File Save and exit Xilinx Pace.

23. Back in the Xilinx ISE window we can now tell the computer to synthesize our design. In the Process subwindow double-click on the Synthesize XST selection and wait for the process to complete. Then double-click on the Implement Design selection and wait for the process to complete. Then double-click on the Generate Programming File selection and wait for completion. If all goes well, you should have green checks marks for the whole design.

24. There is a lot of information you can obtain through all of the objects listed in the Processes subwindow, but let us proceed to downloading the design onto the prototyping board for testing. First make sure the prototyping board is connected to the PC and has power on. Also make sure the slide switch on the FPGA board by the parallel port is set to JTAG (as opposed to Port). Then select Configure Device (iMPACT) underneath the Generate Programming File selection. You should the following window

25. Now you need to specify which bitstream file to use to configure the device. For this tutorial we want to select the mux.bit file and click Open.

You will also get a warning message saying the JTAG clock was updated in the bitstream file (which is good) so just click OK. There is a way to correct for that in the original design flow, but Xilinx automatically catches it here so I dont usually bother.

You will then see another window popping up asking you to assign a new configuration file for the Flash memory chip XCF02S. Click on the Bypass option here as we are not going to use the Flash memory initially.

26. You should now see the XC3S400 and XCF02S chips in the main window.

Right click on the XCF02S and select the Erase option as below to remove any previous contents. A non-erased Flash chip causes download problems.

You will see the Erase Succeeded message if the Flash memory chip.

27. Right click on the FPGA (XC3S400) to prepare for downloading the bitstream file. Select Program on the resulting window.

28. Click OK.

If all goes well you should get the Programming Succeeded message

29. Now just test and verify your design on the actual FPGA board!