Issue 26 Third Quarter 1997 GENERAL Editorial: What Do You Think? .............. 2 New Building in San Jose ....................... 2 Customer Success Story - Cognex ....... 3 Upcoming Events ...................................... 4 New Product Literature ........................... 4 Financial Results ........................................ 4 CORE Solutions Data Book ................... 5 Technical Training Update ..................... 5 PRODUCTS XC9536 ISP Demo Board ....................... 6 Low Cost XC5200 Family ....................... 7 XC9500 Price Reductions ....................... 7 Hi-Rel Product Roadmap ........................ 8 DSP LogiCORE Advantages ................... 9 DEVELOPMENT SYSTEMS Customer Declares Software “A Leap Forward” .......................... 10-12 JTAGProgrammer for ISP ................ 10-11 New CPLD Fitter Option ...................... 12 HINTS & ISSUES Technical Questions & Answers ......... 13 Technical Support Resources .............. 13 XC4000XL-1 Exceeds 100MHz ..... 14-16 XC9500 ISP and Teradyne Z1800 ..... 17 Are You Ready for 2 Million Gates? A Case Study .................... 18-19 Low Voltage Planning ...................... 20-21 HardWire Conversions .................... 22-23 Component Availability Chart ....... 24-25 Software Status ........................................ 26 Programmer Support Charts .......... 27-28 Alliance Contacts & Partners ............... 29 Alliance EDA Products ..................... 30-31 Fax Response Form ................................ 32 The Programmable Logic Company SM Inside This Issue: THE QUARTERLY JOURNAL FOR XILINX PROGRAMMABLE LOGIC USERS R X CELL Hi-Rel Product Roadmap The new development roadmap for high- density, high-reliability products will help Xilinx continue its leadership among QML- certified chip suppliers ... See page 8 DESIGN TIPS & HINTS PRODUCT INFORMATION New Software Called “A Leap Forward” Alliance partner Hollandse Signaalapparaten B.V. thoroughly evaluated the new Alliance Series Software and declared that “improvements have been made in all areas ...” See Pages 10-11 High Performance Design With The 100MHz XC4000XL-1 Using the world’s highest-density and fastest FPGA means designers must consider the special requirements of a chip that outpaces their design style ... See Pages 14-16 Are You Ready for 2 Million Gates? The day is coming when it will take 20-30 engineers a full year to fill a single super-dense chip, if designing from scratch... See Page 18-19
Transcript
Issue 26Third Quarter 1997
GENERALEditorial: What Do You Think? .............. 2
New Building in San Jose ....................... 2
Software Status ........................................ 26
Programmer Support Charts .......... 27-28
Alliance Contacts & Partners ............... 29
Alliance EDA Products ..................... 30-31
Fax Response Form ................................ 32
The ProgrammableLogic CompanySM
Inside This Issue:
T H E Q U A R T E R L Y J O U R N A L F O R X I L I N X P R O G R A M M A B L E L O G I C U S E R S
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XCELLHi-Rel Product RoadmapThe new development roadmap for high-density, high-reliability products will helpXilinx continue its leadership among QML-certified chip suppliers ...
See page 8
DESIGN TIPS & HINTS
PRODUCT INFORMATION
New Software Called “A Leap Forward”Alliance partner Hollandse Signaalapparaten B.V.thoroughly evaluated the new Alliance Series Softwareand declared that “improvements have been made inall areas ...”
See Pages 10-11
High PerformanceDesign With The100MHz XC4000XL-1Using the world’s highest-density andfastest FPGA means designers mustconsider the special requirements of achip that outpaces their design style ...
See Pages 14-16
Are You Ready for 2 Million Gates?The day is coming when it will take 20-30 engineers a full year to fill asingle super-dense chip, if designing from scratch...
XCell is published quarterlyfor customers of Xilinx, Inc.Xilinx, the Xilinx logo, XACT,FPGA Foundry, and NeoCADare registered trademarks;all XC-designated products,HardWire, XACTstep,LogiCORE, AllianceCORE,CORE Generator, FoundationSeries, Alliance Series,WebLINX, SmartSearch,Select-RAM, NGBuild, XABEL-CPLD, Zero+ and EZTag aretrademarks; and “TheProgrammable Logic Com-pany” is a service mark ofXilinx, Inc. All other trade-marks are the property oftheir respective owners.
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❝We are now
asking you to help us
improve XCell and
make it an even
more meaningful and
useful publication.❞
To accomplish this, we need your help. Forexample, what kinds of articles would you liketo see more of, or less of? Do you use thereference information printed in the back, suchas the component availability chart, or do youvisit WebLINX for the latest updates? Whatsections do you read most, and least? Whatcan we provide that will make a positivedifference and help you do your job better?Are you interested in submitting articles ofyour own, describing how you solved a com-mon problem or achieved a unique solution?This is your opportunity to influence the futureof XCell.
With your help, we will continue to pro-vide you with the best possible support.
Note: Bradly Fawcett, the editor of XCellsince 1993 (XCell #10), has left Xilinx to pur-sue even greater challenges. His contributionto Xilinx has been exemplary and we wishhim well. Great job, Brad! ◆
Xilinx AddsBuilding toHQ Facility
What Would You Like to See in XCell?XCell reaches well over 30,000 readers
worldwide. Our surveys show that most of youread XCell regularly, and keep it for reference,because it provides a wealth of useful andtimely information. We are now asking you to
help us improve XCell and makeit an even more meaningful anduseful publication.
In future editions, we intend toprovide more “how-to” informa-tion, including articles submittedby our technology partners show-ing you how to use their productsto develop Xilinx designs. Weintend to keep you informed of thefast changing trends and technol-ogy advances in our industry, soyou can be prepared. We intendto provide reviews, highlighting
the latest products, literature, and servicesavailable both from Xilinx and from our tech-nology partners. And, we intend to show youhow your peers are meeting their specificdesign challenges.
Due to our continuing success, we are expanding. Groundbreaking is now underway for a new building on our San Jose cam-pus. This new, two-story, 180,000 sq. ft. building on 9.8 acres, willhouse up to 700 people. This environmentally conscious, open-floor-plan, high-tech building will house the Xilinx Corporate staff, Sales,Marketing, Accounting, and Human Resources departments, amongothers. Construction is expected to be complete by August 1998. ◆
ARTIST’S RENDERINGCOURTESY OF DENNISKOBZA & ASSOCIATES, INC.
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3dustry to inspect blister packs and sort colortablets and capsules; in the automotive indus-try to verify that color fuses have been in-serted in the correct position in fuse blocks;and in the electronics industry to ensure thatLEDs, cellular phone keys,and pager buttons are thecorrect color.
“The primary reason forselecting ISP technology wasthat this part of our designwas extremely complex, andlarge functional blockscould be incorporated intosingle devices,” Goodspeedsaid. “During the debugprocess, hardware changescould be contained andfixed within a single Xil-inx XC9500 device, thenquickly evaluated byreloading the device through the ISP JTAGconnection. No messy rework and componentreplacements were required.”
System components include an embedded68060 processor, a PCI interface, vision pro-cessing ASICs, CPLDs, and FPGAs. The CPLDsimplement the major control logic, includingthe SDRAM controller and IO controller.
“Pin-locking and ISP have been key toupgrade flexibility of the Checkpoint 900Csystem. New product functionality can bedownloaded using the JTAG port,” saidGoodspeed. “Not having to remove a compo-nent eliminates any need for sockets andextra handling of the hardware if rework isever required.”
The XC9500 family is a proven winner,especially in those applications that take ad-vantage of the rock-solid pin-locking and ISPcapability for design re-programmability. ◆
At the world’s top machine vision com-pany, Cognex, designers of the new Check-point 900C have taken full advantage of theproven pin-locking capabilities and in-systemprogrammability (ISP) of the XC9500 family.This new line of machine vision and patternrecognition products greatly accelerates imageanalysis for color vision applications runningon high-speed production lines.
Based in Natick, Massachusetts, Cognex hasbeen using Xilinx XC9500 devices since early1996 in a multitude of new designs. It beganshipments of this new system in June 1997.
“XC9500 components are key to the Check-point 900C, Cognex’s first color vision proces-sor. Xilinx’s flexible pin-locking architecture,high-speed CPLD specs, and in-system pro-gramming capability have been instrumentalin the development of our latest Checkpointproduct. Changes to the design have beenquick to implement — the re-programmabilitythrough the JTAG port has allowed quicktransition from prototypes to production,”noted Cognex’s Steven Goodspeed.
Cognex has focused on keeping pace withever faster production lines, resulting in im-proved productivity, higher quality, and re-duced costs for manufacturers. The robustperformance and re-programmability of itssystems have fueled its worldwide popularity.
As the first full-scale color machine visionsystem designed for the PC, the Checkpoint900C is capable of a wide range of challeng-
ing machine visionapplications in anumber of majorindustries. For ex-ample, the Check-point 900C systemcan be used in thepharmaceutical in-
CUSTOMER SUCCESS STORY
CPLDs Provide Needed DesignFlexibility in Vision Systems
Cognex’s Checkpoint 900C color system.
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Learn about the newest Xilinx products and services through our extensive library of prod-uct literature. The most recent pieces are listed below. To order or to obtain a complete list ofall available literature, please contact your local Xilinx sales representative. ◆
NewProduct
LiteratureXilinx Packaging Guide Technical Data #100120
CPLD Pin-Locking Quick Reference Guide Technical Data #500855
Xilinx Education/Training Brochure Features & Benefits #0010134-07
Product Overview Brochure Features & Benefits #0010130-06
TITLE DESCRIPTION NUMBER
DSP World Expo /ICSPAT ’97September 15-17San Diego, CA
DSP FranceSeptember 17-19Paris, France
DSP GermanySeptember 30-October 1Munich, Germany
Look for Xilinxtechnical papers andproduct exhibits atthese upcomingindustry forums.For information aboutany of these confer-ences, please contactKathleen Pizzo:Tel: 408-879-5377FAX: 408-879-4676.◆
High-level Electronic Sys-tem Design Conference andExhibition (HESDC ’97)October 7-9San Jose, CAKeynote address by RichardSevcik, Senior Vice President,Software at Xilinx
FINANCIAL RESULTS
Revenues for the fiscal quarter endingJune 28, 1997 totaled $160.8 million, up 6%from $151.8 million in the fourth quarter ofthe prior fiscal year, and up 7% from $150.2million in the first quarter of fiscal 1997. Netincome was $33.4 million, up 10% from thepreceding quarter, and up 3% from the firstquarter of the last fiscal year. Gross marginrose to just over 62%, while operating ex-penses as a percentage of revenues de-creased relative to the preceding quarter.
“I continue to be pleased by the revenuecontributions of our new products whichconstituted nearly $7 million this quarter,”remarked Wim Roelandts, Xilinx chiefexecutive officer. “The XC9500 family ofin-system programmable (ISP) CPLDsdoubled in revenue this quarter, and the
high-density, high-speed XC4000XL familyis currently the fastest ramping FPGA in theindustry’s history. On the software side, weshipped approximately 1,700 revenue seatsthis quarter, and our new Alliance Seriesversion M1 software continues to be wellreceived in the marketplace.”
First quarter North American sales tomajor end markets were as follows: com-munications, 37%; data processing, 29%;and industrial, 15%. In addition, Xilinxcontinued to realize strong revenues fromnetworking companies, which representedan all-time high 15% of North Americanrevenues. Geographically, revenues fromNorth America, Europe, and Asia/Pacificwere up sequentially, while revenues fromJapan declined. ◆
New Products Lead 3Q97 Growth
Xilinx Inc.stock is traded
on the NASDAQexchange under
the symbol XLNX.
5
Xilinx distributors worldwide offer thesesame courses at regional or local sites. Fordates and locations, check with your distribu-tor, see the Xilinx Educational Services bro-chure, or visit the training section under “sup-port” at WebLINX(www.xilinx.com).
The 1997 brochure wasupdated at the end of July.It describes the contents ofeach training course andthe latest dates (at time ofpublication) of scheduledtraining courses.
The customer educa-tion group will continue to develop new train-ing courses to address future Xilinx softwarereleases and the needs of ourcustomers. ◆
The new Alliance Software version M1Tools Course and the Alliance Software ver-sion M1 Update Course are now being offeredon a regularly scheduled basis worldwide.
The Alliance M1 Tools Course, for newusers, is two-and-a-half days long. The Alli-ance Software version M1 Update Course, forexisting users, is one day long.
The dates for these courses, held at theXilinx San Jose facility, are:
TECHNICAL TRAINING UPDATE
Training Now Available Worldwide
Alliance Softwareversion M1 Tools:• August 5, 18• September 9, 15• October 13, 27• November 3, 17• December 1, 17
Alliance Softwareversion M1Update:• August 1, 25• September 5, 22• October 6, 20
The new data book focused on program-mable logic cores and related products pro-vides one definitive source and detailed prod-uct descriptions. Xilinx CORE Solutionsimprove both time-to-market and deviceutilization. They include:
➤ LogiCORE™ products - PCI, DSP, and theCORE generators.
➤ AllianceCORE™ products - Completesolutions for PCMCIA, USB, and Reed-Solomon, plus eight other cores and devel-opment tools from third-party partners.
➤ LogiBLOX™ - Parameterized smallbuilding blocks.
➤ Reference Designs - A listing of allapplication notes on WebLINX accompa-nied by design files.
Pages 5 and 6 in section 1 list all of thefunctions described in the catalog by applica-tion segment, and are your best guide tolocating a specific product that is available
New CORE Solutions Data Book Available
NOTE: New products and updates,made since the last publish date,can be found on WebLINX athttp://www.xilinx.com/products/logicore/logicore.htm
today. If you don’t see what you need, checkthe Areas of Expertise in the profiles of ourAllianceCORE partners, starting on page 3-75.Our partners are happy to discuss the possibil-ity of making a core for your specific needs.
The entire catalog can be downloadedfrom WebLINX at: http://www.xilinx.com/products/logicore/core_sol.htm
To order a hard copy, requestthe CORE Solutions Data Book bycalling 1-800-231-3386 (U.S. only)or 408-879-5017 (worldwide)or e-mailing your request [email protected]. ◆
New XC9536 ISP CPLD Demo Boarddown, for example). Once the new design hasbeen processed, you can immediately repro-gram the demo board to test the change. Thisquickly shows that the pinouts can remainlocked, even after making design changes.
We have an application note to support thedemo board as well. It includes a description ofoperation, a schematic, VHDL and ABEL demofiles, and stock numbers for all components. Itis available now by visiting WebLINX(www.xilinx.com/apps/epld.htm). You canselect application note number XAPP078, theXC9536 ISP Demo Board, and the associatedVHDL or ABEL Johnson shift counter demofiles. To process the ABEL demo file, use theXilinx Foundation Series software. To processthe VHDL file, use the Alliance Series software.
Programming the demo board can beaccomplished using either the Xilinx EZTagsoftware, or the new JTAG programmer soft-ware contained in the Foundation or AllianceSeries Software.
You can order the demo board, partnumber HW-CPLD-DEMOBD, by contactingyour local Xilinx Distributor. ◆
Designers may use the new XC9536 in-system-programming (ISP) demo board toprototype, debug, and troubleshoot smalldesigns. When used with the new FoundationSeries or Alliance Series software, the boarddemonstrates the benefits of combining arobust pin-locking architecture with ISP.
The board includes an XC9536-VQ44CPLD, 555 surface-mount oscillator, eightsurface-mount LEDs, a JTAG interface, and a
sea-of-holesprototyping area.
The eight sur-face mount LEDsare connected tothe right side ofU1, the XC9536CPLD, as shown inFigure 1. Asample design for
a Johnson shift counter is included, produc-ing a shifting LED pattern.
As a test of the XC9500 family pin-lockingcapability, the design of the Johnson shiftcounter can be easily modified to generate adifferent LED pattern (counting up instead of
Figure 1: ISP Demo Board
Find it on the Web at:www.xilinx.com/apps/epld.htm
The XC5200 family is now shipping intonew, high-volume applications such as CDplayers, PC add-in cards, set-top boxes andpersonal communications devices. Because ofcost sensitivity, many of these applicationshave relied on gate arrays in the past. Successin these markets has rocketed sales of theXC5200 family to a million units, in recordtime—twice as fast as any previous device.
According to Masato Yorifuji, senior engi-neer for Hitachi, Ltd., Japan, “… . while de-signing the world’s first MPEG camera fordigital photography, we needed the advan-tages of re-programmability to deliver leadingedge products to the market. Although wehistorically considered only a mask-pro-grammed solution for our product, the XilinxXC5200 family delivered a compatible cost-per-logic-cell and reduced our time-to-pro-duction by six months.”
Matrox Graphics, a Montreal-based com-pany whose sales of PC graphics add-in cardshave more than doubled each of the last threeyears, has selected the Xilinx XC5204 device
XC9500 Family Price ReductionsEffective September 1, the prices for
the XC9500 CPLD family have been reducedup to 30%, depending on speed and pack-age. The price reductions result from im-provements in wafer yields and manufactur-ing efficiencies, along with dramaticincreases in production volumes.
Now it is easier for designers to takeadvantage of the most advanced CPLDtechnology available. For example, price isno longer a barrier to using in-system
programmability (ISP) because the ISP-–capable XC9500 family is now the same priceor lower than other non-ISP devices.◆
for the high-volume RainbowRunner daughtercard, used onthe Matrox Millenium. TheXC5204 was chosen for thisconsumer application because ofits low cost, high I/O count andreprogrammability. Plus, furtherdesign changes are possiblesimply by providing a new soft-ware driver because the XC5204configuration data is part of the driver. Thisallows the board to change not only software,but also hardware, to adapt to the latest 3Dand video applications. Configuring from thedriver also eliminates the need for a serialPROM, further optimizing board space.
The XC5200 family has succeeded in re-placing low density gate arrays where otherPLD vendors have failed because it leveragesleading-edge process technology with specificarchitectural innovations that minimize diearea and cost.
Ask your local Xilinx sales representa-tive for more information. ◆
Even as defense spending continues todecrease, the funds devoted to electronics for“smart” weapons and defense systems areexpected to grow. Designers in the Hi-Rel/Military applications market are spendingwisely, focusing on development time andtime-to-market in a highly competitive indus-try, and using the latest technologies.
Xilinx has created a high-density FPGAroadmap that, in conjunction with QML certifi-cation, makes Xilinx FPGAs the technology ofchoice for defense system designers.
As it becomes more and more difficult toobtain Hi-Rel ASICs, high-density FPGAs willbecome the standard for Hi-Rel logic design.This will be accomplished by focusing onselected products and offering both through-hole and surface mount packaging options.
Xilinx is already shipping the industry’slargest QML-compliant FPGA — the 25,000-gate XC4025E device.
With the trend towards lower supply volt-ages, the 3.3 volt XC4000XL family is destinedto become the flagship of the Xilinx Hi-Relproduct lines. The 62,000-gate XC4062XLFPGA will be available as a QML product inthe first half of 1998.
Out strong product leadership will befurther enhanced with the 2.5 volt, 125,000-gate XC40125XV device before the end of1998, followed by a third generation familythat will provide up to 400,000 gates of QMLprogrammable logic in 1999.
Because FPGAs solve many of the prob-lems facing the defense electronics industry,they have been successfully designed intohundreds of military and aerospace applica-tions, such as electronic warfare, counter-measures, missile guidance, radar, sonar,communications and avionics systems. ◆
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is completed to determine if your systemrequirements were met. The Xilinx segmentedrouting does not have this problem andtherefore timing is always predictable, asillustrated in Figure 3.
Xilinx CORE Solutions and the new COREGenerator, provide predictable, consistent,high-performance designs that get your prod-uct to market in the least time with the leasteffort. See our CORE Solutions Data Book formore information. ◆
The Xilinx CORE Generator, in conjunc-tion with the XC4000XL segmented architec-ture, automatically produces highly efficientDSP designs that are predictable for any sizedevice. Xilinx is the only FPGA supplier thatcan achieve this.
In the past, high-level VHDL designs(originally intended for gate arrays) could beused in FPGAs, but they produced inefficient,slow, and unpredictable results. Now, usingthe DSP LogiCOREs that are created fromyour design specifications, you can get per-formance and density that is equivalent tohand crafted designs.
In addition to logic design, the COREGenerator also produces a physical layout foreach parameterized core, containing relativeplacement information for each CLB. Oncethe CLBs are mapped and placed relative toeach other, multiple cores can be droppedinto a Xilinx FPGA and still meet the pre-defined performance specifications of eachindividual core. This is made possible by ourunique segmented routing architecture.
Xilinx is the only FPGA manufacturer thatproduces a physical layout in parallel with thecore logic design. Our competition uses coresthat must rely on the place and route softwareto build the physical design each time theyare used. And, their non-segmented routingarchitecture means you cannot predict perfor-mance, which decreases as more logic isadded to a device and varies between differ-ent software runs, as shown in Figure 1.
The Xilinx core performance is also inde-pendent of device size. For example, a 12x12parallel multiplier achieves the same maxi-mum clock rate when it’s used in anXC4005XL as when it’s used in an XC4085XL.Our competitor’s non-segmented architecturecannot achieve this because their metal inter-connections get longer as the device sizeincreases, as illustrated in Figure 2. Becauseof this, our competitor’s core performancecannot be specified or controlled during thedesign phase; you must wait until the design
Xilinx DSP LogiCORE Advantages
Figure 1: Ourcompetitor’sFPGAs exhibitperformancedegradation asthe device sizegrows, due to theincreased capac-itance of longnon-segmentedinterconnections.
Figure 2: TheXilinx segmentedrouting guaran-tees consistentperformanceas more logicis added.
Figure 3:Segmentedrouting and theXilinx COREGeneratorguaranteeconsistentperformancebetween smalland large FPGAs
Competitor’s Cores Run Slower asPart Size Increases
PERF
ORM
ANCE
MH
z(1
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mul
tipl
ier
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Number of claimed gate equivalents
Xilinx Core Performance isIndependent of Part Size
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z(1
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ier
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XC4005 XC4013 XC4028 XC4044 XC4085
PART TYPE
12x12 Multiplier(Xilinx Area Optimized Core)
PERF
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z 80 ––––––––––––––––––––––––––––––
70 ––––––––––––––––––––––––––––––
60 ––––––––––––––––––––––––––––––
50 ––––––––––––––––––––––––––––––
40 ––––––––––––––––––––––––––––––
1 2 3 4 8
NUMBER OF INSTANCES
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Xilinx XC4000Family (segmented)
Competitor (non-segmented)
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PRODUCT INFORMATION-DEVELOPMENT SYSTEMS
Signaal Evaluates the Xilinx Alliance Series Software Tools
Hollandse Signaalapparaten B.V.(Signaal), a subsidiary of Thomson-CSF, recentlyperformed an evaluation of the new AllianceSeries software. The design was for an interfacebetween an MC68360 CPU and a SHARC busrunning at a clock frequency of 25 MHz, andwas implemented in an XC4010E-4PQ208FPGA. About 70% of the CLBs and 80% of theIOBs were used. All I/O pins were locked to
“A Leap Forward”
forms (Sun, HP, PC). The same GUI can be usedto download either via the parallel downloadcable (JTAG) or serial download cable (XChecker)as well as being used to generate serial vectorformat (SVF) files for easy interfacing to embed-ded processors, automatic test equipment, orthird-party tools.
As with EZTag, JTAGProgrammer provides asimple-to-use interface that shields the end userfrom the intricacies of the boundary-scan protocol.JTAGProgrammer, however, adds more flexibilityincluding the support of additional programmingoptions like:
New JTAGProgrammer Software for ISPThe new JTAGProgrammer tool repre-
sents a major step forward in the evolution ofin-system programming (ISP) download andtest software.
Using the new JTAGProgrammer graphicaluser interface, designers have immediate ac-cess to all of the ISP functionality provided byXC9500 CPLD 1149.1-compliant devices. Thestructure of the boundary-scan chain is readilyvisible and the status of each part in the chainis clearly indicated on the topology diagram.
The JTAGProgrammer user interface isidentical in its look and feel across all plat-
enable concurrent design of the PCB layout.The evaluation used the Synopsys FPGA
Compiler for synthesis, and the CadenceLeapfrog simulator for behavioral (RTL), func-tional, and timing simulation. However, anysynthesis tool and VITAL-compliant simulatorcould have been used because all interfacesare based on standard formats such as VHDL,SDF, and EDIF. See “design flow” at right.
The Customer Evaluation ReportControllability of the Tools
“The controllability has been improvedusing the flow engine and user-definabletemplates. Design constraints can be specifiedduring synthesis (netlist constraints) andduring place and route (user and physicalconstraints). Constraint-driven place androute is essential for timing-critical, high-density designs.”
Jaap Mol of Signaal wrote, “The newAlliance Series software is a leap forward;improvements have been made in all areas.”His report included many other key insights:
Usability of the Software“The usability has been improved by the
new GUI. It is intuitive and allows for bettercontrol, which is especially important for thefirst time user of the tools.”
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➤ Ability to skip erase beforeprogramming.
➤ Automatic detection of new XC9500silicon features.
➤ Ability to override write protection.
➤ Automatic detection of programmingcharacteristics of silicon.
JEDEC files generated from XACTstepversion 6.X software are 100% compat-ible with JTAGProgrammer so you can use yourarchived JEDEC files without modification in thenew JTAGProgrammer environment.
JTAGProgrammer runs on SunOS 4.x (Solaris1.X), SunOS 5.X (Solaris 5.X), HP UX 9.X and10.X, Windows 95, and Windows NT 4.0. ◆
Interface Formats to Other Tools“The interface to and from Xilinx tools is
dramatically improved by the move to stan-dard formats like EDIF, VHDL, and SDF. Thiswas the major reason why the interfaces fromthe synthesizer and simulator did not causeany major problems. The availability of a
Version and Revision Control“Version and revision control capability have
proven to be very useful in performing design trade-offs. The best possible solution for the design can beselected from implemented versions and revisions.This is especially useful when using Xilinx FPGAtechnology to do rapid prototyping of a system. TheDesign Manager offers the capability for doing ver-sion and revision control on designs. In the DesignManager a design is referred to as a project. If therehave been changes to a logic design (e.g. thenetlist), this is referred to as a new version of thedesign. If the design is mapped into another device,package, or speed-grade, this can be referred to as anew revision. This way, the user can easily maketrade-offs, without losing previous results.”
Report Browsing“During implementation of the design, many
reports are generated. For instance, there arereports concerning timing, place and route,and pad assignments.”
On-Line Help“The on-line help is available from within the
design manager. The help function is based onWindows Hyperhelp, has a search function, and iseasy-to-use.”
The Signaal Design Flow:➤ A VHDL (RTL) model was verified using the VHDL simulator.
This model also functioned as an input for logic synthesis.
➤ The synthesis tool translated the VHDL model to gates. (Therequired synthesis libraries are provided by Xilinx or the synthe-sis tool vendor.)
➤ An EDIF netlist was generated during synthesis, containing theconnectivity between Xilinx primitives. This netlist was latertransferred to the place and route software.
➤ Optionally, functional (pre-layout) simulation could be per-formed using the Xilinx VITAL library, to verify the correctnessof the synthesis process before proceeding with place and route.
➤ The EDIF netlist was processed by the place and route software.After place and route was completed, a VHDL netlist and SDFtiming information were generated. These were used for TimingSimulation, once again making use of the Xilinx VITAL library. Inaddition, static timing analysis was performed during synthesisand during place and route.
Continued onthe following page
12
The new Alliance Series and FoundationSeries software contain a CPLD fitter optioncalled “use advanced fitting.” This new featureallows the software to group equations thathave the same input signals into the same func-tion block. You would typically use this option
on large designs that cannot fit because offunction block input restrictions.
If your design is unable to fit into a particu-lar device, take a look at the top of the report(.RPT) file. Designs which appear to haveplenty of I/O pins, product terms, andmacrocells when mapped into an XC9500device may not fit because of the 36-signalinput limit to each function block.
New Alliance and Foundation CPLD Fitter OptionIn the example in Figure 1, we see that
almost all of the FB inputs are being used.However, the total number of product termsand macrocells in each function block are notfully utilized. This would be a perfect candi-date for trying the “advanced fitting” algorithm.
What exactly does this new algorithm dodifferently? There are 36 inputs to a functionblock in the XC9500 CPLD architecture. TheCPLD fitter software will default to fitting de-signs based on a pin-locking algorithm. Thispin-locking algorithm tends to spread equa-tions throughout the CPLD, ensuring room forgrowth and change for all of the equations.
This spreading function, however, tends touse up the number of function block inputsvery quickly. By selecting the “advanced fitting”algorithm, the software weights common signalusage higher and tends to group equations withthe same signals into the same function block.As a result, it provides a denser fit for largerdesigns by freeing the otherwise used inputsfrom other function blocks. ◆
➤ “The PROM file formatter generates oneor more PROM files in a suitable formatfor an EPROM programmer. It can mergemultiple bitstreams into the resultingPROM files. Both serial and byte-widePROMs are supported.
“It is quite visible that Xilinx has put a lotof effort into the development of this release.The new tools are intuitive, have good con-trollability, and support industry standards.The support of industry standards makes theinterface to third-party EDA vendors easy andseamless. The tools helped cut down ourdesign time significantly, which translatesinto reduced time-to-market. We hopeXilinx will continue investing resourcesin this direction.” ◆
VITAL-compliant VHDL library makes it pos-sible to use one testbench, one simulator, andone language for simulation on any level ofabstraction.
“Apart from the tools, which are calledfrom the flow engine, the following functionsare also available:
➤ “The timing analyzer provides a timinganalysis of specific paths in the design, andhelps to verify that the timing constraintsare met by the place and route tools.
➤ “The epic design editor can be used tomanually place and route any or all partsof the design.
➤ “The hardware debugger provides aninterface to the XChecker cable, which canbe used for reconfiguring an FPGA, whileprototyping the system.
A LeapForward
Continued from theprevious page
13
TECHNICAL QUESTIONS & ANSWERS
If you have either a Foundation Series STD-V or BAS-V package, you will need to have aXilinx hardware security key attached to your PC’s parallel port in order to enable the VHDLfeatures of the product. Existing Foundation Series VHDL customers may use their existing keywith the Foundation Series version M1.3 software. New Foundation Series VHDL customerswill receive a pre-programmed hardware key with their new software.
As long as the XACTstep version 6 implementation software remains installed on your sys-tem (located in C:\XACT by default), and the XACT variable and path point to this location,you will still be able to target XC3000/A and XC5200 devices with the Foundation Series tools.
When you open an existing Foundation Series project, targeting an XC3000/A or XC5200device, it will ask if you wish to enable the XACTstep v6 flow. Once the XACTstep v6 flow isenabled, the Foundation Project Manager will revert back to the XACTstep v6 menus, and willlaunch the XACTstep v6 Design Manager instead of the Foundation Series Design Manager.
The project type can always be switched between the XACTstep v6 and Foundation Seriesflows by selecting “file ➡ project type” from the Project Manager.
If the XACTstep v6 flow is not listed as an available project type, and you wish to create anew project targeting either an XC3000/A or XC5200 device, add the following lines to thebottom of the SUSIE.INI file, located in the Windows directory:
[Flow_26] XILINX6=ON
If the desired libraries are no longer present, they must be copied from the Foundation6.0.1 CD-ROM from the \ACTIVE\SYSLIB directory to C:\ACTIVE\SYSLIB (where C:\ACTIVEis the location of the Foundation Series Design Entry software), and manually added to theFoundation Series project by selecting “file ➡ project libraries” from the Project Manager,and adding the appropriate libraries.
Will I still be able totarget XC3000/A andXC5200 devices with
the FoundationSeries software?
Do I still need ahardware key with the
Foundation Seriessoftware?
The Foundation Series version M1.3.7 includes Verilog and VHDL compile scripts that runthe HDL-compilation commands automatically.
For more information, see the files:
$XILINX/mentor/data/verilog/README
$XILINX/mentor/data/vhdl/README
How do I compile theFoundation Series HDL
simulation libraries so Ican perform timing or
post-synthesissimulation in QuickHDL?
1. Find us on the Internet at www.xilinx.com— We update our “Answers” Web tool dailywith the latest application notes, data sheets,patches, and solutions to your technical ques-tions. Get immediate answers 24 hours per day!
In addition to being the world’s highestdensity FPGAs, the Xilinx XC4000XL-1 family isalso the world’s fastest. They offer greater than100 MHz internal system clocks and more than70 MHz in I/O speed. This combination ofspeed and density comes with low power andtotal compatibility with 3.3 volt or 5.0 volt logic.
The increase in speed can be quite sub-stantial. Designs for the XC4000E-3 family willrun 80-100% faster on the equivalentXC4000XL-1 devices. The pin compatibilityamong all XC4000 Series devices makes itsimple to test actual design speeds — just re-target any design for an existing XC4000 Se-ries FPGA to the appropriate XC4000XL-1device using the Alliance Series or FoundationSeries software.
Article SummaryThis article describes the achievable perfor-
mance (maximum clock frequency) in top-of-the-line FPGAs. It analyzes the performance ofseven typical sub-functions and lists theachievable performance levels for the fastestavailable Xilinx XC4000XL device, comparedwith the fastest available Altera 10K100 device.All data was derived from the manufacturers’worst-case timing analyzer.
The remainder of this article describes thedramatic performance impact of three differentdesign styles. It shows that you can oftendouble the performance of the FPGA byspending some effort on optimizing the designstructure for the specific FPGA architecture.
DESIGN HINTS AND ISSUES
R
High Performance Design
XC4000XL-1 FPGAs Exceed 100MHz
Selected Component Frequency Measurements FREQ. EXPLANATION XC4062XL-1 10K100-3
Fmux(2) 64:32 Mux between registers 131 MHz 105 MHz
Fmux(8) 64:8 Mux between registers 80 MHz 60 MHz
Fmxu(64) 64:1 Mux between registers 56 MHz 38 MHz
Fequ(4) 16 x 4 bit AND terms between registers 164 MHz 86 MHz
Fequ(16) 4 x 16 bit AND term between registers 81 MHz 54 MHz
Fequ(64) 1 x 64 bit AND term between registers 30 MHz 17 MHz
Fadd(1,5) 5-bit adder between registers 135 MHz 148 MHz
Fadd(1,32) 32-bit adder between registers 73 MHz 43 MHz
Fmem(16) 16 Bit 16 element dual port RAM 128 MHz nabetween registers
Fmem(128) 16 Bit 128 element dual port RAM 68 MHz 25 MHzbetween registers
Fmem(1024) 16 Bit 1024 element dual port RAM 40 MHz na between registers
An expanded version of this article is available on WebLINX (www.xilinx.com),as an application note, under the title “Speed metrics for high performance FPGAs.”
❝This combination of speed and density comes with
low power and total compatibility with 3.3 volt or 5.0 volt logic.❞
FREQ. EXPLANATION XC4062XL-1 10K100-3
Fio(int) Clocked I/O referenced to internal clock 196 MHz na
Flut(4,4) Four cascaded 4LUTs between registers 73 MHz 49 MHz
Flut(4,8) Eight cascaded 4LUTs between registers 36 MHz 27 MHz
15
To determine the maximum speed of thecomponents used in FPGA designs, a set oftest designs was created. These designs, writ-ten in VHDL, measure fundamental aspects ofFPGA performance. The following compo-nents were entered and tested for frequency:➤ I/O – three configurations of I/O pins and
clocks.➤ Interconnect – registers separated by
“N” rows and columns.
➤ State Machines – 1 to 6 levels (3-, 4-, and5-input look-up tables).
➤ Constant Comparators (“AND” terms) –4-, 8-, 16-, 32-, and 64-bit AND terms.
➤ Adders – 4-, 8-, 16-, 24-, and 32-bit addersas well as 2- and 4-bit cascaded adders.
➤ Memory–Dual Port RAMs, 16-bits wide; 16-,32-, 64-,128-, 256-, 512- and 1024-bits deep.
FPGA Design Style Affects PerformanceIn general, FPGA designs with a low ratio
of registers to look-up tables (LUTs) run atlower clock rates than designs with equalnumbers of registers and LUTs. Even higherclock rates can be achieved if additionalregisters are used to break up interconnectdelays. Design styles can be characterized aslow, medium, and high frequency based onthe register-to-LUT ratio. They might also becalled “easy,” “medium,” and “difficult.” It isimportant to understand that this difference isnot affected by the design entry method. It isjust as easy to include registers in a VHDLdesign as in a schematic. In fact, high-leveltools can include register re-timing methodswhich can significantly increase system fre-quency.
“No Problems” Design StyleIf you’ve ever done a low-speed design
for an FPGA, you know how convenient it isto ignore logic depth, pipelining, and place-ment issues. Logic synthesizers will oftengenerate designs in this style becausepipelining and logic placement are not auto-matically handled. The “no problem” designstyle requires that timing and placement notbe an issue; if the design passes functionalsimulation, then it will route and meet thenon-demanding timing.
FPGA System Frequency DefinitionsFor maximum frequency designs, the type
of functionality available to you is restricted.In fact, the types of components that run atthe same maximum frequency can be used todefine these design styles in a formal sense.
Medium Frequency FPGA Design StyleMost designs intended for FPGAs fall into
this design style. Your designs will tend to fallinto this category, if you use one-hot statemachines, Global Low Skew (GLS) bufferedclocks, register all your big data-path compo-nents, and practice moderate floor-planning.
High Frequency Design StyleA high clock frequency allows little margin
for such things as routing delay or carry propa-gation. To work at this level, the physical as-pect of a design must be considered. It maymean adding registers to cover interconnectdelay, or detailed floor-planning.
16
The components can be adders, I/O pins,state machines, or anything else you canbuild in an FPGA. For proper operation, allthe components used must run at the selectedsystem frequency. Ifthe types of compo-nents used in a designare known, you canestimate the speed ofa new design withoutdetailed knowledge ofthe actual design.Alternatively, you canlimit the types ofcomponents used in adesign to insure hit-ting a target fre-quency.
The following tabledefines the types ofcomponents that are
HighPerformance
DesignContinued from the
previous page
Component Parameters Defined High Freq. Medium Freq. Low Freq.
State machines Number of cascaded 4LUTs 2 Logic Levels 4 Logic Levels 8 Logic Levels
Multiplexers Number of input bits/ Number of output bits 64-bits/32-bits 64-bits/8-bits 64-bits/1-bit
“AND-OR” Number of Inputs bits/ 4-bit/1 level 16-bit/1 level 64-bit/2 levelsTerms Number of cascaded AND-OR terms
Adders Number of input bits/ 4-Bit/1 level 32-Bits/ 1 Level 32-Bits/4 LevelsNumbers of cascaded adders
Inputs/Outputs Type of Input/Type of Output/ “NoDelay” inputs/ “Full Delay” inputs/ “Full Delay” input via 4LUT/Timing Reference for Clock “Fast” outputs/ “Fast” outputs/ “Slow” Outputs via 4LUT/
Memory Number of locations Dual Ported Memory 16-elements 128-Elements 1024 Elements
Interconnect Distance between registers 4 CLBs 64 CLBs 128 CLBs
a design style are measured, then the systemfrequency is determined. The system frequencyis defined as the minimum speed of all thecomponents necessary for each design style.To illustrate the point that Xilinx XC4000XL-1devices are the world’s fastest high-densityFPGAs, these same measurements were madefor a competitor’s FPGA; the Altera 10K100-3device is roughly the same size as the XilinxXC4052XL. ◆
System Frequency MeasurementsThe system frequencies for the three asso-
ciated design styles can now be measured.First the component frequencies required for
Frequency Design Style XC4062XL-1 10K100-3
Fmax High Frequency 128 MHz 82 MHz
Ftyp Typical system 68 MHz 43 MHz
Fmin Low frequency 28 MHz 17 MHz
available within each design style; the se-lected components are generally compatiblewith each other, and a formal definition al-lows frequency measurements to be taken.
17
➤ A C compiler capable of producing a16-bitDOS executable for the Z1800. The com-puters provided with Teradyne board testsystems support Microsoft Visual C++ andBorland Turbo C++ version 3.0 compilers.
Integrating XC9500 ISP Capabilities WithManufacturing Test on the Teradyne Z1800In-system programming (ISP) allows you
to program and re-program devices that arealready soldered on a system board. ISPstreamlines manufacturing flows, allows youto update and reconfigure remote systems,and makes prototyping much easier. TheXC9500 family integrates ISP functionalitythrough the IEEE 1149.1 (JTAG) test accessport without requiring any externally appliedvoltages greater than 5V. This allows JTAG-compatible automatic test equipment, such asthe Teradyne Z1800, to program XC9500devices.
Z1800 Configuration and FixturingThe Teradyne Board Test System performs
ISP as an integrated part of the manufacturingtest process. In order to integrate program-ming into the system test flow, you need:
➤ A Teradyne Z1800 tester with the digitalfunctional processor board running the F1software.
➤ The Xilinx EZTag or JTAGProgrammersoftware.
➤ The zip file containing the Teradyne SVFPtranslator, C files, and software libraries(downloaded from WebLINX).
AvailabilityThe svfp translator, C files, libraries, and
accompanying documentation are availableon WebLINX (www.xilinx.com), the XilinxWeb site. Point your browser to http://www.xilinx.com/apps/isp.htm and select thetopic titled Programming Xilinx XC9500 on a
Teradyne Z1800 with DFP -EZTag Version.
Xilinx now offers you fullJTAG/ISP support for the topthree ATE manufacturers:Teradyne, HP, and GenRad. Thenecessary software and docu-mentation for all three ATEplatforms is available free ofcharge from WebLINX.
With complete ATE supportand the industry’s most exten-sive JTAG capability, Xilinx isthe ISP CPLD vendor ofchoice. ◆
Find it on the Web at:http://www.xilinx.com/apps/isp.htm
Just as it’s easier to paint by numbers, it’s easier tore-use blocks of logic. The use of intellectualproperty or core-based design modules is anessential component of a high-end “system on achip” solution. The LogiCORE and AllianceCOREmodules from Xilinx offer proven, pre-imple-mented, and fully verified cores that provide thefast time-to-market solutions you need.
This article demonstrates the use of technol-ogy-independent intellectual property (IP) throughthe design of a Universal Serial Bus application.
By the year 2000, Xilinx will be producingdevices containing more than 100,000 logiccells (2 million gates). You will soon have acanvas so broad that it will be difficult to paintall the landscape. We estimate that it will take afull 12 months and 20-30 engineers to fill adevice of this density, if designing from scratch.
Clearly the solution to maintaining atrouble-free design cycle is to stop creatingevery design from scratch, and to start usingtechnology-independent intellectual property.
Using Technology-IndependentIntellectual Property Are You Ready for 2
UniversalSerial Bus
Case Study
The Universal Serial Bus (USB) protocolwas created to provide a standardized serialbus to be used in the personal and mobilecomputer markets. Just as PCI is becoming astandard parallel bus, USB is now becoming astandard PC serial bus for lower-bandwidthPC peripherals such as mice, keyboards,modems, and so on.
USB Protocol DescriptionThe USB protocol uses a differential-
twisted shielded pair for its physical medium.The signal coding is NRZI with bit stuffing,and has been designed to transmit data attwo rates: 1.5 Mbps (low speed) and 12 Mbps(full speed). It can support up to 127 devices.
The USB architecture defines a host PCand “devices” or “functions” (such as key-board or mouse) with “hubs” in the middle asnecessary for fan-out.
Verilog HDL USB Design GoalsMentor Graphics Inventra, a member of the
Xilinx AllianceCORE partnership, has developed afamily of USB functions and hub controller softcores. These cores can be combined with applica-tion-specific back-end logic.
Inventra USB cores come in low speed and fullspeed versions for applications such as micro-control-lers, audio, and generic user definable USB interfaces.These cores have been designed with the followinggoals in mind:
➤ A technology independent design methodology.
➤ Design implementation and mapping directed bysynthesis timing constraints.
➤ Synthesis tools select state machines.
➤ Ability to re-use the bus interface with applica-tion-specific logic.
For this USB case study, an Inventra USB func-tion controller core was selected. The USB functioncontroller’s hierarchy and logic was originally de-signed with its full-speed timing characteristics inmind. The USB function controller’s hierarchy isillustrated in Figure 1.
While the full-speed USB Function Controller runsat 12 MHz, the design involves several blocks that runat 4X the basic rate, or 48 MHz. This 48 MHz clock is
19
used to over-sample and drive both the data andthe 12 MHz data clock from the serial NRZI USBdata signal.
Controlling TimingThe design’s logic was divided into different
timing blocks as illustrated in Figure 2. This wasdone to understand the timing relationships bothwithin and between blocks of logic.
By implementing the design using these timingblocks as the hierarchical boundaries, the Inventraengineers where able to clearly define timingspecifications and constraints for the blocks oflogic that needed to run at a rate of 48 MHz andthose that needed to run only at 12 MHz. Theywere also able to control the timing interactionbetween these blocks.
By using the Xilinx Alliance series timing con-straint capability, the global timing of 12 MHz wasapplied to the entire design. Then the more criticalconstraint of 48 MHz was applied to the flip-flopsand I/O pads that needed to run at the 4X rate.
State MachinesThe synthesis tools were also used to select the
most efficient and highest performance state ma-chines. The USB function controller consists of,among other things, five state machines. TheInventra engineers found that two of the statemachines would not meet the system timing re-quirements if standard encoding methods wereused for synthesis. By directing the synthesis toolsto use “one hot” encoding for these two machines,performance requirements for these two blockswere met. To maintain the core’s design re-usecapability, the Verilog RTL code was not modified;only the synthesis options were changed.
Module Re-useBy developing the USB function controller as a
reusable IP, Inventra is able to maintain a singleversion of RTL source code with a range of inter-facing options for various back-end applications.This back-end application logic can also be devel-oped using this technology independent method-ology, allowing the modules to interface easily.
SummaryThis USB IP development case study shows
how generic Verilog RTL code was used todefine the register transfer level functions whilesynthesis was used to produce the gate levelimplementation. The constraint files and direc-tives are used to drive both the synthesis andthe Alliance Series place androute tools.
In this technology-inde-pendent IP design flow, theXilinx design tools used thenew timing-drivenplacement androuting algorithms.The robust timinganalysis tools werealso used to verifythat the timing requirementswere met. There was nohand placement or routing,and no floor-planing wasrequired.
The use of this technology independentmethodology will become more and moreimportant as device densities increase. Xilinxis committed to delivering not only the high-est performance and highest density devices,but also to providing you with the tools youneed to develop them quickly and easily.
For information on the XilinxLogiCORE, AllianceCORE, or MentorGraphics Inventra USB products, checkout the Xilinx CORE Solutions web site at:http://www.xilinx.com/products/logicore/logicore.htm ◆
To demonstrate the importance of good Vccdecoupling, assume that you have a 40 MHzclock and the device consumes 1 amp. Most ofthe current flow will be in the first 5 ns of the25 ns clock period. This 5 amp peak currentmust be supplied by the sum of the decouplingcapacitors. In this example, 5 amps times 5 nscauses a 250 mV drop on a 0.1 µF decouplingcapacitance, creating a possible problem. Hereare some recommendations:
➤ Decoupling capacitors must have very lowinductance and series resistance. The totalcapacitance value is less important, as longas it exceeds 0.1 µF. The best way to achievelow impedance at gigahertz speeds is to usemultiple capacitors in parallel. Use 0.01 to0.1 µF ceramic capacitors mounted veryclose to each Vcc pin and directly connectedto the ground plane.
➤ Signal lines must be kept short. A narrow,0.25 inch (6 mm) trace represents an induc-tance of 20 nH. A current transient of 100mA/ns causes a voltage drop of 2 volts acrossthis inductance, which is unacceptable.
➤ Some PC boards can use an extremely thindielectric layer between the ground and Vccplanes to achieve excellent distributeddecoupling capacitance.
➤ Ground bounce, cross-talk, and other externalnoise must be minimized. Xilinx provides aslew-rate-limited output option, individuallyprogrammable for each pin, so you can slowthe transition rate on all non-critical outputs.
Interfacing Between Deviceswith Different Supply Voltages
Because all supply voltages share a commonground, there are no problems interfacing at Lowlogic levels. All potential problems occur wheninterfacing at High logic levels. For example:
➤ 3.3 volt logic High driving a 5 volt input— There is no problem when the 5 voltdevice has a TTL-level input threshold ofapproximately 1.3 volt. This is true for mostCMOS devices. The driving 3.3 volt output
The relentless pressure to achieve higherspeed, higher density, lower cost, and lowerpower consumption is driving Xilinx (andother IC manufacturers) to use ever-thinnergate oxides and smaller geometries, resultingin a requirement for lower supply voltages.
At 0.35 microns, devices cannot reliablytolerate a 5 volt supply, and require a 3.3 voltsupply instead. At 0.25 microns, the supplyvoltage must be lowered to 2.5 volts. At 0.18microns, a 1.8 volt supply will be likely. Totake advantage of the technical and economicbenefits of these smaller process geometries,you will face several challenges:
➤ Distributing multiple supply voltages on thePC board.
➤ Interfacing between CMOS devices usingdifferent supply voltages.
➤ Sequencing supply voltages.
Distributing Multiple SupplyVoltages on the PC Board
At today’s speeds, the analog characteristicsof a PC board play a strong role in determiningdigital system performance. Even modest-length(3 inch) interconnects must be treated as trans-
mission lines. Pay attentionto each signal path, includ-ing the complete currentloop from the positive sup-ply connection, through theIC and interconnects,through the ground distribu-tion, through the decouplingcapacitors, back to the posi-tive supply terminal.
Modern designs requirePC boards with at least four
layers (and usually more). At least one innerlayer must be dedicated as a ground planeand kept as undisturbed as possible. Anymajor hole in the ground plane forces theground current to take detours — increasingthe inductance and causing ground voltagespikes. In simple designs, 5 volt and 3.3 voltsupplies can share a common power plane.
Plan Now for Lower Supply Voltages
❝At 0.35 microns,
devices cannot reliably
tolerate a 5 volt supply,
and require a 3.3 volt
supply instead.❞
21
High level is close to Vcc, and thus wellabove the required Vih of 2 volts.
➤ 5 volt logic High driving 3.3 volt input— In most cases, the High 5 volt outputvoltage will force excessive current into the3.3 volt input. The pins on older Xilinx 3.3volt FPGAs, and on most other manufactur-ers’ 3.3 volt devices have a clamp diodebetween each pin and Vcc to protect thecircuit against electrostatic discharge (ESD).This diode starts conducting when the pin isdriven more than 0.7 volts positive withrespect to its Vcc. This diode presents aproblem in mixed-voltage systems, becauseit clamps whenever a 5 volt logic High isconnected to a 3.3 volt input.
Xilinx has overcome this problem byeliminating the clamp diode between the pinand Vcc in the circuit structure of the XilinxXC4000XL family. The pin can thus be drivenas high as 5.5 volts without regard to theactual supply voltage on the receiving input.Therefore, these devices are unconditionally 5volt tolerant, and you can ignore all interfaceprecautions. ExcellentESD protection (several thousand volts) isachieved by means of a patented diode-transistor structure that does not connect toVcc. Directly connecting an active High 5 voltCMOS output to an active High 3.3 volt out-put creates contention and must be avoided.
When 3.3 volt inputs are being drivenfrom a TTL-level output using an n-channelpull-up transistor — available as an option onall XC4000 and XC4000E and XC4000EXdevices — the input current is naturally lim-ited to less than a few mA, even when the5 volt supply is at 5.25 volts while the 3.3 voltsupply is at 3.0 volts; a very unlikely combi-nation. At nominal supply voltage levels, thecurrent is approximately 1 mA.
When non-5-volt-tolerant inputs are drivenfrom a CMOS-level, complementary, rail-to-rail output, you must somehow limit thecurrent. A 1 Kohm resistor limits the currentto less than 2 mA, but causes a slight speedpenalty (1 Kohm x 35 pF = 35 ns )
➤ 3.3 volt logic High driving a “CMOSthreshold” 5 volt input — This interfacesituation should be avoided. Anactive High 3.3 volt output cannotbe pulled higher, because theinternal pull-up transistor repre-sents an impedance of approxi-mately 50 ohms for any current ineither direction. A pull-up resistorto 5 volts is therefore useless. If theinternal pull-up transistor is dis-abled (open drain output) the pincan be pulled higher, until the ESDclamp becomes conductive. Thepins on the Xilinx XC4000X familcan thus be configured as opendrain, and an external resistor canpull them all the way to 5 volts (with aresulting RC speed penalty).
Sequencing Supply VoltagesAny system with more than one supply
voltage faces the possibility of these voltagesbeing applied in an undefined or uncontrolledsequence. For most ICs, this means you mustcalculate the maximum current flowing into thepins of the non-powered device. The currentvalue depends on the powered-up device’soutput structure (complementary outputs drivethe highest current) and on the voltage compli-ance (impedance) of the non-powered Vccdistribution net. If it is held rigidly to ground,the undesired current will be high. If the non-powered Vcc can easily be pulled High, thecurrent will be far less. Most inputs will tolerate50 mA for a few seconds, and 10 mA for unlim-ited time. For significantly higher currents theremight be the short-term risk of latch-up, and thelong-term risk of metal migration if the highcurrent persists for thousands of hours.
The Xilinx XC4000XL family is 5 volt tolerant,even when their Vcc is zero. Therefore, thesedevices have no problem with arbitrary powersequencing or even with “hot plug-in”. When 5volt power is applied first, there is no currentinto the Xilinx FPGAs. When 3.3 volt power isapplied first, the device outputs can be kept in a3-state condition by connecting the 5 volt Vccline as an active-Low Global 3-state input to the
❝At 0.25microns, the supply
voltage must be
lowered to 2.5 volts.
At 0.18 microns, a
1.8 volt supply will
be likely.❞
Continued on thefollowing page
22
HardWire™ conversion of FPGAs intoASICs gives system designers the power ofprogrammability, greatly accelerating thedesign phase, while adding the cost-effective-ness of a true ASIC solution, especially fordensity ranges of 25,000 gates and above.
Since 1991, Xilinx’s HardWire service hascompleted more than 700 conversions offlexible FPGA designs to low-cost ASICsready for volume production.
Here are some of the critical issues forensuring a successful FPGA conversion.
1.Use SynchronousDesign Methods
We recommend that you design your FPGAwith the production solution (ASIC) in mind.FPGAs can sometimes “hide” design flaws.These flaws can manifest themselves in theASIC version when the design speeds up. Themost common issues are with asynchronous
paths and simultaneous switching output noise.To ensure consistent timing, your design must
be synchronous. Because FPGAs are RAM-baseddevices, an ASIC conversion will remove all theprogrammable elements and replace them withmetal vias. In almost every case, the device timingspeeds up substantially. If a design is asynchro-nous, the timing relationships may not behave thesame in the ASIC as they did in the FPGA, perhapscausing race conditions.
In asynchronous FPGA designs, the smallglitches generated by unstable outputs can befiltered by the pass transistors used to control therouting of long nets. However, in the ASIC version,those pass transistors are replaced by metal vias,possibly allowing an unfiltered glitch to propagatethroughout the system.
If your design must be asynchronous, it is im-perative that you carefully plan the timing relation-ships on the device itself, and between chips at thesystem level. Building in generous timing marginscan help.
HardWire: Ensuring a Successful FPGA to
❝Here aresome of the critical
issues for ensuring
a successful
FPGA conversion.❞
3.3 volt devices, again eliminating any undesirable cur-rent.
Converting to Lower Voltage DesignsXilinx 3.3 volt FPGAs are fully compatible with their 5
volt equivalents. You can start a design using 5 volt sup-plies, later plugging in the 3.3 volt devices with no con-cern for functionality, speed, pin locations, or logic levels.
The next transition — to 2.5 volts — will arrive withina year. This change will be less of a challenge becauseXilinx will, at first, use 2.5 volts only for the internal logic,while running the I/O with 3.3 volt power. You must pro-vide the additional Vcc, but you need not be concernedabout signal level incompatibilities. However, we willincrease the number of Vcc and ground pins.
To ease these transitions, the IC industry plans toaccommodate direct interfacing between threesuccessive generations: first between 5, 3.3, and 2.5 voltdevices, and then in 1999, 3.3, 2.5, and 1.8 volt devices.
ConclusionNew improvements in IC technology enable a
wealth of new, smaller systems with higher performanceand lower power requirements. To take advantageof these improvements, designers must provide newsupply voltages — 3.3 volts now and 2.5 volts in thenear future.
In many cases, these new, lower-voltage devices willbe used side-by-side with older, 5 volt parts. Thesemixed-voltage environments could create a variety ofdesign challenges, especially when using FPGAs that arenot specifically designed to operate in mixed-voltageenvironments. The new 3.3 volt Xilinx FPGA families areimmune to all power sequencing problems and can beinterfaced directly with 5 volt devices, making them anideal solution for many mixed-voltage systems. ◆
An expanded version of this article appears in the August 18, 1997edition of Electronic Design.
Lower Supply Voltages Continued from the previous page
23
2.Thoroughly SimulateYour FPGA Design
Xilinx does not require functional or timingsimulations, prior to FPGA/ASIC conversion.However, the FPGA design destined for anASIC should be exhaustively simulated.
Unit delay simulation can be thought of as“best-case” simulation, since the logic willusually perform under the actual unit delay.This can set the “timing minimum” pole.The maximum simulation sets the “timingmaximum” pole. If there are no functionaldifferences between the maximum and mini-mum, then the design is likely to be free oftiming dependencies.
3. Plan Your RAM UsageRAM on an FPGA device is very efficient.
However, RAM on an ASIC can be inefficientif not well planned,; and large RAM blocksmay require extensive silicon area. Generally,if a design’s RAM requirements exceed 25-35%of the total CLBs used, the die size willincrease substantially, perhaps requiring triple-level metal for additional routing. One single-port RAM bit equals roughly four to six gatearray gates; one dual port RAM bit can requireseven to ten gates. If large amounts of RAMare required, it may be appropriate to leavepart off-chip, or in extreme cases, consider astandard cell implementation.
4.Pay Attention to FPGAConfiguration Modes
FPGA configuration modes are key. In theFPGA, data is stored in the PROM. The PROMis downloaded to the FPGA via one of manyconfiguration modes, allowing the system to“wake up” in an orderly manner. During con-version, the normal configuration mode is“instant on.” If the ASIC device is still depen-dent on other events prior to “waking up,”you should implement the configuration modeinto the ASIC. Otherwise, system-level timing
errors may result or ASICs might appear non-functional. Prior to ASIC conversion, the con-figuration scheme must be well documentedso that configuration logic can be included inthe ASIC version.
5. Select Your Best VendorFinally, select a vendor who can handle
the features, density, and volume productionof the resulting ASIC. Many ASIC vendorsoffer a “conversion service” that is nothingmore than netlist translation into a third-partylibrary. After the netlist translation, customersmust re-simulate and re-validate both timingand functionality.
Xilinx supports full turnkey conversion,using Xilinx-specific tools and technology.The Xilinx-converted ASIC has Xilinx-specificfeatures built into the die to eliminate themismatch between the FPGA features and theASIC implementation.
HardWire is the only FPGA conversionmethod that supports Xilinx devices withstate-of-the-art technology and guaranteessuccess. Xilinx design engineers work closelywith you to ensurethat all consider-ations have beenreviewed. TheFPGA is convertedto a Xilinx Hard-Wire device usingthe same fabricationfacilities used tomake the FPGA,with greater than90% first-attemptsuccess rates.
When consider-ing an FPGA toASIC conversionproject, it is wise toreview all the design considerations, performthe critical system level testing, and most ofall choose a vendor who can support yourspecific requirements. ◆
ASIC Conversion
❝When considering an
FPGA to ASIC conversion
project, it is wise to review all
the design considerations,
perform the critical system level
testing, and most of all choose
a vendor who can support your
specific requirements.❞
PIN
S
TY
PE
CO
DE
XC
30
20
A
XC
30
30
A
XC
30
42
A
XC
30
64
A
XC
30
90
A
XC
30
20
L
XC
30
30
L
XC
30
42
L
XC
30
64
L
XC
30
90
L
XC
31
42
L
XC
31
90
L
XC
31
20
A
XC
31
30
A
XC
31
42
A
XC
31
64
A
XC
31
90
A
XC
31
95
A
XC
40
03
E
XC
40
05
E
XC
40
06
E
XC
40
08
E
XC
40
10
E
XC
40
13
E
XC
40
20
E
XC
40
25
E
XC
40
28
EX
XC
40
36
EX
XC
40
05
XL
XC
40
10
XL
XC
40
13
XL
XC
40
20
XL
XC
40
28
XL
XC
40
36
XL
XC
40
44
XL
XC
40
52
XL
PLASTIC LCC PC44
PLASTIC QFP PQ44
PLASTIC VQFP VQ44
CERAMIC LCC WC44
PLASTIC VQFP VQ64
PLASTIC LCC PC68
CERAMIC LCC WC68
PLASTIC LCC PC84
CERAMIC LCC WC84
CERAMIC PGA PG84
PLASTIC PQFP PQ100
PLASTIC TQFP TQ100
PLASTIC VQFP VQ100
TOP BRZ. CQFP CB100
CERAMIC PGA PG120
PLASTIC PGA PP132
CERAMIC PGA PG132
PLASTIC TQFP TQ144
CERAMIC PGA PG144
HI-PERF TQFP HT144
CERAMIC PGA PG156
HI-PERF QFP HQ160
PLASTIC PQFP PQ160
TOP BRZ. CQFP CB164
PLASTIC PGA PP175
CERAMIC PGA PG175
PLASTIC TQFP TQ176
HI-PERF TQFP HT176
CERAMIC PGA PG191
TOP BRZ. CQFP CB196
PLASTIC PQFP PQ208
HI-PERF QFP HQ208
CERAMIC PGA PG223
PLASTIC BGA BG225
TOP BRZ. CQFP CB228
PLASTIC PQFP PQ240
HI-PERF QFP HQ240
PLASTIC BGA BG256
CERAMIC PGA PG299
HI-PERF. QFP HQ304
PLASTIC BGA BG352
CERAMIC PGA PG411
PLASTIC BGA BG432
CERAMIC PGA PG475
CERAMIC PGA PG559
PLASTIC BGA BG560
COMPONENT AVAILABILITY CHART
44
64
68
84
100
120
132
144
156
160
164
175
176
191
196
208
223
225
228
240
256
299
304
352
411
432
475
559
560
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◆ ◆ ◆ ◆◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆◆ ◆ ◆ ◆◆ ◆ ◆◆ ◆ ◆◆ ◆ ◆ ◆
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◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ❖
◆ ◆ ◆ ❖
◆ ◆
24❖ ❖
❖ ❖ ❖
❖ ❖
PIN
S
TY
PE
CO
DE
XC
40
62
XL
XC
40
85
XL
XC
40
05
L
XC
40
10
L
XC
40
13
L
XC
52
02
XC
52
04
XC
52
06
XC
52
10
XC
52
15
XC
62
16
XC
62
64
XC
95
36
XC
95
72
XC
95
10
8
XC
95
21
6
XC
95
28
8
AUGUST 1997
PLASTIC LCC PC44
PLASTIC QFP PQ44
PLASTIC VQFP VQ44
CERAMIC LCC WC44
PLASTIC VQFP VQ64
PLASTIC LCC PC68
CERAMIC LCC WC68
PLASTIC LCC PC84
CERAMIC LCC WC84
CERAMIC PGA PG84
PLASTIC PQFP PQ100
PLASTIC TQFP TQ100
PLASTIC VQFP VQ100
TOP BRZ. CQFP CB100
CERAMIC PGA PG120
PLASTIC PGA PP132
CERAMIC PGA PG132
PLASTIC TQFP TQ144
CERAMIC PGA PG144
HI-PERF TQFP HT144
CERAMIC PGA PG156
HI-PERF QFP HQ160
PLASTIC PQFP PQ160
TOP BRZ. CQFP CB164
PLASTIC PGA PP175
CERAMIC PGA PG175
PLASTIC TQFP TQ176
HI-PERF TQFP HT176
CERAMIC PGA PG191
TOP BRZ. CQFP CB196
PLASTIC PQFP PQ208
HI-PERF QFP HQ208
CERAMIC PGA PG223
PLASTIC BGA BG225
TOP BRZ. CQFP CB228
PLASTIC PQFP PQ240
HI-PERF QFP HQ240
PLASTIC BGA BG256
CERAMIC PGA PG299
HI-PERF. QFP HQ304
PLASTIC BGA BG352
CERAMIC PGA PG411
PLASTIC BGA BG432
CERAMIC PGA PG475
CERAMIC PGA PG559
PLASTIC BGA BG560
44
64
68
84
100
120
132
144
156
160
164
175
176
191
196
208
223
225
228
240
256
299
304
352
411
432
475
559
560
◆ ❖
◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
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◆
◆ ◆ ◆ ◆ ◆
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◆ ◆ ◆ ◆
◆ ◆ ◆
◆ ◆
◆ ◆ ◆ ◆◆
◆◆
◆ ◆ ◆
◆ = Product currentlyshipping or planned
❖ = New since last issueof XCell◆ ◆
25◆ ◆ ◆
26
XILI
NX IN
DIV
IDUA
L PR
OD
UCTS
XIL
INX
PAC
KAG
ESXILINX RELEASED SOFTWARE STATUS - AUGUST 1997
XILINX PART CURRENT VERSION BY PLATFORM LAST PREVIOUS
PRODUCT PRODUCT PRODUCT REFERENCE PC1 SN2 HP7 UPDT VERSION NOTES/KEY CATEGORY DESCRIPTION FUNCTION NUMBER 6.2 4.1.X 9.01 COMP RELEASE FEATURES
U CORE XEPLD Support Core Implementation DS-550-xxx 6.0.1 5.2.1 5.2.1 7/96 5.2/6.0 PC update by request only
U* XABEL-CPLD XC9500 Support Entry/Simulation/Core DS-571-PC1 6.1.2 11/96 6.1.1 New version w/Win 95 to 3.11, update by request
Alliance Evaluation Kit 4KE/L/EX/XL/XC9500 Eval. kit for Alliance base & wkstns DS-ALI-EVAL 1.3 1.3 1.3 na 1.2 Solaris, OS, HP-UX, HP715, Win95, NT
SILICON SUPPORT
2K 3K 4K/E 5K 7K 9K
I Cadence X X X DS-CDN-STD-xxx 5.2.1 5.2.1 7/96 5.20
I Mentor X X X DS-MN8-STD-xxx 5.2.1 5.2.1 7/96 5.20 No AP1 update
I Mentor X X X DS-MN8-ADV-xxx 7.00 7.00 na na
I Synopsys X X DS-SY-STD-xxx 5.2.1 5.2.1 7/96 5.20 Includes DS-401 v5.2
I Viewlogic X X X DS-VL-STD-xxx 6.0.1 5.2.1 5.2.1 7/96 5.26.0 DA1 platform remains at v6.0
I Viewlogic/S X X X DS-VLS-STD-PC1 6.0.1 7/96 6.0 Currently updating in-warranty cust. w/WVO
U, I 3rd Party Alliance X X X DS-3PA-BAS-xxx 6.0.1 7/96 na Customer w/v6.0 will receive v6.0.1 update
I 3rd Party Alliance X X X DS-3PA-STD-xxx 6.0.1 5.2.1 5.2.1 7/96 5.2/6.0 Includes 502/550/380
Foundation Series X X X DS-FND-BAS-PC 1.3 8/97 6.0.2 Includes support for XC4000E/X & XC9500
Foundation Series X X X DS-FND-BSV-PC 1.3 8/97 6.0.2 Includes support for XC4000E/X & XC9500
Foundation Series X X X DS-FND-STD-PC 1.3 8/97 6.0.2 Includes support for XC4000E/X & XC9500
Foundation Series X X X DS-FND-STV-PC 1.3 8/97 6.0.2 Includes support for XC4000E/X & XC9500
Foundation Series X X X DL-FND-BAS-PC 1.3 8/97 6.0.2 XC4000 not supported. Bill only additional lic.
LogiCore-PCI Slave LC-DI-PCIS-C 1.10 1.10 1.10 na na Requires signed license agreement
LogiCore-PCI Master LC-DI-PCIM-C 1.10 1.10 1.10 na na Requires signed license agreement
Evaluation X X X DS-EVAL-XXX-C 2.00 2.00 2.00 4/96 01/04 PC, Sun, HP kits with v5.2.1 and v6.0.1
KEY: N=New Product U= Update by request only I=Libraries, interfaces and XBLOX are included with versions 1.2 & 1.3 * = Check FTP site for most current revision of EZTAG programming software..
BYTEK 135H-FT/U 8E 8E 8E 8EMTK-1000 8E 8E 8E 8EMTK-2000 8E 8E 8E 8EMTK-4000 8E 8E 8E 8EFIREMAN-8M 8E 8E 8E 8EFIREMAN-8X 8E 8E 8E 8ECHIPBURNER-40 1.0a 1.0a 1.0a 1.0a
COMPANY NAME CONTACT NAME PHONE NUMBER E-MAIL ADDRESS COMPANY NAME CONTACT NAME PHONE NUMBER E-MAIL ADDRESS
PARTNER NAME PHONE EMAIL/WEB URL EXPERTISE
ARM Semiconductor (USA), Inc. Tel: 408-733-3344 [email protected] Microprocessors, microcontrollers,1095 E. Duane Ave., Suite 211 Sunnyvale, CA 94086 (USA) Fax: 408-733-9922 www.armsemi.com peripherals, communications
CAST, Inc. Tel: 914-354-4945 [email protected] AM29xx peripherals, DSP24 White Birch Drive, Pomona, NY 10970 (USA) Fax: 914-354-0325 www.cast-inc.com
Comit Systems Tel: 408-988-2988 [email protected] Base functions, communications1250 Oakmead Pkwy, Suite 210 Sunnyvale, CA 94088 (USA) Fax: 408-988-2133 www.comit.com
Inventra/Mentor Tel: 503-685-8000 USB, PCI, DSP, telecom,1001 Ridder Park Drive, San Jose, CA 95131-2314 (USA) Fax: 408-451-5690 www.mentorg.com/inventra microprocessor peripherals
Logic Innovations Tel: 619-455-7200 [email protected] PCI, MPEG-2, ATM,6205 Lusk Boulevard San Diego, CA 92121 (USA) Fax: 619-455-7273 www.logici.com communications
Memec Design Services Tel: 602-491-4311 [email protected] Microprocessor peripherals, base1819 S. Dobson Rd., Suite 203, Mesa, AZ 85202 (USA) Fax: 602-491-4907 www.memecdesign.com functions, Xilinx design services
Mobile Media Research, Inc. Tel: 510-657-4891 [email protected] PCMCIA, CardBus39675 Cedar Blvd., Suite 295A, Newark, CA 94560 (USA) Fax: 510-657-4892 www.mobmedres.com
NMI Electronics, Ltd., Fountain House, Great Cornbow, Tel: +44 121 585 5979 [email protected] Design services and base-levelHalesowen, West Midlands, B63 3BL (UK) Fax: +44 121 585 5764 www.nmi.co.uk functions for the XC9500
Phoenix Technologies/Virtual Chips Tel: 408-570-1000 [email protected] PCI, USB, CardBus, ATM2107 N. First Street, Suite 100, San Jose, CA 95113 (USA) Fax: 408-452-0952 www.phoenix.com
SAND Microelectronics Tel: 408-235-8600 [email protected] PCI, USB3350 Scott Blvd., #24, Santa Clara, CA 95131 (USA) Fax: 408-235-8601 www.sandmicro.com
SICAN Microeletronics Corp. Tel: 650-871-1494 [email protected] CAN bus, DSP, communications400 Oyster Point Blvd., #512, So. San Francisco, CA 94080 (USA) Fax: 650-871-1504 www.sican-micro.com
Technology Rendezvous, Inc. Tel: 408-556-0280 [email protected] FireWire3160 De La Cruz Blvd., Suite 101, Santa Clara, CA 95054 (USA) Fax: 408-556-0284 www.trinic.com
Additional information is available on WebLINX, starting at: http://www.xilinx.com/products/logicore/alliance/tblpart.htm
Changes since last issue normally printed in color. There have been no changes since XCell 25.Inquiries about the Xilinx Alliance Program can be e-mailed to [email protected]
