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Is Now Part of
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June 2014
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 1 www.fairchildsemi.comFDMC8200 Rev.A2
FDMC8200 Dual N-Channel PowerTrench® MOSFET 30 V, 9.5 mΩ and 20 mΩ
FeaturesQ1: N-Channel
Max rDS(on) = 20 mΩ at VGS = 10 V, ID = 6 A
Max rDS(on) = 32 mΩ at VGS = 4.5 V, ID = 5 A
Q2: N-ChannelMax rDS(on) = 9.5 mΩ at VGS = 10 V, ID = 9 A
Max rDS(on) = 13.5 mΩ at VGS = 4.5 V, ID = 7 A
RoHS Compliant
General DescriptionThis device includes two specialized N-Channel MOSFETs in a dual Power33 (3mm x 3mm MLP) package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous MOSFET (Q2) have been designed to provide optimal power efficiency.
ApplicationsMobile Computing
Mobile Internet Devices
General Purpose Point of Load
MOSFET Maximum Ratings TC = 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Q1 Q2 UnitsVDS Drain to Source Voltage 30 30 VVGS Gate to Source Voltage (Note 3) ±20 ±20 V
ID
Drain Current - Continuous (Package limited) TC = 25 °C 18 18
A - Continuous (Silicon limited) TC = 25 °C 23 45 - Continuous TA = 25 °C 8 1a 12 1b
- Pulsed 40 40
PDPower Dissipation TA = 25 °C 1.9 1a 2.2 1b
WPower Dissipation TA = 25 °C 0.7 1c 0.9 1d
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJA Thermal Resistance, Junction to Ambient 65 1a 55 1b
°C/WRθJA Thermal Resistance, Junction to Ambient 180 1c 145 1d
RθJC Thermal Resistance, Junction to Case 7.5 4
Device Marking Device Package Reel Size Tape Width QuantityFDMC8200 FDMC8200 Power 33 13 ” 12 mm 3000 units
G2 G1
BOTTOM
G2
D1
S2S2
S2
D1
G1D1
D1
D2/S1
S2
S2
S2 D1
D1
D1Pin 1VIN
SWITCH NODE
GLS
VIN
GND GND GND
GHSVIN
VIN
VIN
SWITCH NODE
GLS
VIN
GND GND GND
GHSVIN
VIN
4
3
2
1
5
6
7
8 Q1
Q2 4
3
2
1
5
6
7
8 Q1
Q2
Power 33
BOTTOM
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 2 www.fairchildsemi.comFDMC8200 Rev.A2
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Symbol Parameter Test Conditions Type Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 VID = 250 μA, VGS = 0 V
Q1Q2
3030 V
ΔBVDSS ΔTJ
Breakdown Voltage TemperatureCoefficient
ID = 250 μA, referenced to 25 °CID = 250 μA, referenced to 25 °C
Q1Q2 14
14 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 VVDS = 24 V, VGS = 0 V
Q1Q2
11 μA
IGSS Gate to Source Leakage Current VDS = 20 V, VGS = 0 V Q1Q2 100
100nAnA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μAVGS = VDS, ID = 250 μA
Q1Q2
1.01.0
2.32.3
3.03.0 V
ΔVGS(th) ΔTJ
Gate to Source Threshold VoltageTemperature Coefficient
ID = 250 μA, referenced to 25 °CID = 250 μA, referenced to 25 °C
Q1Q2
-5-6 mV/°C
rDS(on) Static Drain to Source On Resistance
VGS = 10 V, ID = 6 A VGS = 4.5 V, ID = 5 A VGS = 10 V, ID = 6 A, TJ = 125 °C
Q1162422
203228
mΩVGS = 10 V, ID = 9 A VGS = 4.5 V, ID = 7 A VGS = 10 V, ID = 9 A, TJ = 125 °C
Q27.39.510
9.513.513
gFS Forward Transconductance VDD = 5 V, ID = 6 AVDD = 5 V, ID = 9 A
Q1Q2
2956 S
Ciss Input Capacitance
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1Q2 495
1180660
1570 pF
Coss Output Capacitance Q1Q2
145330
195440 pF
Crss Reverse Transfer Capacitance Q1Q2
2030
3045 pF
Rg Gate Resistance Q1Q2
1.41.4 Ω
td(on) Turn-On Delay Time Q1VDD = 15 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω
Q2VDD = 15 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω
Q1Q2 11
132023 ns
tr Rise Time Q1Q2 3.1
41010 ns
td(off) Turn-Off Delay Time Q1Q2 35
385660 ns
tf Fall Time Q1Q2 1.3
61012 ns
Qg(TOT) Total Gate Charge VGS = 0 V to 10 V Q1:VDD = 15 V, ID = 6 A,
Q2:VDD = 15 V, ID = 9 A,
Q1Q2
7.316
1022 nC
Qg(TOT) Total Gate Charge VGS = 0 V to 4.5 V Q1Q2
3.17
4.310 nC
Qgs Gate to Source Charge Q1Q2 1.8
4.1 nC
Qgd Gate to Drain “Miller” Charge Q1Q2 1
1.5 nC
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 3 www.fairchildsemi.comFDMC8200 Rev.A2
Electrical Characteristics TJ = 25 °C unless otherwise noted
Drain-Source Diode Characteristics
Notes:
1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
Symbol Parameter Test Conditions Type Min Typ Max Units
VSDSource to Drain Diode Forward Volt-age
VGS = 0 V, IS = 6 A (Note 2)VGS = 0 V, IS = 9 A (Note 2)
Q1Q2 0.8
0.8 1.21.2 V
trr Reverse Recovery Time Q1IF = 6 A, di/dt = 100 A/sQ2IF = 9 A, di/dt = 100 A/s
Q1Q2
1321
2434 ns
Qrr Reverse Recovery Charge Q1Q2 2.3
5.61012 nC
a.65 °C/W when mounted on a 1 in2 pad of 2 oz copper
c. 180 °C/W when mounted on a minimum pad of 2 oz copper
b.55 °C/W when mounted on a 1 in2 pad of 2 oz copper
d. 145 °C/W when mounted on a minimum pad of 2 oz copper
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 4 www.fairchildsemi.comFDMC8200 Rev.A2
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
Figure 1.
0.0 0.5 1.0 1.5 2.0 2.5 3.00
10
20
30
40VGS = 10 V
VGS = 4 V
PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX
VGS = 3.5 V
VGS = 4.5 V
VGS = 6 V
I D, D
RA
IN C
UR
REN
T (A
)
VDS, DRAIN TO SOURCE VOLTAGE (V)
On Region Characteristics Figure 2.
0 10 20 30 400
1
2
3
4
VGS = 3.5 V
PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX
NO
RM
ALI
ZED
DR
AIN
TO
SO
UR
CE
ON
-RES
ISTA
NC
E
ID, DRAIN CURRENT (A)
VGS = 4 V
VGS = 4.5 V
VGS = 6 V VGS = 10 V
Normalized On-Resistance vs Drain Current and Gate Voltage
Figure 3. Normalized On Resistance
-75 -50 -25 0 25 50 75 100 125 1500.8
1.0
1.2
1.4
1.6
ID = 6 AVGS = 10 V
NO
RM
ALI
ZED
DR
AIN
TO
SO
UR
CE
ON
-RES
ISTA
NC
E
TJ, JUNCTION TEMPERATURE (oC)
vs Junction TemperatureFigure 4.
2 4 6 8 100
20
40
60
80
100
TJ = 125 oC
ID = 6 A
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
r DS(
on),
DR
AIN
TO
SO
UR
CE
ON
-RES
ISTA
NC
E (m
Ω) PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
On-Resistance vs Gate to Source Voltage
Figure 5. Transfer Characteristics
2.0 2.5 3.0 3.5 4.0 4.50
10
20
30
40
TJ = 150 oC
VDS = 5 V
PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
I D, D
RA
IN C
UR
REN
T (A
)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.2 0.4 0.6 0.8 1.0 1.20.001
0.01
0.1
1
10
40
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
I S, R
EVER
SE D
RA
IN C
UR
REN
T (A
)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode Forward Voltage vs Source Current
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 5 www.fairchildsemi.comFDMC8200 Rev.A2
Figure 7.
0 2 4 6 80
2
4
6
8
10ID = 6 A
VDD = 10 V
VDD = 15 V
V GS,
GA
TE T
O S
OU
RC
E VO
LTA
GE
(V)
Qg, GATE CHARGE (nC)
VDD = 20 V
Gate Charge Characteristics Figure 8.
0.1 1 10 3010
100
1000
f = 1 MHzVGS = 0 V
CA
PAC
ITA
NC
E (p
F)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Capacitance vs Drain to Source Voltage
Figure 9.
0.01 0.1 1 10 1002000.001
0.01
0.1
1
10
100
10 s1 s
DC
100 ms10 ms1 ms
100 us
I D, D
RAI
N CU
RRE
NT (A
)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS LIMITED BY rDS(on)
SINGLE PULSETJ = MAX RATEDRθJA = 180 oC/WTA = 25 oC
Forward Bias Safe Operating Area
Figure 10.
25 50 75 100 125 1500
5
10
15
20
25
Limited by Package
RθJC = 7.5 oC/W
VGS = 4.5 V
VGS = 10 V
I D, D
RA
IN C
UR
REN
T (A
)
Tc, CASE TEMPERATURE (oC)
Maximum Continuous Drain Current vs Case Temperature
10-4 10-3 10-2 10-1 1 10 100 1000
1
10
100
P (PK
), PEA
K T
RA
NSI
ENT
POW
ER (W
) VGS = 10 V
SINGLE PULSERθJA = 180 oC/W
TA = 25 oC
t, PULSE WIDTH (s)
300
0.5
Figure 11. Single Pulse Maximum Power Dissipation
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 6 www.fairchildsemi.comFDMC8200 Rev.A2
Figure 12.
10-4 10-3 10-2 10-1 1 10 100 10000.003
0.01
0.1
1
SINGLE PULSERθJA = 180 oC/W
DUTY CYCLE-DESCENDING ORDER
NO
RM
ALI
ZED
TH
ERM
AL
IMPE
DA
NC
E, Z
θJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5 0.2 0.1 0.05 0.02 0.01
2
PDM
t1t2
NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x ZθJA x RθJA + TA
Junction-to-Ambient Transient Thermal Response Curve
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 7 www.fairchildsemi.comFDMC8200 Rev.A2
Typical Characteristics (Q2 N-Channel)
Figure 13. On-Region Characteristics
0.0 0.5 1.0 1.5 2.0 2.5 3.00
10
20
30
40
VGS = 3 V
VGS = 4 V
PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX
VGS = 3.5 V
VGS = 4.5 V
VGS = 10 V
I D, D
RA
IN C
UR
REN
T (A
)
VDS, DRAIN TO SOURCE VOLTAGE (V)0 10 20 30 40
0
1
2
3
4
5
6
VGS = 3 V
PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX
NO
RM
ALI
ZED
DR
AIN
TO
SO
UR
CE
ON
-RES
ISTA
NC
E
ID, DRAIN CURRENT (A)
VGS = 3.5 V
VGS = 4 V VGS = 4.5 V
VGS = 10 V
Figure 14. Normalized on-Resistance vs Drain Current and Gate Voltage
Figure 15. Normalized On-Resistance vs Junction Temperature
-75 -50 -25 0 25 50 75 100 125 1500.6
0.8
1.0
1.2
1.4
1.6
ID = 9 AVGS = 10 V
NO
RM
ALI
ZED
DR
AIN
TO
SO
UR
CE
ON
-RES
ISTA
NC
E
TJ, JUNCTION TEMPERATURE (oC)2 4 6 8 10
0
10
20
30
40
50
60
TJ = 125 oC
ID = 9 A
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
r DS(
on),
DR
AIN
TO
SO
UR
CE
ON
-RES
ISTA
NC
E (m
Ω) PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
Figure 16. On-Resistance vs Gate to Source Voltage
Figure 17. Transfer Characteristics
1.5 2.0 2.5 3.0 3.5 4.00
10
20
30
40
TJ = 150 oC
VDS = 5 V
PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
I D, D
RA
IN C
UR
REN
T (A
)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 18. Source to Drain Diode Forward Voltage vs Source Current
0.0 0.2 0.4 0.6 0.8 1.0 1.20.001
0.01
0.1
1
10
40
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
I S, R
EVER
SE D
RA
IN C
UR
REN
T (A
)
VSD, BODY DIODE FORWARD VOLTAGE (V)
TJ = 25 °C unless otherwise noted
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 8 www.fairchildsemi.comFDMC8200 Rev.A2
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted
Figure 19. Gate Charge Characteristics Figure 20. Capacitance vs Drain to Source Voltage
Figure 21. Forward Bias Safe Operating Area
Figure 22. Maximum Continuous Drain Current vs Case Temperature
Figure 22. Single Pulse Maximum Power Dissipation
0 3 6 9 12 15 180
2
4
6
8
10ID = 9 A
VDD = 10 V
VDD = 15 V
V GS,
GA
TE T
O S
OU
RC
E VO
LTA
GE
(V)
Qg, GATE CHARGE (nC)
VDD = 20 V
0.1 1 10 3010
100
1000
2000
f = 1 MHzVGS = 0 V
CA
PAC
ITA
NC
E (p
F)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
0.01 0.1 1 10 1002000.01
0.1
1
10
100
10 s1 s
DC
10 ms
1 ms
100 us
100 ms
I D, D
RAI
N CU
RRE
NT (A
)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS LIMITED BY rDS(on)
SINGLE PULSETJ = MAX RATEDRθJA = 145 oC/WTA = 25 oC
25 50 75 100 125 1500
10
20
30
40
50
Limited by Package
RθJC = 4 oC/W
VGS = 4.5 V
VGS = 10 VI D
, DR
AIN
CU
RR
ENT
(A)
Tc, CASE TEMPERATURE (oC)
10-4 10-3 10-2 10-1 1 10 100 1000
1
10
100
1000
P (PK
), PEA
K T
RA
NSI
ENT
POW
ER (W
) VGS = 10 V
SINGLE PULSERθJA = 145 oC/W
TA = 25 oC
t, PULSE WIDTH (s)
0.5
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 9 www.fairchildsemi.comFDMC8200 Rev.A2
Figure 23. Junction-to-Ambient Transient Thermal Response Curve
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted
10-4 10-3 10-2 10-1 1 10 100 10000.001
0.01
0.1
1
SINGLE PULSERθJA = 145 oC/W
DUTY CYCLE-DESCENDING ORDER
NO
RM
ALI
ZED
TH
ERM
AL
IMPE
DA
NC
E, Z
θJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5 0.2 0.1 0.05 0.02 0.01
2
PDM
t1t2
NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x ZθJA x RθJA + TA
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 10 www.fairchildsemi.comFDMC8200 Rev.A2
Dimensional Outline and Pad Layout
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, spe-cifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_MLDED-CX8
FDM
C8200 D
ual N-C
hannel PowerTrench
® MO
SFET
©2009 Fairchild Semiconductor Corporation 11 www.fairchildsemi.comFDMC8200 Rev.A2
TRADEMARKSThe following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used here in:1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONSDefinition of Terms
AccuPower™AX-CAP®*BitSiC™Build it Now™CorePLUS™CorePOWER™CROSSVOLT™CTL™Current Transfer Logic™DEUXPEED®
Dual Cool™EcoSPARK®
EfficentMax™ESBC™
Fairchild®
Fairchild Semiconductor®FACT Quiet Series™FACT®
FAST®
FastvCore™FETBench™FPS™
F-PFS™FRFET®
Global Power ResourceSM
GreenBridge™Green FPS™Green FPS™ e-Series™Gmax™GTO™IntelliMAX™ISOPLANAR™Marking Small Speakers Sound Louder and Better™MegaBuck™MICROCOUPLER™MicroFET™MicroPak™MicroPak2™MillerDrive™MotionMax™mWSaver®OptoHiT™OPTOLOGIC®
OPTOPLANAR®
PowerTrench®
PowerXS™Programmable Active Droop™QFET®
QS™Quiet Series™RapidConfigure™
Saving our world, 1mW/W/kW at a time™SignalWise™SmartMax™SMART START™Solutions for Your Success™SPM®
STEALTH™SuperFET®
SuperSOT™-3SuperSOT™-6SuperSOT™-8SupreMOS®
SyncFET™Sync-Lock™
®*
TinyBoost®TinyBuck®
TinyCalc™TinyLogic®
TINYOPTO™TinyPower™TinyPWM™TinyWire™TranSiC™TriFault Detect™TRUECURRENT®*μSerDes™
UHC®
Ultra FRFET™UniFET™VCX™VisualMax™VoltagePlus™XS™仙童 ™
®
™
Datasheet Identification Product Status Definition
Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Preliminary First ProductionDatasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.
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