ZCU102 Root Complex Design in Vivado - Xilinx...the “.hdf” file is inside the “hdf_zcu102rc”...

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Xilinx Answer 71493 1

Xilinx Answer 71493

PetaLinux Image Generation and System Example Design with ZCU102 PS-PCIe as Root Complex and ZC706 as Endpoint

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ZCU102 Root Complex Design in Vivado

Overview This document describes an example design consisting of Zynq UltraScale+ MPSoC ZCU102 and Zynq-7000 SoC ZC706. The ZCU102 is configured as root complex while the ZC706 is configured as an endpoint. The document goes through the detailed steps for design creation for ZCU102 and ZC706 in Vivado and PetaLinux Image generation for ZCU102 required to boot Linux on the Zynq ZCU102 device. There are 5 chronological steps required to generate the PetaLinux image file. These include configuring subsystems from the hardware description file for boot up, configuring the root filesystem component to enable the “lspci” command of PCIe, generating the default Linux kernel component, building the project from the configured components, and packaging the project together with the bitstream. If successful, an image.ub file and a BOOT.BIN file, which are needed to boot Linux, will be generated for hardware testing.

IP Integrator Design Creation The design method for ZCU102 root complex will utilize the “Create Block Design” tool under IP INTEGRATOR in the Flow Navigator window. This block design window allows the user to create a design using various IP blocks, depending on the selected parts or boards.

Design Overview

Figure 1 shows the Zynq processor block design of a ZCU102 evaluation board with PCI Express set up as root complex.

Figure 1 - Zynq-7000 Processor IP Block

http://www.xilinx.com/support/answers/71493.html



Create a new Vivado project

Launch Vivado 2018.2 and click on “Create Project” under “Quick Start”. Click “Next”.

Figure 2 - Create a new Vivado project

Enter a desired name for the Project and note the project location for future reference. Tick the “Create

a project subdirectory” checkbox as shown below. Click “Next”.

Figure 3 - Choose a project name

For the Project Type window, choose “RTL (Register Transfer Level) Project” and tick the checkbox

“Do not specify sources at this time”. Addition of sources can be done at a later stage of the design

process. Click “Next”.

https://www.xilinx.com/support/download.html



Figure 4 - Select project type

In the “Default Part” window, click on Boards and type the board name, ZCU102, into the Search field. Select the board and click “Next”.

Figure 5 - Choose a board for the project

A message dialog box will show the Project Summary which contains the project name and the board information as shown in Figure 6. Click “Finish” to continue with the design.



Figure 6 - Project summary

Create the block design

The following steps will show how to create the block design.

From the Vivado Flow Navigator, click on “Create Block Design”. The Vivado Flow Navigator is located

at the left part of the Vivado Project page.

Figure 7 - Flow navigator

In the “Design name” field, specify a name for the block design, for example ZCU102RC. Leave the

default selections for the other fields as shown below. Click “OK”.

Figure 8 - Choose block design name



Click on the “+” sign or “Add IP” icon. This will open the IP (Intellectual Property) catalog. Alternatively,

use “CTRL+ I” to open the “Add IP” catalog.

Figure 9 - Adding IP

Search for “Zynq UltraScale+ MPSoC” by typing it into the search field. Double click on “Zynq

UltraScale+ MPSoC” to add the block.

Figure 10 - Searching for the Zynq processor

The Zynq UltraScale+ MPSoC block will be added to the block design as shown below. Click Run Block

Automation to configure the Zynq for the target hardware.



Figure 11 - Run block automation

On the left part of the resulting dialog box, ensure that the checkbox for the “zynq_ultra_ps_e_0” block is selected. Click OK to use the default block automation settings.

Figure 12 - Confirmation for the block automation

Re-customize the block

Double-click on the Zynq block (middle part) to configure it.



Figure 13 - Customizing Zynq IP

Under Page Navigator, select the “Switch to Advance” checkbox and then click on the I/O Configuration tab.

Figure 14 - Customizing Zynq IP (I/O Configuration)

Expand “High Speed” and uncheck the SATA checkbox. Similarly, expand “USB” and uncheck USB 0. Lastly, expand “PCIe” and set Lane Selection to x4.



Figure 15 - Customizing Zynq IP (High Speed Peripheral)

Under Page Navigator click on the PCIe Configuration tab and check that the parameters are the same as shown in Figure 16.



Figure 16 - Customizing Zynq IP (PCIe Configuration)

Click on the PS-PL Configuration tab.



Figure 17 - Customizing Zynq IP (PS-PL Configuration)

Expand “PS-PL interfaces”, and disable/uncheck the AXI HPM0 FPD, AXI HPM1 FPD and AXI HPM0

LPD interfaces. These interfaces are not needed, and so can be disabled.

Figure 18 - Customizing Zynq IP (PS-PL Interfaces)

Expand “General” and untick the “Fabric Reset Enable” checkbox. Click OK.



Figure 19 - Customizing Zynq IP (untick "Fabric Reset Enable")

Below is the re-customized block. Press Ctrl + S to save and then check that validation is successful

by clicking the validation icon.

Figure 20 - Validating the customized Zynq IP

After validating the design, save it again.



Figure 21 - Saving the block design

Create the HDL wrapper

Now that the block diagram is complete the user can go ahead and create the HDL wrapper. Click on the “Sources” tab from the Block Design window. Right-click on “ZCU102RC.bd” and select “Create HDL wrapper” from the drop-down menu.

Figure 22 - Create HDL wrapper

In the resulting dialog box, select the option "Let Vivado manage wrapper and auto-update" and click

OK.



Figure 23 - Confirmation for creating HDL wrapper

Export the design

Go to File > Export > Export Hardware…

Figure 24 - Export hardware

The user can specify the location of the file to be exported. This file is needed for PetaLinux image

generation. Click OK to export hardware.

Figure 25 - Export hardware

Go to File > Export > Export Bitstream File.



Figure 26 - Export bitstream

The user can enter a desired file name and specify the location of the file to be exported. This file is

needed for PetaLinux image generation. Click OK to export bitstream.

Figure 27 - Export bitstream

PetaLinux Image Generation for ZCU102

The primary file needed for image creation is the hardware description file (.hdf) that was exported from the Vivado design. This file will be used to configure the subsystem of the board. After it is completely configured, the root filesystem (rootfs) and kernel will be available for configuration. If these configurations are successfully done, the project should be ready for building and packaging to create an image file. The following steps describes the PetaLinux image creation.



Setting up the PetaLinux environment Note: Create a directory in the Linux OS for the Hardware Description File (hdf) and the Bitstream (bit) files of the ZCU102 root complex design. For this project, the directory name is hdf_zcu102rc (yours could be different). Copy and paste the “.hdf” and “.bit” files to this directory. Open the file directory of PetaLinux if the location is known, otherwise use the Terminal and echo the tool as described in figure 2.1. Open the Terminal and run the command “echo $PETALINUX”. Change directory using the syntax “cd <PETALINUX-DIRECTORY>” to the PetaLinux absolute path.

Figure 28 - Changing directory to PetaLinux

Creating a project Create a project directory for the ZCU102 root complex design using the syntax shown below. The “-t” command is short for the type. The “-n” command is for the name of the directory. For this project, the “--template” that will be used is “zynqMP”.

Figure 29 - Creating project

A message in the Terminal will confirm that the ZCU102 project directory is created.

Figure 30 - Confirmation message regarding project that was created

Verify it in the file directory.



Figure 31 - Check for the project directory

Change directory to ZCU102RC or any project name directory that was created.

Figure 32 - Syntax for changing directory

Configuring the project Target the “.hdf” (Hardware Definition File) that was created from the Vivado project. For this project, the “.hdf” file is inside the “hdf_zcu102rc” directory. The command for getting the hardware definition file is:

Figure 33 - Importing hardware description file

A message will appear in Terminal which indicates that the “.hdf” file is being fetched as shown in Figure 34 after which the system configuration window will appear as shown in Figure 35.

Figure 34 - Information for the .hdf file

In the “misc/config System Configuration” window, select “Subsystem AUTO Hardware Settings”.



Figure 35 - System configuration

Select “Exit”.

Figure 36 - Exiting system configuration

Exit again and save the “misc/config System Configuration”.



Figure 37 - Saving system configuration

The Terminal will show a message “*** End of the configuration” and it will initialize the settings. This will take time depending on the system’s performance.

Figure 38 - Confirmation message for system configuration

After initializing the system configuration, it will display information regarding the generation of u-boot, kernel, kconfig, and petalinux-user-image.bb.

Figure 39 - Confirmation message for u-boot, kernel and image.bb



Configure the component root filesystem using the syntax below.

Figure 40 - Syntax for configuring root filesystem

The configuration window will appear. Select “Filesystem Packages”.

Figure 41 - Root filesystem configuration

Select “console” under “Filesystem Packages”.

Figure 42 - Filesystem packages



Select “utils” under “console”.

Figure 43 - Console package

Select “pciutils” under “utils”.

Figure 44 - Utils package

Press <Y> to include “pciutils”.



Figure 45 - Include pciutils package

Select “base” under “Filesystem Packages”.

Figure 46 - Filesystem packages

Select “util-linux” under “base”.



Figure 47 - Util-linux base

Press <Y> to include “util-linux”.

Figure 48 - Include util-linux

Press <Y> to include “util-linux-mkfs” and “util-linux-fdsik”.



Figure 49 - Include util-linux-mkfs and util-linux-fdsik

Press <Y> to include “util-linux-mount” and “util-linux-blkid”

Figure 50 - Include util-linux-mount and util-linux-blkid

Press <Y> to include “util-linux-uuid”



Figure 51 - Include util-linux-uuid

Press <Y> to include “util-linux-cfdisk” and “util-linux-sfdisk”.

Figure 52 - Include util-linux-cfdisk and util-linux-sfdisk

Press <Y> to include “util-linux-mountpoint” then exit once.



Figure 53 - Include util-linux-mountpoint

Go back to “base” configuration and select “e2fsprogs”.

Figure 54 - Select e2fsprogs under base

Press <Y> to include “e2fsprogs” and “e2fsprogs-mke2fs” under “e2fsprogs”.



Figure 55 - Include e2fsprogs and e2fsprogs-mke2fs

Exit and save configuration for the root file system component.

Figure 56 - Save root filesystem configuration

A message will be displayed in the Terminal indicating a successful configuration of the root filesystem.

Figure 57 - Confirmation message for configured root filesystem

Configure the kernel component using the syntax below:



Figure 58 - Syntax for kernel configuration

It will take time to open the window for the kernel configuration. This will depend on the system’s performance.

Figure 59 - Loading up the kernel configuration window

A new window that contains the kernel configuration will appear.

Figure 60 - Loaded kernel window

Exit and save the kernel configuration.

Figure 61 - Save the kernel configuration

A message will appear indicating that the kernel configuration was successful as shown in Figure 62.

Figure 62 - Confirmation message for the configured kernel

Building and packaging the project Build the project using the “petalinux-build” command.



Figure 63 - Building the project

It will again take time to build the project. If successful, then an information stating that the project was successfully built will appear in the Terminal. According to (Xilinx Answer 71110) 2018.x Zynq UltraScale+ MPSoC: Yocto or PetaLinux that throws warnings when the build do_rootfs tasks completes, this warning can be ignored.

Figure 64 - Confirmation message for successful built project

Locate the file “bl31.elf” for packaging and generating image, which is usually located in the file directory <project-root>/images/linux.

Figure 65 - Locating CPU codes .elf file

Locate the file “zynqmp_fsbl.elf” for packaging and generating the image. It is usually located in the file directory <project-root>/images/linux.

https://www.xilinx.com/support/answers/71110.html



Figure 66 - Locating the other. elf CPU code

Locate the file “ZCU102RC_wrapper.bit” that was copied earlier to be included in the petalinux-package file.

Figure 67 - Bitstream file for packaging

Package these files: “ZCU102RC_wrapper.bit”, “zynqmp_fsbl.elf” and “bl31.elf” by using the syntax:

petalinux-package --boot --fsbl ./images/linux/zynqmp_fsbl.elf --atf ./images/linux/bl31.elf --u-boot ./images/linux/u-boot.elf --fpga ./ZCU102_wrapper.bit

Figure 68 - Packaging both CPU codes to generate boot and image files

A “Binary is ready” message will be shown. Ignore the TFTPBOOT warning.



Figure 69 - Confirmation message for packaged binary file

Locate the file location of “BOOT.BIN” and “image.ub”.

Figure 70 - Searching for both image file and boot file

Copy these files and save them in an SD Card for booting up Linux.

Figure 71 - Copy of image file and boot file for SD Card boot up



Example Design testing with ZCU102 as the Root Complex and ZC706 as an Endpoint

Hardware configuration Connect the ZCU102 board and ZC706 board via PCIe connection. Refer to Figure 72 for ZCU102 PCIe slot and Figure 73 for ZC706 PCIe connector.

Figure 72 - ZCU102 board



Figure 73 - PCIe connection of ZCU102 and ZC706

1. ZCU102 PCIe Slot 2. SD Card slot for the ZCU102 3. ZCU102 evaluation board designed as root complex 4. ZCU102 power switch 5. ZCU102 board power supply connector 6. UART or USB port for serial monitor of ZCU102 root complex 7. ZC706 PCIe connector 8. ZC706 board as an endpoint 9. ZC706 power switch 10. JTAG or USB port for programming the ZC706 11. ZC706 board power supply connector



Programming ZC706 using Vivado Open the ZC706 design in Xilinx Example . In the Flow Navigator window, expand “Open Hardware Manager” then click on “Open Target” as shown in Figure 74 and then select “Auto Connect” from the drop-down menu as shown in Figure 75.

Figure 74 - Program and debug

Figure 75 - Targeting the board

Click on "Program device" as shown in the Figure 76 - Programming the device.



Figure 76 - Programming the device

Click “Program” to program the targeted device as shown in Figure 77.

Figure 77 - Program device

Figure 78 below shows the device status as programmed.

Figure 78 - Device status

Booting up Linux Open the Tera Term application for serial monitor to display Linux booting in the root complex device. Refer to Appendix A: Setting up “Tera Term” for Serial Out. Select “Serial” connection then click “OK”.

Figure 79 - Tera Term start-up window



Click on Setup then Serial port...

Figure 80 - Serial port configuration

A dialog box will appear. Notice the “Speed” is set to 9600. This is the baud rate communication from the board to the serial monitor.

Figure 81 - Default speed

Change the speed to 115200 then click “OK”.

Figure 82 - Change speed to 1152

When the ZCU102 board is turned on enter “root” when prompted for the login and password during the boot up process. Refer to Appendix C: Linux Boot Log for the complete Linux boot log file. Check if the devices are registered by running the “lspci” command. The details of the board device configuration will depend on the number of “v”s to verbose the information as shown in figures 83, 84 and 85.



Figure 83 - lspci

Figure 84 - lspci -vvv for ZCU102 root complex



Figure 85 - lspci -vvv for ZC706 endpoint



Appendix A: Setting up “Tera Term” for Serial Out

Go to this website: https://ttssh2.osdn.jp/index.html.en and then browse under “Download”, and click download page.

Figure 86 - Web page for Tera Term application

A new page or tab will open. Download the latest “teraterm-4.99” executable file.

Figure 87 - Tera Term download link

https://ttssh2.osdn.jp/index.html.en



Install the Tera Term application.

Figure 88 - Tera Term installation

Select “Standard Installation” then click “Next”.

Figure 89 - Tera Term standard installation

Open the Tera Term application. Select “Serial” connection then click “OK”.

Figure 90 - Tera Term start-up window



Under the “Setup” tab, select “Serial port…”.

Figure 91 - Serial port configuration

A dialog box will appear. Notice the “Speed” is set to 9600. This is the baud rate communication from the board to the serial monitor.

Figure 92 - Default baud rate

Change the speed to 115200 then click “OK”.

Figure 93 - Change speed to 1152



Appendix B: ZC706 as an Endpoint Design in Vivado

Create a new Vivado project Open Vivado 2018.2 and click “Create Project” under “Quick Start”.

Figure 94 - Create project

A message dialog box will appear. Click “Next” to proceed.

Figure 95 - Confirmation in creating a project

Enter a desired name for the Project and note the project location for future reference. Tick the “Create a project subdirectory” checkbox as shown below. Click “Next”.

https://www.xilinx.com/support/download.html



Figure 96 - Choose project name

Select the “RTL (Register Transfer Level) Project” option and tick the checkbox “Do not specify sources at this time” then click “Next”.

Figure 97 - Choose a project type

Select the “Default Part” by clicking “Boards”. The board name is ZC706 and it can be searched for by typing into the search field. Click “Next” after the board is selected.



Figure 98 - Select board for the project

A message dialog box will display the Project Summary that contains the project name and the board

information. Click “Finish” to continue with the design.

Figure 99 - Project summary

IP Catalog editor In the Vivado interface, there is a Flow Navigator window located at the left-hand side of the interface.

Click “IP Catalog”.



Figure 100 - IP Catalog

In the IP Catalog window, expand the “Standard Bus Interface” by clicking the “>” sign beside it. Then locate “7 Series Integrated Block for PCI Express”.

Figure 101 - Integrated block for the PCIe

Right-click on “7 Series Integrated block for PCI Express” and select “Customize IP”.

Figure 102 - Customizing PCIe IP

Configure the settings in the “Basic” tab. Rename the “Component Name” to zc706_pcie_x4_gen2. Change the “Xilinx Development Board” to ZC706 and “Silicon Revision” to GES and Production. Change the “Lane Width” to X4 with a “Maximum Link Speed” of 5.0 GT/s. Ensure the “Reference Clock Frequency” is set at 100MHz.



Figure 103 - Customizing PCIe IP

Check the settings in the “IDs” tab, and ensure the following settings are correct:

Vendor ID is set to 10EE; Device ID is set to 7024

Revision ID is set to 00; Subsystem Vendor ID is set to 10EE, and

Subsystem ID is set to 0007

Figure 104 - Customizing PCIe IDs

Configure the settings under “BARs” tab. Enable the interface by ticking the “Bar0 Enabled” checkbox. Change the “Size Unit” to Megabyte and “Size Value” to 1. Click “OK”.



Figure 105 - Customizing PCIe BARs

Another dialog box will appear for the generation of output product. Leave the default settings and click “Generate”.

Figure 106 - Generating output product

A message dialog box will appear for the confirmation of generated product. Click “OK” to continue.

Figure 107 - Confirmation of generated output product

Check the Design Runs window at the bottom part of the Vivado interface to see if the process is complete. A checkmark beside zc706_pcie_x4_gen2_synth_1 is an indication that the processing is complete.



Figure 108 - Synthesizing the generated product

Xilinx Example Design Open an “IP Example Design” by selecting zc706_pcie_x4_gen2.xci under Design Sources in the Sources window.

Figure 109 - Sourcing the PCIe example project

In the resulting dialog box click on the three dots (“…”) beside the “Example project directory” field and locate the downloaded Xilinx example project. Tick the “Overwrite existing example project” checkbox. Click “OK” to continue.



Figure 110 – Targeting the PCIe example project

A new Vivado project will be open for the example project. This should be the Design Source Verilog

file name: xilinx_pcie_2_1_ep_7x.v

Figure 111 - Selecting the Verilog file under source

In the Verilog file, xilinx_pcie_2_1_ep_7x.v, add the following lines of code:

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property CFGBVS VCCO [current_design]

set_property CONFIG_VOLTAGE 3.3 [current_design]

This is rule specification for UG908 and UG912.

Figure 112 - Adding Verilog lines of code



In the Flow Navigator window, click on Generate Bitstream.

Figure 113 - Generate bitstream

Appendix C: Linux Boot Log

Xilinx Zynq MP First Stage Boot Loader

Release 2018.2 Aug 10 2018 - 22:23:05

NOTICE: ATF running on XCZU9EG/silicon v3/RTL5.1 at 0xfffea000

NOTICE: BL31: Secure code at 0x0

NOTICE: BL31: Non secure code at 0x8000000

NOTICE: BL31: v1.4(release):xilinx-v2018.1-4-g93a69a5a

NOTICE: BL31: Built : 21:19:07, Aug 10 2018

PMUFW: v1.0

U-Boot 2018.01 (Aug 10 2018 - 22:16:53 +0100) Xilinx ZynqMP ZCU102 rev1.0

I2C: ready

DRAM: 4 GiB

EL Level: EL2

Chip ID: zu9eg

MMC: sdhci@ff170000: 0 (SD)

SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB

*** Warning - bad CRC, using default environment

In: serial@ff000000

Out: serial@ff000000

Err: serial@ff000000

Board: Xilinx ZynqMP

Bootmode: LVL_SHFT_SD_MODE1

Net: ZYNQ GEM: ff0e0000, phyaddr ffffffff, interface rgmii-id

eth0: ethernet@ff0e0000

U-BOOT for ZCU102RC



ethernet@ff0e0000 Waiting for PHY auto negotiation to

complete......................................... TIMEOUT !

Hit any key to stop autoboot: 0

Device: sdhci@ff170000

Manufacturer ID: 3

OEM: 5344

Name: SU08G

Tran Speed: 50000000

Rd Block Len: 512

SD version 3.0

High Capacity: Yes

Capacity: 7.4 GiB

Bus Width: 4-bit

Erase Group Size: 512 Bytes

reading image.ub

15257480 bytes read in 1004 ms (14.5 MiB/s)

## Loading kernel from FIT Image at 10000000 ...

Using '[email protected]' configuration

Trying 'kernel@1' kernel subimage

Description: Linux kernel

Type: Kernel Image

Compression: gzip compressed

Data Start: 0x10000104

Data Size: 6959731 Bytes = 6.6 MiB

Architecture: AArch64

OS: Linux

Load Address: 0x00080000

Entry Point: 0x00080000

Hash algo: sha1

Hash value: 0b15e88d2dac7c071316af0a213bd49767566557

Verifying Hash Integrity ... sha1+ OK

## Loading ramdisk from FIT Image at 10000000 ...


Trying 'ramdisk@1' ramdisk subimage

Description: petalinux-user-image

Type: RAMDisk Image

Compression: gzip compressed

Data Start: 0x106aae70

Data Size: 8264582 Bytes = 7.9 MiB


OS: Linux

Load Address: unavailable

Entry Point: unavailable

Hash algo: sha1

Hash value: 05f2908212829fbc90aa708ff29ef24fb9d7730c


## Loading fdt from FIT Image at 10000000 ...


Trying '[email protected]' fdt subimage

Description: Flattened Device Tree blob

Type: Flat Device Tree

Compression: uncompressed

Data Start: 0x106a347c

Data Size: 31021 Bytes = 30.3 KiB


Hash algo: sha1

Hash value: f92d12381bbcd546eff986669591465f8f5e6c2c


Booting using the fdt blob at 0x106a347c

Uncompressing Kernel Image ... OK

Loading Ramdisk to 0781e000, end 07fffb86 ... OK

Loading Device Tree to 0000000007813000, end 000000000781d92c ... OK

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0



[ 0.000000] Linux version 4.14.0-xilinx-v2018.2 (oe-user@oe-host) (gcc version

7.2.0 (GCC)) #1 SMP Fri Aug 10 22:28:36 IST 2018

[ 0.000000] Boot CPU: AArch64 Processor [410fd034]

[ 0.000000] Machine model: xlnx,zynqmp

[ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8')

[ 0.000000] bootconsole [cdns0] enabled

[ 0.000000] efi: Getting EFI parameters from FDT:

[ 0.000000] efi: UEFI not found.

[ 0.000000] cma: Reserved 256 MiB at 0x000000006fc00000

[ 0.000000] psci: probing for conduit method from DT.

[ 0.000000] psci: PSCIv1.1 detected in firmware.

[ 0.000000] psci: Using standard PSCI v0.2 function IDs

[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.

[ 0.000000] percpu: Embedded 21 pages/cpu @ffffffc87ff79000 s46488 r8192 d31336

u86016

[ 0.000000] Detected VIPT I-cache on CPU0

[ 0.000000] CPU features: enabling workaround for ARM erratum 845719

[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1033987

[ 0.000000] Kernel command line: earlycon clk_ignore_unused

[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)

[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)

[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)

[ 0.000000] software IO TLB [mem 0x6bc00000-0x6fc00000] (64MB) mapped at

[ffffffc06bc00000-ffffffc06fbfffff]

[ 0.000000] Memory: 3776488K/4193280K available (9980K kernel code, 646K rwdata,

3132K rodata, 512K init, 2166K bss, 154648K reserved, 262144K cma-reserved)

[ 0.000000] Virtual kernel memory layout:

[ 0.000000] modules : 0xffffff8000000000 - 0xffffff8008000000 ( 128 MB)

[ 0.000000] vmalloc : 0xffffff8008000000 - 0xffffffbebfff0000 ( 250 GB)

[ 0.000000] .text : 0xffffff8008080000 - 0xffffff8008a40000 ( 9984 KB)

[ 0.000000] .rodata : 0xffffff8008a40000 - 0xffffff8008d60000 ( 3200 KB)

[ 0.000000] .init : 0xffffff8008d60000 - 0xffffff8008de0000 ( 512 KB)

[ 0.000000] .data : 0xffffff8008de0000 - 0xffffff8008e81a00 ( 647 KB)

[ 0.000000] .bss : 0xffffff8008e81a00 - 0xffffff800909f330 ( 2167 KB)

[ 0.000000] fixed : 0xffffffbefe7fd000 - 0xffffffbefec00000 ( 4108 KB)

[ 0.000000] PCI I/O : 0xffffffbefee00000 - 0xffffffbeffe00000 ( 16 MB)

[ 0.000000] vmemmap : 0xffffffbf00000000 - 0xffffffc000000000 ( 4 GB

maximum)

[ 0.000000] 0xffffffbf00000000 - 0xffffffbf1dc00000 ( 476 MB

actual)

[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc880000000 ( 34816 MB)

[ 0.000000] Hierarchical RCU implementation.

[ 0.000000] RCU event tracing is enabled.

[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.

[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4

[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

[ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000

[ 0.000000] GIC: Using split EOI/Deactivate mode

[ 0.000000] arch_timer: cp15 timer(s) running at 99.99MHz (phys).

[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles:

0x170f8dc196, max_idle_ns: 440795203664 ns

[ 0.000003] sched_clock: 56 bits at 99MHz, resolution 10ns, wraps every

4398046511099ns

[ 0.008234] Console: colour dummy device 80x25

[ 0.012491] console [tty0] enabled

[ 0.015857] bootconsole [cdns0] disabled

[ 0.000000] Booting Linux on physical CPU 0x0

[ 0.000000] Linux version 4.14.0-xilinx-v2018.2 (oe-user@oe-host) (gcc version

7.2.0 (GCC)) #1 SMP Fri Aug 10 22:28:36 IST 2018

[ 0.000000] Boot CPU: AArch64 Processor [410fd034]

[ 0.000000] Machine model: xlnx,zynqmp

[ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8')

[ 0.000000] bootconsole [cdns0] enabled

[ 0.000000] efi: Getting EFI parameters from FDT:

[ 0.000000] efi: UEFI not found.

[ 0.000000] cma: Reserved 256 MiB at 0x000000006fc00000

[ 0.000000] psci: probing for conduit method from DT.



[ 0.000000] psci: PSCIv1.1 detected in firmware.

[ 0.000000] psci: Using standard PSCI v0.2 function IDs

[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.

[ 0.000000] percpu: Embedded 21 pages/cpu @ffffffc87ff79000 s46488 r8192 d31336

u86016


[ 0.000000] CPU features: enabling workaround for ARM erratum 845719

[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1033987

[ 0.000000] Kernel command line: earlycon clk_ignore_unused

[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)

[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)

[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)

[ 0.000000] software IO TLB [mem 0x6bc00000-0x6fc00000] (64MB) mapped at

[ffffffc06bc00000-ffffffc06fbfffff]

[ 0.000000] Memory: 3776488K/4193280K available (9980K kernel code, 646K rwdata,

3132K rodata, 512K init, 2166K bss, 154648K reserved, 262144K cma-reserved)

[ 0.000000] Virtual kernel memory layout:

[ 0.000000] modules : 0xffffff8000000000 - 0xffffff8008000000 ( 128 MB)

[ 0.000000] vmalloc : 0xffffff8008000000 - 0xffffffbebfff0000 ( 250 GB)

[ 0.000000] .text : 0xffffff8008080000 - 0xffffff8008a40000 ( 9984 KB)

[ 0.000000] .rodata : 0xffffff8008a40000 - 0xffffff8008d60000 ( 3200 KB)

[ 0.000000] .init : 0xffffff8008d60000 - 0xffffff8008de0000 ( 512 KB)

[ 0.000000] .data : 0xffffff8008de0000 - 0xffffff8008e81a00 ( 647 KB)

[ 0.000000] .bss : 0xffffff8008e81a00 - 0xffffff800909f330 ( 2167 KB)

[ 0.000000] fixed : 0xffffffbefe7fd000 - 0xffffffbefec00000 ( 4108 KB)

[ 0.000000] PCI I/O : 0xffffffbefee00000 - 0xffffffbeffe00000 ( 16 MB)

[ 0.000000] vmemmap : 0xffffffbf00000000 - 0xffffffc000000000 ( 4 GB

maximum)

[ 0.000000] 0xffffffbf00000000 - 0xffffffbf1dc00000 ( 476 MB

actual)

[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc880000000 ( 34816 MB)

[ 0.000000] Hierarchical RCU implementation.

[ 0.000000] RCU event tracing is enabled.

[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.

[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4

[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

[ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000

[ 0.000000] GIC: Using split EOI/Deactivate mode

[ 0.000000] arch_timer: cp15 timer(s) running at 99.99MHz (phys).

[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles:

0x170f8dc196, max_idle_ns: 440795203664 ns

[ 0.000003] sched_clock: 56 bits at 99MHz, resolution 10ns, wraps every

4398046511099ns

[ 0.008234] Console: colour dummy device 80x25

[ 0.012491] console [tty0] enabled

[ 0.015857] bootconsole [cdns0] disabled

[ 0.019767] Calibrating delay loop (skipped), value calculated using timer

frequency.. 199.98 BogoMIPS (lpj=399960)

[ 0.019780] pid_max: default: 32768 minimum: 301

[ 0.019882] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)

[ 0.019899] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)

[ 0.020476] ASID allocator initialised with 65536 entries

[ 0.020528] Hierarchical SRCU implementation.

[ 0.020797] EFI services will not be available.

[ 0.020822] zynqmp_plat_init Platform Management API v1.0

[ 0.020830] zynqmp_plat_init Trustzone version v1.0

[ 0.020929] smp: Bringing up secondary CPUs ...


[ 0.021202] CPU1: Booted secondary processor [410fd034]





[ 0.021814] smp: Brought up 1 node, 4 CPUs

[ 0.021845] SMP: Total of 4 processors activated.

[ 0.021853] CPU features: detected feature: 32-bit EL0 Support

[ 0.021863] CPU: All CPU(s) started at EL2



[ 0.021880] alternatives: patching kernel code

[ 0.022573] devtmpfs: initialized

[ 0.025580] random: get_random_u32 called from bucket_table_alloc+0x108/0x260

with crng_init=0

[ 0.025729] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff,

max_idle_ns: 7645041785100000 ns

[ 0.025750] futex hash table entries: 1024 (order: 5, 131072 bytes)

[ 0.031125] xor: measuring software checksum speed

[ 0.067841] 8regs : 2302.000 MB/sec

[ 0.107870] 8regs_prefetch: 2052.000 MB/sec

[ 0.147904] 32regs : 2830.000 MB/sec

[ 0.187931] 32regs_prefetch: 2381.000 MB/sec

[ 0.187939] xor: using function: 32regs (2830.000 MB/sec)

[ 0.188004] pinctrl core: initialized pinctrl subsystem

[ 0.188178] random: fast init done

[ 0.188502] NET: Registered protocol family 16

[ 0.189246] cpuidle: using governor menu

[ 0.189563] vdso: 2 pages (1 code @ ffffff8008a46000, 1 data @ ffffff8008de4000)

[ 0.189579] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

[ 0.190027] DMA: preallocated 256 KiB pool for atomic allocations

[ 0.219507] reset_zynqmp reset-controller: Xilinx zynqmp reset driver probed

[ 0.220065] ARM CCI_400_r1 PMU driver probed

[ 0.224820] zynqmp-pinctrl ff180000.pinctrl: zynqmp pinctrl initialized

[ 0.231987] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages

[ 0.300179] raid6: int64x1 gen() 403 MB/s

[ 0.368160] raid6: int64x1 xor() 447 MB/s

[ 0.436226] raid6: int64x2 gen() 688 MB/s

[ 0.504240] raid6: int64x2 xor() 603 MB/s

[ 0.572277] raid6: int64x4 gen() 1042 MB/s

[ 0.640351] raid6: int64x4 xor() 742 MB/s

[ 0.708423] raid6: int64x8 gen() 980 MB/s

[ 0.776439] raid6: int64x8 xor() 745 MB/s

[ 0.844562] raid6: neonx1 gen() 727 MB/s

[ 0.912564] raid6: neonx1 xor() 853 MB/s







[ 1.320881] raid6: using algorithm neonx8 gen() 1652 MB/s

[ 1.320888] raid6: .... xor() 1533 MB/s, rmw enabled

[ 1.320896] raid6: using neon recovery algorithm

[ 1.321713] SCSI subsystem initialized

[ 1.321883] usbcore: registered new interface driver usbfs

[ 1.321919] usbcore: registered new interface driver hub

[ 1.321952] usbcore: registered new device driver usb

[ 1.322019] media: Linux media interface: v0.10

[ 1.322047] Linux video capture interface: v2.00

[ 1.322086] pps_core: LinuxPPS API ver. 1 registered

[ 1.322094] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti

<[email protected]>

[ 1.322115] PTP clock support registered

[ 1.322140] EDAC MC: Ver: 3.0.0

[ 1.322440] zynqmp-ipi ff9905c0.mailbox: Probed ZynqMP IPI Mailbox driver.

[ 1.322580] FPGA manager framework

[ 1.322687] fpga-region fpga-full: FPGA Region probed

[ 1.322771] Advanced Linux Sound Architecture Driver Initialized.

[ 1.323013] Bluetooth: Core ver 2.22


[ 1.323050] Bluetooth: HCI device and connection manager initialized

[ 1.323061] Bluetooth: HCI socket layer initialized

[ 1.323071] Bluetooth: L2CAP socket layer initialized

[ 1.323089] Bluetooth: SCO socket layer initialized

[ 1.323550] clocksource: Switched to clocksource arch_sys_counter

[ 1.323622] VFS: Disk quotas dquot_6.6.0

[ 1.323664] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)




[ 1.327881] TCP established hash table entries: 32768 (order: 6, 262144 bytes)

[ 1.328092] TCP bind hash table entries: 32768 (order: 7, 524288 bytes)

[ 1.328475] TCP: Hash tables configured (established 32768 bind 32768)

[ 1.328546] UDP hash table entries: 2048 (order: 4, 65536 bytes)

[ 1.328623] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)


[ 1.328964] RPC: Registered named UNIX socket transport module.

[ 1.328974] RPC: Registered udp transport module.

[ 1.328981] RPC: Registered tcp transport module.

[ 1.328988] RPC: Registered tcp NFSv4.1 backchannel transport module.

[ 1.329083] Trying to unpack rootfs image as initramfs...

[ 1.653273] Freeing initrd memory: 8068K

[ 1.653615] hw perfevents: no interrupt-affinity property for /pmu, guessing.

[ 1.653768] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters

available

[ 1.654415] audit: initializing netlink subsys (disabled)

[ 1.654498] audit: type=2000 audit(1.640:1): state=initialized audit_enabled=0

res=1

[ 1.654808] workingset: timestamp_bits=62 max_order=20 bucket_order=0

[ 1.655466] NFS: Registering the id_resolver key type

[ 1.655487] Key type id_resolver registered

[ 1.655495] Key type id_legacy registered

[ 1.655507] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

[ 1.655527] jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.

[ 1.681843] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)

[ 1.681863] io scheduler noop registered

[ 1.681870] io scheduler deadline registered

[ 1.681890] io scheduler cfq registered (default)

[ 1.681899] io scheduler mq-deadline registered

[ 1.681906] io scheduler kyber registered

[ 1.682516] nwl-pcie fd0e0000.pcie: Link is UP

[ 1.682559] OF: PCI: host bridge /amba/pcie@fd0e0000 ranges:

[ 1.682581] OF: PCI: MEM 0xe0000000..0xefffffff -> 0xe0000000

[ 1.682593] OF: PCI: MEM 0x600000000..0x7ffffffff -> 0x600000000

[ 1.682718] nwl-pcie fd0e0000.pcie: PCI host bridge to bus 0000:00

[ 1.682732] pci_bus 0000:00: root bus resource [bus 00-ff]

[ 1.682743] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff]

[ 1.682754] pci_bus 0000:00: root bus resource [mem 0x600000000-0x7ffffffff

pref]

[ 1.683250] pci 0000:00:00.0: BAR 8: assigned [mem 0xe0000000-0xe00fffff]

[ 1.683265] pci 0000:01:00.0: BAR 0: assigned [mem 0xe0000000-0xe00fffff]

[ 1.683279] pci 0000:00:00.0: PCI bridge to [bus 01-0c]

[ 1.683291] pci 0000:00:00.0: bridge window [mem 0xe0000000-0xe00fffff]

[ 1.684050] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success








[ 1.685255] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success

[ 1.685400] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success

[ 1.685541] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success

[ 1.685684] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success

[ 1.685833] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success

[ 1.685980] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success

[ 1.686126] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success

[ 1.686270] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success

[ 1.710855] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

[ 1.713586] cacheinfo: Unable to detect cache hierarchy for CPU 0

[ 1.717681] brd: module loaded

[ 1.720973] loop: module loaded

[ 1.721818] mtdoops: mtd device (mtddev=name/number) must be supplied

[ 1.722846] m25p80 spi0.0: n25q512a (131072 Kbytes)

[ 1.722869] 3 ofpart partitions found on MTD device spi0.0



[ 1.722877] Creating 3 MTD partitions on "spi0.0":

[ 1.722887] 0x000000000000-0x000000100000 : "boot"

[ 1.723294] 0x000000100000-0x000000140000 : "bootenv"

[ 1.723690] 0x000000140000-0x000001740000 : "kernel"

[ 1.724863] libphy: Fixed MDIO Bus: probed

[ 1.725805] tun: Universal TUN/TAP device driver, 1.6

[ 1.725942] CAN device driver interface

[ 1.726966] macb ff0e0000.ethernet: Not enabling partial store and forward

[ 1.727338] libphy: MACB_mii_bus: probed

[ 1.731197] macb ff0e0000.ethernet eth0: Could not attach to PHY

[ 1.760523] usbcore: registered new interface driver asix

[ 1.760578] usbcore: registered new interface driver ax88179_178a

[ 1.760607] usbcore: registered new interface driver cdc_ether

[ 1.760635] usbcore: registered new interface driver net1080

[ 1.760664] usbcore: registered new interface driver cdc_subset

[ 1.760693] usbcore: registered new interface driver zaurus

[ 1.760730] usbcore: registered new interface driver cdc_ncm

[ 1.761016] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM

[ 1.761420] usbcore: registered new interface driver uas

[ 1.761459] usbcore: registered new interface driver usb-storage

[ 1.761904] rtc_zynqmp ffa60000.rtc: rtc core: registered ffa60000.rtc as rtc0

[ 1.761951] i2c /dev entries driver

[ 1.762293] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 33

[ 1.762618] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 34

[ 1.762804] IR NEC protocol handler initialized

[ 1.762813] IR RC5(x/sz) protocol handler initialized

[ 1.762820] IR RC6 protocol handler initialized

[ 1.762827] IR JVC protocol handler initialized

[ 1.762834] IR Sony protocol handler initialized

[ 1.762841] IR SANYO protocol handler initialized

[ 1.762847] IR Sharp protocol handler initialized

[ 1.762854] IR MCE Keyboard/mouse protocol handler initialized

[ 1.762862] IR XMP protocol handler initialized

[ 1.763783] usbcore: registered new interface driver uvcvideo

[ 1.763791] USB Video Class driver (1.1.1)

[ 1.764267] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer at

ffffff8009135000 with timeout 10s

[ 1.764431] Bluetooth: HCI UART driver ver 2.3

[ 1.764441] Bluetooth: HCI UART protocol H4 registered

[ 1.764449] Bluetooth: HCI UART protocol BCSP registered

[ 1.764475] Bluetooth: HCI UART protocol LL registered

[ 1.764483] Bluetooth: HCI UART protocol ATH3K registered

[ 1.764491] Bluetooth: HCI UART protocol Three-wire (H5) registered

[ 1.764531] Bluetooth: HCI UART protocol Intel registered

[ 1.764539] Bluetooth: HCI UART protocol QCA registered

[ 1.764574] usbcore: registered new interface driver bcm203x

[ 1.764609] usbcore: registered new interface driver bpa10x

[ 1.764643] usbcore: registered new interface driver bfusb

[ 1.764675] usbcore: registered new interface driver btusb

[ 1.764684] Bluetooth: Generic Bluetooth SDIO driver ver 0.1

[ 1.764733] usbcore: registered new interface driver ath3k

[ 1.764851] EDAC MC: ECC not enabled

[ 1.764995] EDAC DEVICE0: Giving out device to module zynqmp-ocm-edac controller

zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)

[ 1.765434] cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 1199880 KHz

[ 1.765487] cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed

to: 1199999 KHz

[ 1.765844] sdhci: Secure Digital Host Controller Interface driver

[ 1.765853] sdhci: Copyright(c) Pierre Ossman

[ 1.765860] sdhci-pltfm: SDHCI platform and OF driver helper

[ 1.811565] mmc0: SDHCI controller on ff170000.sdhci [ff170000.sdhci] using ADMA

64-bit

[ 1.817462] ledtrig-cpu: registered to indicate activity on CPUs

[ 1.817609] usbcore: registered new interface driver usbhid

[ 1.817618] usbhid: USB HID core driver

[ 1.819480] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered



[ 1.822216] pktgen: Packet Generator for packet performance testing. Version:

2.75

[ 1.822399] Netfilter messages via NETLINK v0.30.

[ 1.822513] ip_tables: (C) 2000-2006 Netfilter Core Team

[ 1.822690] Initializing XFRM netlink socket


[ 1.823112] Segment Routing with IPv6

[ 1.823156] ip6_tables: (C) 2000-2006 Netfilter Core Team

[ 1.823267] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver



[ 1.823620] bridge: filtering via arp/ip/ip6tables is no longer available by

default. Update your scripts to load br_netfilter if you need this.

[ 1.823634] Ebtables v2.0 registered

[ 1.823720] can: controller area network core (rev 20170425 abi 9)


[ 1.823769] can: raw protocol (rev 20170425)

[ 1.823777] can: broadcast manager protocol (rev 20170425 t)

[ 1.823788] can: netlink gateway (rev 20170425) max_hops=1

[ 1.823961] Bluetooth: RFCOMM TTY layer initialized

[ 1.823973] Bluetooth: RFCOMM socket layer initialized

[ 1.823987] Bluetooth: RFCOMM ver 1.11

[ 1.823997] Bluetooth: BNEP (Ethernet Emulation) ver 1.3

[ 1.824005] Bluetooth: BNEP filters: protocol multicast

[ 1.824015] Bluetooth: BNEP socket layer initialized

[ 1.824023] Bluetooth: HIDP (Human Interface Emulation) ver 1.2

[ 1.824035] Bluetooth: HIDP socket layer initialized

[ 1.824134] 9pnet: Installing 9P2000 support

[ 1.824153] Key type dns_resolver registered

[ 1.824480] registered taskstats version 1

[ 1.824807] Btrfs loaded, crc32c=crc32c-generic

[ 1.830890] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 46, base_baud =

6249375) is a xuartps

[ 1.979846] mmc0: new high speed SDHC card at address aaaa

[ 1.987358] mmcblk0: mmc0:aaaa SU08G 7.40 GiB

[ 1.994868] mmcblk0: p1

[ 3.466360] console [ttyPS0] enabled

[ 3.470326] ff010000.serial: ttyPS1 at MMIO 0xff010000 (irq = 47, base_baud =

6249375) is a xuartps

[ 3.480800] rtc_zynqmp ffa60000.rtc: setting system clock to 2018-08-20 15:28:41

UTC (1534778921)

[ 3.489692] clk: Not disabling unused clocks

[ 3.493915] ALSA device list:

[ 3.496830] No soundcards found.

[ 3.500582] Freeing unused kernel memory: 512K

INIT: version 2.88 booting

Starting udev

[ 3.609008] udevd[1677]: starting version 3.2.2

[ 3.618035] udevd[1678]: starting eudev-3.2.2

[ 4.041747] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may

be corrupt. Please run fsck.

Starting internet superserver: inetd.

Configuring packages on first boot....

(This may take several minutes. Please do not power off the machine.)

Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...

update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)

INIT: Entering runlevel: 5

Configuring network interfaces... Cannot find device "eth0"

Starting Dropbear SSH server: Generating key, this may take a while...

Public key portion is:

ssh-rsa

AAAAB3NzaC1yc2EAAAADAQABAAABAQC2+0QjpiljgI7PsGHPdavD2iCTktxdq4AthLLiFvkG00RVV/UKo/e

q9PYwcXoD3JX2r3Uxgcv4MPW/XhOhNgh029KM2zM1x19Q8igiOjYZrPTMDhvwzjO0Al7UT/38DPvxv+iAw1

NRmAFHfZgKhzpRLD+JMrRTm2lOF73Sl1VhRD8nmVEvAykBPl14B69/6h/ja9CBgxhU9/x/fto9CrCJKn/mB

tsqEH+8fzW2kNCLoeAUfoPsYnBup3peYwqTfMdXUvyM90MQjRqVLM10LZl/F0Hk7nT3P43Y8yt/R/oIpSA0

Cog6ww4Q1fosKan3jLNuFxIPhwe/eyGemD6Ic98F root@ZCU102RC

Fingerprint: md5 7b:8d:be:4f:52:f2:a9:8c:66:d5:2c:de:a4:29:87:fb



dropbear.

Starting syslogd/klogd: done

Starting tcf-agent: OK

PetaLinux 2018.2 ZCU102RC /dev/ttyPS0

ZCU102RC login: root

Password:

root@ZCU102RC:~# lspci

00:00.0 PCI bridge: Xilinx Corporation Device d021

01:00.0 Memory controller: Xilinx Corporation Device 7024

root@ZCU102RC:~# lspci -vvv

00:00.0 PCI bridge: Xilinx Corporation Device d021 (prog-if 00 [Normal decode])

Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-

Stepping- SERR- FastB2B- DisINTx-

Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-

<MAbort- >SERR- <PERR- INTx-

Interrupt: pin A routed to IRQ 255

Bus: primary=00, secondary=01, subordinate=0c, sec-latency=0

I/O behind bridge: 00000000-00000fff [size=4K]

Memory behind bridge: e0000000-e00fffff [size=1M]

Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff

[empty]

Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-

<MAbort- <SERR- <PERR-

BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-

PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-

Capabilities: [40] Power Management version 3

Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA

PME(D0+,D1+,D2+,D3hot+,D3cold-)

Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-

Capabilities: [60] Express (v2) Root Port (Slot-), MSI 00

DevCap: MaxPayload 256 bytes, PhantFunc 0

ExtTag- RBE+

DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-

RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+

MaxPayload 128 bytes, MaxReadReq 512 bytes

DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend+

LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM not supported

ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+

LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-

ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-

LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+

BWMgmt- ABWMgmt+

RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna-

CRSVisible+

RootCap: CRSVisible+

RootSta: PME ReqID 0000, PMEStatus- PMEPending-

DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR-, OBFF Not

Supported ARIFwd-

AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-

DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF

Disabled ARIFwd-

AtomicOpsCtl: ReqEn- EgressBlck-

LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-

Transmit Margin: Normal Operating Range,

EnterModifiedCompliance- ComplianceSOS-

Compliance De-emphasis: -6dB

LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-,

EqualizationPhase1-

EqualizationPhase2-, EqualizationPhase3-,

LinkEqualizationRequest-

Capabilities: [100 v1] Device Serial Number 00-00-00-00-00-00-00-00

Capabilities: [10c v1] Virtual Channel

Caps: LPEVC=0 RefClk=100ns PATEntryBits=1

Arb: Fixed- WRR32- WRR64- WRR128-

Ctrl: ArbSelect=Fixed



Status: InProgress-

VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-

Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-

Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff

Status: NegoPending- InProgress-

Capabilities: [128 v1] Vendor Specific Information: ID=1234 Rev=1 Len=018

<?>

01:00.0 Memory controller: Xilinx Corporation Device 7024

Subsystem: Xilinx Corporation Device 0007

Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-

Stepping- SERR- FastB2B- DisINTx-

Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-

<MAbort- >SERR- <PERR- INTx-

Interrupt: pin A routed to IRQ 255

Region 0: Memory at e0000000 (32-bit, non-prefetchable) [disabled]

[size=1M]

Capabilities: [40] Power Management version 3

Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA

PME(D0+,D1+,D2+,D3hot+,D3cold-)

Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-

Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+

Address: 0000000000000000 Data: 0000

Capabilities: [60] Express (v2) Endpoint, MSI 00

DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1

unlimited

ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-

SlotPowerLimit 0.000W

DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-

RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+

MaxPayload 128 bytes, MaxReadReq 512 bytes

DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-

LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s, Exit Latency L0s

unlimited

ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-

LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-

ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-

LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive-

BWMgmt- ABWMgmt-

DevCap2: Completion Timeout: Range B, TimeoutDis-, LTR-, OBFF Not

Supported

AtomicOpsCap: 32bit- 64bit- 128bitCAS-

DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF

Disabled

AtomicOpsCtl: ReqEn-

LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-

Transmit Margin: Normal Operating Range,

EnterModifiedCompliance- ComplianceSOS-

Compliance De-emphasis: -6dB

LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-,

EqualizationPhase1-

EqualizationPhase2-, EqualizationPhase3-,

LinkEqualizationRequest-

Capabilities: [100 v1] Device Serial Number 00-00-00-01-01-00-0a-35

root@ZCU102RC:~#



References

Zynq PCI Express Root Complex Made Simple. https://www.youtube.com/watch?v=D1vOFBSuWAc

Root Port Made Simple for Zynq UltraScale+. https://www.youtube.com/watch?v=_jIw5ON0h7s

PetaLinux Tools Documentation Reference Guide

Zynq-7000 All Programmable SoC: Embedded Design Tutorial: A Hands-On Guide to Effective Embedded System Design.

Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator

Vivado Tutorial Using IP Integrator.

Revision History

09/10/2018 - Initial release

https://www.youtube.com/watch?v=D1vOFBSuWAc

https://www.youtube.com/watch?v=_jIw5ON0h7s

Date post:	08-Aug-2020
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ZCU102 Root Complex Design in Vivado - Xilinx...the “.hdf” file is inside the “hdf_zcu102rc”...

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