ZERO VOLTAGE SWTCHING

FLYBACK ANI) FORWARD CONVERTER TOPOLOGIES

Youhao Xi

A Thesis

in

The Department

of

Electrical and Computer Engineering

Presented in Partial Fulfillment of the Requirements for the Degree of Master of Applied Science at

Concordia University Montréal, Québec, Canada

June 1997

O Youhao Xi, 1997

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Zero voltage switching flyback and forward converter topologies

Youhao Xi

Advanced telecornmunication and cornputer systems demand high efficiency and

high power density, dihbuted power supplies. Both the flyback and fonvard converter

topologies are good candidates for these applications, owing to their simple circuitry.

These topologies, however, require practical performance improvements.

Improved zero voltage switching (ZVS) flyback and forward dddc converter

topologies are developed in this thesis. They employ an auxiliary circuit, with oniy a few

small components and switching devices, to achieve ZVS of the main switch. Steady state

analyses are performed and show that the proposed topologies have the following rnents:

lossless switching of the main switch independent of the line and load conditions. no

increase in conduction losses, simple power and control circuitry, and capability of

operating in either voltage or current mode control.

The srnall signal analysis and closed loop stability of the proposed topologies are

also derived. The resulting compensation required for stable operation is obtained and

shown to be straightfonvard.

The steady state and small signal analyses are verified on a 50W prototype

flyback converter switching at 200 kHz, and on a 100 W prototype fonvard converter

switching at 300 kHz, respectively. Experirnental results show that both the flyback and

forward converters have about 5 to 7% higher efficiencies than the conventional hard

switching converters for typicd efficiencies of 70% and 85%, respectively. These

topologies can therefore advantageously replace existing power supplies in advanced

telecommunications and cornputer applications.

1 would like to express my sincere gratitude to my supervisors, Dr. P. K. Jain and

Dr. G. Jobs, for their guidance, encouragement, fnendship and support, during the course

of this study.

Special th& to Norte1 Power Group (Ottawa) for their generous oEer of

components, devices and data sheds, for work related to this thesis. The financial support

provided through a BNR/NSEC Collaborative R&D Grant is highiy appreciated.

I am grateful for the International Tuition Remission through the agreement

between the Chinese Embassy and Québec Government.

I would like ro thank my colleagues at the Power Electronics Laboratory very

much for their kindness and help in every aspect, and for the nurnerous valuable

discussions we have shared.

Finally, 1 would like to express rny thanks to my wife, my siblings, and my

dearest parents, for their everlasting love, spiritual encouragement and strong support,

during these years.

................................................................................. List of Figures ... .............................. x

... .................................................................................................................. List of Tables x i i r

............................................................................................................ List of Acronyms xiv

List of Primary Symbols .......... .. ............................. .. ................................................ xv

CHAPTER 1 Introduction

1.1 Power Supplies for Telecommunication and Computer

1.2 Flyback and Fonvard Topologies ................................................................................

.................................................... 1.3 Problems with Standard Topolo~ies and Solutions 4

1.4 Review of Existing ZVS Flyback/Fonvard Topologies ............................................. 5

S ystems ............................... 1

9

Active Clamp Topology .................................................................................... 5

..................................................................... . Mirrored Structure' Topology -6

Passive Non-dissipative Snubber FlybacWFonvard Topologies ...................... 7

...................................................................... 1.5 Scope and Contributions of this Thesis 8

............................................................................................................. 1.6 Thesis Outline 9

CHAPTER 2 A ZVS Flyback Converter Topology

.............................................................................................................. 2.1 Introduction 1 1

. . .................................................................................................... 2.2 Circuit Descnption 12

............................................................................................... 2.3 Modes of Operation 1 3

................................................................................................ 2.4 Steady State Analysis 17

............................................................................................................. 2.5 Performance 26

............................................................. 2.5.1 Effects of the Non-Ideal Components 26

2.5.2 Determination of Duty Cycle for the Output Regdation ................................ 28

............................ 2.5.3 Advantages and Disadvantages of the Proposed Converter 29

......................................... 2.5 -4 RMS, Average, Peak Current and Voltage Values 30

.......................................................... 2.5.5 Losses Caused by the Auxiliary Circuit 32

......................................................... 2.5.6 Losses Removed by ihe ZVS Operation 33

............................................................................................... 2.6 Experimental Results 33

............................................................... 2.6.1 Experiment Setup ..................... ... -33

................................................................ 2.6.2 Key Waveforms ........................ ... 34

....................................................................................................... 2.6.3 Efficiency -38

.............................................................................................................. 2.7 Conclusions 39

CHAPTER 3 A ZVS Forward Converter Topology

.......................................................................... Introduction .... ................................. 41

. . . . Circuit Descnption .................................................................................................... 42

Modes of Operation ................................................................................................. 43

............................................................................................. Steady State Analyses -48

............................................................................................................. Performance 60

....... ..............................*.... Effects of the Non-Edeal Components/Devices ..... 60

................... Determination of Duty Cycle as to Regulate the Output Voltage 61

Advantages and Disadvantages of the Proposed Converter ............................ 62

................................................................... RMS or Average Current Values -63

vii

........................ .............................. 3 S.5 Losses Caused by the Auxiliary Circuit .... 65

......................................................... 3 S.6 Losses Removed due to ZVS Operation 65

............................................................................................. 3 -6 Experimental Results -66

............................................................................................ 3 .6.1 Experiment Setup 66

............................................................................................... 3 .6.2 Key Waveforms 67

.................................................................................................... 3 .6.3 Efficiency -73

.............................................................................................................. 3 -7 Conclusions 75

CHAPTER 4 Small Signal Models and Closed Loop Stability

......................................................................................... .......... Introduction .... -77

................................................................ Criteria of a Dynamicdly Stable System 78

.............................................. Small Signal Models of the ZVS Flyback Converter 79

............... 4.3.1 Small Signal Mode1 of the Current Loop of the Flyback Converter 81

.............. 4.3.2 Small Signal Mode1 of the Voltage Loop of the Flyback Converter 84

.............................................. Small Signal Models of the ZVS Fonvard Converter 87

...... 4.4.1 Small Signal Model of the Current Loop of the ZVS Forward Converter 88

................................................. 4.4.2 Voltage Loop of the ZVS Forward Converter 93

............................................................................................... Experimental Results -94

..................................................................................... ............. Conclusions .... -98

CRAPTER 5 Design Procedures

............................................................................................................... 5.1 Introduction 99

........................................................... 5.2 Design Procedure of the Flyback Converter 100

......................................................................... 5.2.1 Design of the Power Circuit 1 0 0

.................................................................. 5.2.2 Design of the Auxiliary Circuit 1 03

......................................... 5.2.3 A Design Example ........................................... 107

5.3 Design Procedure of the Forward Converter .......................................................... 108

............................................ 5 .3.1 Design of the Power Circuit ......................... .. 108

5.3.2 Design of the Awciliary Circuit .............................. .. ............................. 111

......................................................................................... 5.3.3 A Design Example 113

................... ........................ 5.4 Gating Generation for the Awliary Switch .... 115

5.4.1 Gating Pattern Generation by Additional Logic and Drive Circuit ............... 115

.............................................................................. 5 .4.2 The Design of the Splitter 117

........................................................................................ 5.4.3 A Design Example 1 8

CHAPTER 6 Conclusions

6.1 Summary ................................................................................................................. 120

............................................................................... 6.2 Conclusions and Contributions 121

................................................................................... 6.3 Suggestion for Future Work 1 2 2

............................................................................................................. REFERENCE -124

APPENDIX

1 The Control Chip UC3855 ..................................................................................... A-l

................................................................... II Schematic of the prototype converters A-2

Fig . 1.1

Fig . 1.2

Fig . 1.3

Fig . 1.4

Fig . 1.5

Fig . 2.1

Fig . 2.2

Fig . 2.3

Fig . 2.4

Fig . 2.5

Fig . 2.6

Fig . 2.7

Fig . 2.8

Fig . 2.9

Fig . 2.10

Fig . 2.1 1

Fig . 2.12

Fig . 3-1

............................................................................. A flyback converter topology 2

A fonvard converter topology ................................ .. ...................................... -3

An active clamp forward converter topology ..................................................... 6

The 'mirror-structured' ZVS flyback topology ................................................. -7

A fonvard converter with a non-dissipative snubber .......................................... 8

.............................................. The proposed ZVS flyback converter topology 12

. Key waveforms of the convener of Fig 2.1 ..................................................... 14

. ............................................... Modes of operation of the converter of Fig 2.1 15

The equivalent circuit of the discharging resonant loop in Interval 1 .............. 15

Theoretical results: the drain voltage and current waveforms of QI ................ 34

...... The experimental results: the drain voltage and curent waveforms of Q I 35

................ Theoretical results: the drain voltage and current waveforms of Q2 35

The expenmental results of the drain voltage and current waveforms of 0 2 - 3 6

The experimental results : the current and voltage waveforms of the main

3 switch in ZVS operation under light load conditions ...................................... 37

The current and voltage waveforms of the auxiliary switch under light load

............................................................................ conditions .................... l... 37

The overall effïciency of the converter vs . input AC voltage .................................. 38

The overall efficiency vs . load under given input voltage ................................ 38

............................................... The proposed ZVS forward converter topology 42

. *.................... Fig . 3.2 Key waveforms of the converter of Fig 3.2 .. .............. ... . ............................................... Fig . 3.3 Modes of operation of the converter of Fig 3.1 45

Fig . 3.4 The equivaient circuit of the discharging process in Interval 1 ........................ 46

Fig . 3.5 The equivalent circuit of the discharging process in Interval 5 ........................ 46

Fig . 3.6 The drain voltage and current waveforms of Ql in Fig . 3.1 (theoretical) ........ 67

Fig . 3.7 The experimental results of the drain voltage and current waveforms of QL.68

Fig . 3.8 The drairi voltage and current waveforms of Q2 in Fig . 3.1 (theoretical) ........ 69

Fig . 3.9 The experimental results of the drain voltage and current waveforms of Q1 ... 69

....... Fig . 3.10 Experimental results: the current and voltage of QI at high line full load 70

..... Fig . 3.1 1 Experimental results: the current and voltage of QI at high line Iight load 70

........ Fig . 3.12 Experimental results: the current and voltage of QI at low line full load 71

...... Fig . 3.13 Experimental results: the current and voltage of QI at low line light load 71

Fig . 3.14 Experimental results: the current and voltage of Q2 at medium line half load ....

......................................................................................................................... -72

..... Fig . 3.15 Experimental results: the current and voltage of Q2 at high line light load 72

....... Fig . 3.16 Experimental results: the current and voltage of Q2 at low line half load 73

Fig . 3.17 The efficiency vs . input voltage of the prototype converter ............................. 74

........................................... Fig . 3.18 The efficiency vs . load of the prototype converter 74

........................................................... Fig . 4.1 The Block diagram of the control loops 80

. ............................ Fig . 4.2 A typical implementation of the feedback loops of Fig 4.1 80

..... Fig . 4.3 The Bode plot of the open current loop of the prototype flyback converter 82

Fig . 4.4 The Bode plot of the open voltage loop of the prototype flyback converter ..... 86

Fig . 4.5 A typical Block diagram of the control loops of the fonvard converter ............ 87

Fig . 4.6

Fig . 4.7

Fig . 4.8

Fig . 4.9

Fig . 4.10

Fig . 4.1 1

Fig . 4.12

A typical implementation of the feedback loops o f Fig . 4.5 .......................... -87

The reconstruction of the sensed current in the proposed ZVS forward

............................................................................................................ converter 88

The Bode plot of the open current loop of the prototype forward converter ..... 91

The Bode plot of the open voltage loop of the prototype fonvard converter .... 93

Ccrnparison between the experimental and theoretical gain of the open voltage loop

power circuit ................................................................................................. ......95

Cornparison between the phase shift of the open voltage loop power circuit transfer

................................................................................... ............... function ...... -96

Experimental results of the fornard converter: transient response (Io step up) ....

97

Fig . 4.13 Experimental results of the fonvard converter: transient response (1, step

Fig . 4.14

Fig . 5.1

Fig . 5.2

Fig . 5.3

Fig . 5.4

................................................................................................................ doum) -97

Experimental results of the fonvard converter: transient response (K,, step

................................................................................................................ d o m ) -98

The secondary current and the output voltage ripples in the flyback converter ...

............................................................................................................. 101

A gating generation circuit, a splitter ............................................................. 1 16

. .................................................... Key waveforms of the splitter o f Fig 5.2 1 16

.............. Experimental results of the gating pattern generated by the splitter 1 18

xii

Table 1.1

Table 2.1

Table 2.2

Table 3.1

Table 3.2

Table 4.1

Table 5.1

Table 5.2

Table 5.3

Comparison between the two topologies based on the same powe :r leveI and

........................................ ................................... ... operating fiequenc y .. ... -3

Comparison between the theoretical and experimental results of the current

............. ...............*........*.......*...*................... and voltage of the main switch .. 35

Comparison between the theoretical and experimental results of the current

- . and voltage of the auxiliary switch.. .............................................................. 3 6

Cornparison between the theoretical and experimental results of the current

and voltage of the main switch .............. .. ..................................................... 67

Cornparison between the theoretical and experimental results of the current

................................................................. and voltage of the auxiliary switch 68

The theoretical and experimental resuIts of the power circuit transfer function

......................... .. .......................................................................................... 94

...................................... The parameters of die prototype flyback converter 107

................................... The parameters of the prototype forward converter 1 14

The parameters of the splitter in a design example ............................ . 1 1 9

AC

CA

DC

EMI

IC

MOSFET

PCB

PI

P W M

rrns

VA

ZCS

zvs

Alternative Current

enor Current Amplifier

Direct Current

Electromagnetic Interference

Integrated Circuit

Metal-Oxide-Semiconductor Field Effect Transistor

Printed Circuit Board

Proportional-Integral network

PuIse Width Modulation

Root Mean Square value

error Voltage AmpIifier

Zero Current Switching

Zero Voltage Switching

xiv

O, angdar frequency given by I/JK

a,, angdar fiequency given by I/ JG for the flyback topoiogy, and by

2 / (L C ) for the forward topology ,,/y or angdar frequency given by

C, input capacitor of a dddc converter

Co output capacitor

$Il* snubber capacitor

D, primary side blocking diode of the auxiliary circuit

D, secondary side blocking diode of the auxiliary circuit

Do, rectifier diode in the output stage

DO? freewheeling diode in the output stage

D nominal duty cycle of the main switch

Dm duty cycle of the auxiliary switch

Dm_ maximum duty cycle of the main switch

Dm, minimum duty cycle of the main switch

De effective duty cycle of the main switch in the forward topology

D, reduction in duty cycle of the main switch by L in the forward topology

d small signai deviation of D in Laplace transformation

2, small signal deviation of LIr in Laplace transformation

f , cross over frequency of an open Ioop system

4 a pole of a transfer function

f - a zero of a tramfer function

f , switching frequency

G,-+-(s) transfer fünction of the error current amplifier compensation network

Gi,,(s) closed loop transfer function of the current loop

GJs) transfer function of the voltage loop power circuit

Gu@) transfer function of the error voltage amplifier compensation network

Hl@) transfer function of current loop po wer circuit

H,(s) transfer function of the output stage of voltage loop

I~P primary peak current of the awciliary circuit

Iar secondary peak current of the auxiliary circuit

IO nominal output curent

lpeak peak switch current of the flyback topology

lm instantaneous magnetizing current in the fonvard topology

jS instantaneous secondary current of the power transformer

*

i, small signal deviation of the output inductor current in Laplace transformation

A

i, small signal deviation of the output current in Laplace transformation

K turns ratio of the current sensor transformer

k deviation factor of Vo from y,,

Lw primary of the coupled inductors of the auxiliary circuit

Lm secondary of the coupled inductors of the auxiliary circuit

xvi

magnetizing inductor of Tr

output inductor

additional secondary inductor in the forward topology

effective inductance seeing into primary winding of T in the forward topology

reflected inductance of Ls hto the primary side of Tr

number of tunis of the core resetting winding of Tr

nurnber of tums of the prirnary winding of Tr

number of t ums of the secondary winding of T'

reciprocal of the tums ratio of the power transformer, equal to NIN,

main switch power MOSFET

auxillary switch power MOSFET

clamp switch power MOSFET in the active clamp t~palogy

main switch power MOSFET in the active clamp topology

load resistor

on resistance of a power MOSFET

current sensor resistor

power switch

Laplace transformation variable

power transformer

switching cycle of the converter

instantaneous drain-to-source voltage of Q l

instantaneous secondary voltage of Tr

xvii

drain-to-source voltage of Q I at the beginning of each switching cycle

input voltage of the DClDC converter

nominal output voltage

reference voltage

peak value of the secondary voltage of T,

peak-to-peak voltage of the saw-tooth signai in the PWM control unit

small signal deviation of the output voltage of CA in Laplace transformation

small signal deviation of F(> in Laplace transformation

small signal deviation of the voltage resulted fiom the sensed current in Laplace

transformation

small signal deviation of the output voltage of VA in Laplace transformation

xviii

1.1 POWER SUPPLIES FOR TELECOMMUNICATION AND

COlMPUTER SYSTEMS

In recent years, telecornmunication and cornputer systems have experienced fast

growth. These advanced systems require distributed power supplies. The principal

features of the supplies are constant operating frequency, high efficiency and high power

density. The power levels are usually ranged fi-om hundreds of watts down to thirty watts

or lower.

To meet the requirements of these applications, a nurnber of pulse width

modulation (PWM) MOSFET topologies are cornmonly used to implement the

distributed power supplies. These topologies include the full bridge, half bridge, push-

pull, double switch forward, single switch fonvard and flyback topologies, which are

listed in the sequence fiom high power level down to low power level. Each topology has

unique properties which makes it best suited for a certain power level-

This thesis limits the discussion within applications with power level below 150

watts, where the single switch MOSFET forward and flyback topologies are best suited.

1.2 FLYBACK AND FORWARD TOPOLOGIES

Figs. 1.1 and 1.2 show the standard topologies of the single switch MOSFET

flyback and fornard converters, which are best suited for applications at power level

below 150 W and dc line voltages below 200 V. Their operating principles are briefed

below. Each topology has advantages and drawbacks, which are compared in Table 1.1.

The transformer of the flyback is operated in the indirect power transfer mode.

"men the switch is nimed on, a nsing current flows through the primary winding (an

inductor), thus an amount of energy is stored in the core of the transformer. When the

switch is turned off, the dotted end of the secondary winding (another inductor) reverses

the voltage polarity. Thus, the rectifier diode is forward biased and the stored energy is

transferred to the output via the secondary winding and the rectifier. Periodical switching

of the switch will keep the power continuously flowing h m the input to the output. By

modulating the pulse width of each switching signal, the output voltage is regulated.

R e c t i f i e r -..

T r a n s f o r m e r

8 Fig. 1.1 A flyback converter topology.

The transformer of the forward is operated in the direct power transfer mode.

When the switch is turned on, an amount of energy is transferred to the output via the

transformer and the rectifier. When the switch is -ed off, the core of the transformer is

reset by a tertiary winding. Penodical switching of the switch will keep the power

flowing from the input to the output. By moduiating the pulse width of each switchùig

signal, the output voltage is regdateci.

o a d

Table 1.1 Cornparison between the two topologies based on the same power level

Advantages

Disadvantages

Applications

The flyback topology The forward topology

1, Simpler circuitry: no output inductor, only one rectification diode in the output stage,

2. Simpler transformer structure, 3. Better regulating of slave outputs

against t h e load variations in multi-outputs appIications.

1. Higher RMS and peak currents, 2. Larger ripples in the output

voltage, 3. Bigger output capacitor needed.

and operating frequencv

-

1. Low output current, 2. Relatively lower power level, 3. Multiple outputs.

1. Less ms and peak currents,

2. Less nppk in the output voltage,

3. Smaller output capacitor needed.

1. Output inductor and two more diodes are needed,

2. One more set of winding of the power transformer is needed to reset the core,

3. Poor regulation of slave outputs against the Ioad variations.

1. High output current, 2. Relatively higher power level, 3. Better for single output.

1.3 PROBLEMS WITH THE STANDARD TOPOLOGIES AND

SOLUTIONS

Unfortunately, the standard flyback and forward topologies are operated with hard

switching, that is, there are significant overlaps between the switch current and voltage

during the tum-on and tuni-off transients. These overlaps causes the so cdled switching

Iosses. Thus, it is difficult to achieve high power density and high efficiency with the

standard topologies.

In order to achieve high power densities, the power supplies are operated at

increasingly higher fiequencies. However, when the switching fiequency increases, the

losses associated with the tum-on and nim-off of the power switching devices in the hard

switching MOSFET converters also increase. These losses are so significant that

operation of the converters above 50 H z is prohibitive, because of the low conversion

efficiency and high cooling requirements.

Over the years, the resistor-capacitor-diode snubber (RCD) has been employed to

reduce the turn-off voltage stress and switching losses in the switches of converters.

However, the power removed fiom the switching losses due to RCD dissipates

completely in RCD itself. Thus, RCD has no contributions to achieve high efficiency nor

to reduce the size of the cooling devices. Hence, RCD is not an solution to the

applications concemed herein.

Normally, the solution is to employ the soft switching techniques. There are two

types of soft switching techniques, namely zero voltage switchùig (ZVS) and zero current

switching (ZCS). Both can eliminate or greatly reduce the switching losses. But it has

been shown in [l] that ZVS is a better scheme than ZCS in the MOSFET converter

topologies. Owing to this reason, a lot of work has been done to develop ZVS

flybacWforward topologies.

1.4 REVIEW OF EXISTING ZVS FLYBACK/F'ORWARD

TOPOLOGIES

Several ZVS flyback /fornard converter topologies have been proposed, including

the active clamp converters [2-131, the "mirror-stnictured" converters [14], and the non-

dissipative snubber [15-171. Although ZVS is achieved in these converter topologies9

they have at least one of the following drawbacks: complicated control schemes,

increased conduction losses, loss of ZVS under the light load conditions, under utilization

of power transformer, and restrictions on use due to patents.

1.4.1 Active Clamp Topology

Fig. 1.3 shows an active clamp forward converter topology, where a clamp circuit

consisting of a switch and a capacitor is added to the standard forward circuit. With the

clamp circuit, ZVS is achieved in the main switch. The clamp circuit of Fig. 1.3 can also

be employed in the flyback topology, forming an active clamp flyback converter.

The drawbacks of these topologies include:

C apacitor M ain sw itch

Fig. 1.3 An active clamp forward converter topology.

(i) They need an isolated, variable d u t - cycle gate drive for the clamp switch,

(ii) They require a modified PWM control technique to properly program the associated

delays between gate drives of the main and clamp switches, so as to achieve ZVS,

(iii) ZVS is lost under light load conditions.

(iv) ZVS is achieved at the cost of increased conduction losses,

(v) The current mode control c m not be used,

(vi) The patent related legai issues make it difficult to use, because it is a patented

technique.

1.4.2 'Mirrored structure' Topology

Fig. 1.4 shows a ZVS flyback converter topology which has a mirrored structure

on both sides of the power transformer [14], where a MOSFET switch replaces the

rectifier diode of the standard flyback circuit. Other topologies like the fornard can be

converted into a ZVS operation in the same manner.

o a d Y'"

Fig. 1.4 The 'mirrored-structure' ZVS flyback converter.

I n p u t i O u t p u t - c a p a c i t o r

L &

The mirrored structure circuit employs fewer components than the active clamp

converter. As the output voltage is usually low (<24 V) for the telecornmunication and

cornputer systems applications, a low voltage rating MOSFET can be selected for the

ZVS switch. The drawbacks of this topology include:

(i) It needs an isolated gate drive for the ZVS switch,

(ii) The utilization of the power transformer is poorer,

(iii) The conduction losses are increased:

(iv) Larger ripples are resulted on the output capacitor.

1.4.3 Passive Non-dissipative Snubber Flyback/Forward Topologies

Fig. 1.5 shows a fonvard converter topology employing a non-dissipative snubber

[15-171. Two diodes and a capacitor and an inductor foms the snubber. No additional

switch is required. This snubber can also be applied to a flyback converter topology.

The drawbacks of the non-dissipative snubber include: (i) The switch has a hard

switching at tum-on, and (ii) The topology is not suitable for applications when the input

voltage varies in a wide range.

Fig. 1.5 A forward converter with a non-dissipative snubber.

1.5 SCOPE AND CONTRIBUTIONS OF THIS THESIS

The objective of this thesis is to propose and analyze ZVS flyba ck and f o ~

topologies that can overcome the following drawbacks of the existing topologies:

(i) complicated gate drive schernes.

(ii) loss of ZVS under light load,

(iii) no ability to employ current mode control,

(iv) increase in conduction losses,

and to compare performance of the proposed topologies with that of the standard

(conventional hard switching) fl yback and fonvard converters.

The scope of this thesis is lirnited to the steady state analyses, smdl signal

analyses, experimental verifications. and design of the proposed topologies for

applications at the power level below 150 W, switching fiequency between 200 kHz and

300 kHz, dc line voltage below 200V. Average current mode control is selected as the

control scheme.

The principle contributions of this thesis are as follows:

(i) ZVS flyback and forward converter topologies are proposed and analyzed. It is shown

that the proposed topologies have several advantages over the existing ZVS and

conventional flyback and forward topologies, including no increase in conduction losses,

simplicity in both power and control circuitry, lossless switching independent of lineAoad

conditions.

(ii) Prototype flyback and forward converters of the proposed topologies are built, which

are operated at 200 kHz and powering 50 W, and at 300 kHz and powering lOOW,

respectively. Expenmentd verifications of the theoretical analyses are performed with

these prototypes. Cornparisons of efficiencies between the proposed converters and the

conventional hard switching converters are made, which show that the proposed

converters have about 5% to 7% higher efficiency.

(iii) The design procedures for the proposed converter topologies are presented.

The contents of each chapter in this thesis are sumrnarized below.

In Chapter 2, a ZVS flyback converter topology is presented. The principles of

operation are illustrated and modes of operation are detailed. The steady state operation in

each mode is analyzed. Parameters evaluating the steady state performance of the

converter are denved. Experimental results of the prototype fiyback converter are

presented and are compared with the theoretical predictions.

In Chapter 3, a ZVS forward converter topology is presented. The principle of

operation is illustrated and modes of operation are detailed. The steady state operation in

each mode is analyzed. Some parameters evaluating the steady state performance of the

converter are derived. Experimental results of the prototype forward converter are

presented and are compared with the theoretical predictions.

In Chapter 4, small signal models are discussed, based on the average current

mode control. The flyback converter can utilize the same srnall signal model as a

conventional flyback converter. The small signal model of the fonvard converter is

derived. The compensation for both the current and voltage loops is discussed and the

small signal analysis of the fonvard converter is verified experimentally.

In Chapter 5, design procedures are presented. Design examples are given for both

the flyback and forward topologies. A simple implementation of generating of the gating

drive signals for the auxiliary switch is presented.

In Chapter 6, research and development in the thesis are summarized. Advantages

and disadvantages of the proposed topologies are discussed. Suggestions for future work

are made.

A ZVS FLYBACK CONVERTER TOPOLOGY

2.1 INTRODUCTION

Among the conventional dcldc converters. the flyback topology employs the

fewest power components and devices. It is best suited for multiple output applications at

total power levels below 150 W and dc line voltages above 100 V. However, as

mentioned previously, the standard flyback is unable to meet the requirements for high

power density and high efficiency. and the existing ZVS flyback converters have several

previously rnentioned drawbacks. Research for better solutions is hence required.

This chapter presents a ZVS flyback converter topology which is able to

overcome some of the drawbacks of the existing topologies. The topology employs an

auxiliary circuit that helps to achieve ZVS in the main switch, with addition of only a few

nurnber of small power rating components and devices.

The converter operates in the discontinuous mode. The continuous mode

operation is not recommended here since it is not easy to stabilize the converter. A steady

state analysis of the converter is presented in this chapter to understand the behavior and

to develop performance characteristics.

The circuit description is made in Section 2.2. The modes of operation are

detailed in Section 2.3. The steady state analysis is pe r fmed in Section 2.4.

Performance is discussed in Section 2.5 and experimental venfications are made in

Section 2.6.

2.2 CIRCUIT DESCRTPTION

Fig. 2.1 shows a ZVS flyback converter topology employing an auxiliary circuit

drawn inside the dashed line block. Outside the bIock is a standard flyback topology

shown in Fig. 1.1.

In Fig. 2.1, Citr is the input capacitor, T is the power transformer with windings Np

(pnmary) and N,. (secondary), L,,, is the rnagnetizing inductance of T , Do is the output

rectifier diode, Co is the output capacitor, R,, is the load and QI is the main switch.

The auxiliary circuit consists of (i) a snubber capacitor CStrb, whkh is connected in

parallel with the main switch QI, (ii) two coupled inductors L, (primary) and L,

(secondary), (iii) two blocking diodes D, and D2, and (iv) an auxiliary switch Q2.

2.3 MODES OF OPERATION

Fig. 2.2 shows key wavefoxms of the proposed converter. For each switching

cycle, T,, the converter operates in the following five intervals. In the operation of a

standard flyback, there are no Intervals 1 and 3. These two intervals are fulfilled by the

auxiliary circuit and are introduced here to achieve ZVS in the main switch, QI, during

both its turn-on and turn-off transients.

2.3.1 Interval 1 ( t , < t tJ

Fig. 2.3(a) shows the circuit operation during this interval. At the beginning of

this interval, 0 2 is turned ON. It has a zero current tum-on, because L, is in series with

it. Its drain-to-source voltage falls rapidly to zero. and a resonant loop consisting of C,,

La,, and L,, as s h o w in Fig. 2.4, is formed. C,,, starts to discharge through Lap. The

discharging current builds up a magnetic field in the core of the coupled inductors,

transfemng the stored energy in C,,,l, in the previous cycle to the core of L,,.

intervals

Main switch

Auxiliary switch

O

Main s w itch voltage and

curren

A uxiliar). sw itch voltage and

currefl

O

Transforrn e secodary curren

O

Coupled inducto sencondary O

c u m n

- . I

+ I I 0 I I I

, . 8 , 1 I I I

: t 0 , I I

4 , I I * , a I , I

4 ta r; ta l; ~ ' + T s t im e

Fig. 2.2 Key waveforms of the converter of Fig. 2.1. The converter operates in five modes per switching cycle. Variables are defined in Fig. 2.1

At the end of this interval, t = t,, - C,,,, is depleted. As a consequence, the drain of

Q l is pulled d o m to zero voltage: providing the ZVS condition for Ql at its tum-on.

During this interval, Co supplies the output current.

2.3.2 Interval2 (t, < t 5 4)

Fig. 2.3@) shows the circuit operation during this interval. At the beginning of

this interval, Ql is tumed ON under the zero voltage condition. Hence it has no tum-on

losses. At the same moment, Q2 is nimed OFF, stopping the current in Lw rapidly. The

* (a) Interval 1 (t,<lst2)

* (b) Interval 2 ( t p s t , )

t4 (d) Interval 4 (t,<tQ,)

O

(e) Interval 5 (t,<t<T,+i,) Fig. 2.3 Modes of operation of the converter of Fig. 2.1. The operation is divided

into five modes per switching cycle. The key waveforms are shown in Fig. 2.2.

Fig. 2.4 The equivalent circuit of the discharging resonant loop in Intervai 1. Variables are defined in Fig. 2.1.

rapidly falling current in L, reverses the voltage polarity on the dotted ends of the

coupled inductors. Thus D, becomes forward biased and is forced to conduct.

When D, is conducting, Lm sees a constant voltage y,,. Through coupling, L, sees

a reflected voltage. This voltage is the stress voltage on Q2. By increasing the ratio of L,

to L,, the stress will be lower. This in h m reduces the turnoff switching losses in Q2. On

the other hand, the current in Lar is decreasing linearly. In this way the stored energy in

the core of the coupled inductors is gradually fed back into the input line. At r = t,, the

process completes and D, becomes reverse biased again.

When Ql is ON, the magnetizing inductor of T sees a constant voltage y,,. Thus,

the current in Ql nses linearly. In this way the energy is stored in the core of T in the

sarne fashion as in a standard flyback converter. During this interval, Co supplies the

output current.

2.3.3 Interval 3 (t, < t r t,)

Fig. 2.3(c) shows the circuit operation during this interval. At the beginning of

this interval, Ql is turned OFF. C,, is in the process of charging and it slows down the

rise of the drain voltage of Q l . A sufficient value of capacitance of C,, will guarantee a

ZVS tunioff. The current in the primary side is decreasing in a resonant mode, with an

angular fiequency determined by L,,, and Cm*. The decreasing of the primary current

reverses the polarity on the dotted ends of T' But before the voltage of the secondary side

of T, reaches the output voltage y,' D,, maintains reverse biased. Co supplies the output

current during this interval.

2.3.4 Interval4 (t, < t s ta

Fig. 2.3(d) shows the circuit operation during this interval. At the beginnuig of

this interval, the voltage of the secondary side reaches V'- Then Do is forward biased and

begins to conduct. The secondary current refills Co, and also supplies the output current.

In this way the stored energy in T is now transferred to the output.

The conduction of D, causes N,. to see a constant voltage Vo. This in turn clamps

the voltages on both primary and secondary windings, and consequently, it clamps the

voltage across the main switch QI.

2.3.5 Interval 5 (t, < t s t,+TJ

Fig. 2.3(e) shows the circuit operation during this interval. At the beguuiing of

this interval, the stored energy in T is completely transferred to the load. Then Do is

reversed biased again and C, supplies al1 the output current. The dif5erence between the

drain voltage of Q I and the dc line voltage y.,) causes a resonance in the network

consisting of L,,, and C,,.

At the end of Interval 5, a new cycle begins and Intervals 1 through 5 repeat.

2.4 STEADY STATE ANALYSIS

The operating principle has been described in last section. In this section the

steady state analysis is performed with the assumptions made below. In the andysis, the

time varying variables such as the cwent and voltage of the principal components and

devices are detemiined. Based on these variables, the performance of the converter is

illustrated, and the resultant quantities such as the rms, average or peak c w e n t and

voltage of the principal components and devices are obtained in Section 2.5. These

quantities are used in designing the converter as presented in Chapter 5.

In the analysis presented below, a closed form solution is obtained by solving a

set of differential equations in each interval and by matching the boundary conditions at

the boundary of each interval. The initial conditions are a fûnction of the operating

kequencyf;, the input dc line voltage y,, and the output power P,,. These initial conditions

can be obtained by the iterative process such as the Newton-Raphson method.

2.4.1 Assurnptions, Definitions and Initial Conditions

For convenience, following assumptions are made:

(i) The steady state conditions have be established. and the converter is running at the

nominal output voltage Vo and the static load condition: Po,

(ii) Each component and device has ideal properties, that is

(1) T,: the leakage inductance is ipnored, and the core does not saturate,

(2) L,, L,: the coupling factor is 1 .O, and the core does not saturate,

(3) Co, Cd: pure capacitors, and the capacitance of Co is infmitive,

(4) Dl, D2, Do: the fonvard voltage drop is O V, the recovery time is O s,

(5) Q I , 02 : the on resistances are O Cl, the inherent capacitances are O F.

The effects of the non-ided properties of the components and devices are investigated in

Section 2.5.1.

(iii) The magnetizing inductance of the transformer, Ln,, is much larger than L,.

Following parameters are defmed:

a,,--angular fiequency of the resonant tank of C,), and L,,

a,--angular frequency of the resonant tank of C,, and L, ,

--instantaneous current in Q2, I ~ P

Iap--peak current in Q2,

i,-4nstantaneous current in La-$,

1,--peak current in L,,

I,,l,,---peak magnetizing current in T,

i,,--instantaneous current in Q I ,

i.5--instantaneous secondary current,

1,--peak secondary current.

n--reciprocal of t u m s ratio of Troor NJV,,.

uQ,-4nstantaneous drain voltage of Ql? or voltage across C,,,,

um-4nstantaneous drain voltage of QI,

V,--initial drain voltage of Ql per switching cycle,

Vp-Q,--clamped voltage stress of Ql when it is OFF.

The analysis begins by stating the initial conditions of Interval 1 :

(i) Ql and Q2 are both OFF, and the drain voltage of the paralleled switches is V,,

u&,) = uO2(tJ = VO (2- 1

('1 ) = ) = 0 (2-2)

(ii) The magnetizing inductor Ln, and Cd undergoes a resonance, but the resonant cunent

in L, is negligible,

',,,(tJ = 0 (2-3)

(iii) Both D, and Do are reverse biased, and Co supplies the total output curent,

i&) = i&) = O (2-4)

2.4.2 Intewai 1 (t, -= t 5 t,) This interval starts at t = t,. QZ is nimed on and C.,, and LtIl foms a resonant tank

as s h o w in Fig. 2.4. Hence the following equations govem the resonant process in this

tank.

Combining Eqs. (2-5) through (2-7),

According to the assumption (iii), L,<<Ln,. Hence, Eq. (2-8) can be approximated as,

By the definition made above,

Giving the initial conditions expressed in Eqs. (2-1) through (2-4), Eqs. (2-9) and (2-6)

yield, respectively

u,, ( 0 = K, co$q,(t - t , ) ] (2-1 1)

iap(t) = ~ J w ' s i # ~ , , ( t - r l ) ] (2- 12)

Because D, and Do are reverse biased and Ql is OFF and Q2 is ON, the following

equations are fourid to govem the respective variables in this interval.

Lm = i.&) = iQ, (0 = (0 = 0 (2- 1 3)

= 0 (2- 1 4)

At the end of this interval, the resonance completes a quarter of its period, Le., o,(t, - 1,)

equals r/2. Thus- uQ, always reaches zero regardlesç of V, which is determined by f;. y,,

and Po,

and i, reaches the peak value given by

The final value of each variable in Interval 1 defines the initial conditions of Interval 2.

2.4.3 Intemai 2 (t, < t 4)

This interval starts at t = 1,. 0 2 is turned OFF and i, falls immediately to zero. A

current is forced to flow through L, and D, - and into the input dc line, with an initiai

current 1, determined by the energy conservative equation,

which yields

Substituting Eq.(2- 16) into (2- 1 8),

L, sees a constant voltage y,,. As Ql is ON, Lllt also sees a constant voltage y,,. Thus,

As Ql is ON and Q2 is OFF and Do is reverse biased. therefore

i., ( t ) = iU" ( t ) = O

At t = t,, i, reaches zero. Thus, by letting ia, be zero

Hence the voltage stress on Q-2 is govemed by

(2-23)

in Eqs. (ZZO), ta c m be found,

At the end of this interval, t = t,, iQ, reaches its peak value, as given by

where, f; is the switchuig frequency, and

D is the switching duty cycle of Q l , which is required to regulate the output

voltage at the static load conditions (discussed in Section 2.5.2) and is here equal

to (t3-t2)/T'.

The final value of each variable in Interval 2 defines the initial conditions of Interval 3.

2.4.4 Interval3 (t, < t 5 t,)

This interval starts at t = t,. Q2 is tumed OFF and C,.,l, is charged by in#. Refehg

to Fig. 2.4, the drain voltage of Ql in this interval satisfies the following equation

Giving the initial conditions determined by Eqs. (2-21) and (2-23): the solution of Eq. (2-

27) c m be obtained as

where, by the definition made previously.

As both Ql and Q2 are OFF and 4 is reverse biased, other variables in this

interval are found to be govemed by the following equations, respectively,

ici ( t ) = i&) = isz( t) = i J t ) = O (2-3 O)

Investigating the rising speed of uQ, by differentiating Eq. (2-28) and substituting

Eq. (2-29) into the result:

Eq. (2-31) reveals that the nsing speed of II,, is controlled by C,,. Giving the proper

value of C,, will suffikiently slow down the rise of uQ, and hence achieve ZVS in Q I at

the turn-O ff transient .

The magnetizing current is given by

At the end of this interval, t = t,. u,, reaches the clarnped voltage as given by

Thus, the duration of this interval cm be determined by substituthg Eq. (2-33) into (2-

28) and solving the resultant equation for (r,-t,). The final value of each variable in

Interval 3 defines the initial conditions of Intervd 4.

This interval starts at f = t,. 4, is fonvard biased and a current flows through N,.

and Do into the output end. As Nv has a inductance equal to n2Ln,, the initial value of the

secondary current, tP, can be obtained from the energy conservative equation,

which gives

Ns sees a constant voltage Va- therefore

Y, is (t ) = Isp - ( t - t4 ) (2-3 6 )

n- 4,

As Ql and Q2 are OFF and uQ, is clamped, thus, the following equations are obtained

ur,i ('1 = V p - y (2-3 7)

Because the converter is operated in the discontinuous conduction mode, the

secondary current i, will reach zero within one switching cycle. Thus, the relation

between the peak value of the secondary current and the output power Po is found to be

Hence, at the end of this interval. t = t,.

where, D'is the equivalent duty cycle of rectifier D,, and is equal to (t5-i4X.

The duration of this interval can be determined by combining Eqs. (2-39) and (2-40) and

solving the resultant equation for DI The final value of each variable in Interval 4

defines the initial conditions of Interval 5.

2.4.6 Intewal5 ( t5<t 5 Ts+ t , )

This interval starts at i = t,. 4 is reverse biased again. Ql and Q2 are OFF. C,,

and Lm undergo a resonance and this resonance obeys Eq. (2-27). Giving the initial

conditions as determined by last interval, and solving the equation for un,,

As Do and D, are reverse biased and Ql and QZ are OFF, thus,

is(t) = iQ1 (t) = iaq ( t ) = iap ( t ) = O

At the end of this interval, t = Tr+tl, uQ, reaches a voltage V,, which is the steady

state initial voltage of Interval 1 of each cycle. From Eq. (2-41), it is found that

1 Vfi = uQl(T + r l ) = y,, +-Y, cos[ao(T, + f l -QI (2-44)

n

Since LJtt is much larger than Lw, by comparing Eqs (2-42) to (2-12), in, is negligible and

hence ignored in the analysis of Interval 1 that is.

~J~ +f i ) * 0 (2-45)

The final value of each variable in Interval 5 defines the initial conditions of Interval 1 in

the next switching cycle' which just repeats the same process as analyzed above..

2.5 PERFORMANCE

2.5.1 Effects of the Non-Ideal Cornponents

The above analysis has been made mder the assunlptions of ideal components and

devices. In fact, each component and device of the circuit has some non-ideal properties.

For example, the leakage of the transformer, the ON resistance and the inherent

capacitance of switches, and so on. It is important to determine whether they make a

remarkable deviation.

It can be explained as follows. The ON resistance of switch causes the so called

conduction losses. The inherent capacitors indeed have some effects on the performance

of the switch. But the output capacitor of the switches c m be combined with Cd, and the

effects of input capacitor of the switches c m be made negligible by employing strong

gate drives. The blocking diodes in Fig. 2.1 can be chosen as neariy ideal ones, like the

Schottky diode or the ultra-fast diode. However. the effect of the Ieakage inductances of

the circuit are detectable on key wavefoms.

The effects of the leakage inductance of the transformer become apparent in

Interval 4. It is because in other intervals they c m be combined with magnetizing

inductance L,!,. However, in Interval 4, the flux linked inductance (L,) is clarnped at a

constant voltage ( V h ) , but the leakage inductance is not affected by t h i s clamp action.

The leakage, called Lkak in the following discussion, undergoes a resonance govemed by

where uQ, ,, is the voltage component of z iQI caused by the leakage, and

R, is the equivalent series resistance of the resonant loop.

The initial conditions of Eq. (2-46) are given by Eqs. (2-21) and (2-23). T'us, the

solution of Eq. (2-46) is

where,

Superimposing uQ, - ,(t) ont0 uQ, will give the total voltage of C,,.

Similarly, the leakage of L, and the inherent drain-to-source capacitor of Q2

undergo another resonance between the tumoff of Q2 and ta, as given by

where L is the leakage of L,,

Cm-, is the inherent capacitance of QZ,

a, ,, is given by

h is given by

where Ra , is the equivalent series resistance of the resonant tank.

Hence, superirnposing tiQ2-leak(t) ont0 uQ2 will give the total drain voltage of Q2.

2.5.2 Determination of Duty Cycle for the Output Regulation

Combining Eqs. (2-39) and (2-40),

Combining Eqs. (2-26), (2-33), (2-34). (2-40) and (2-53), the duty cycle required at the

input and Ioad conditions is found to be

When Po is so large that the second tenn in the bracket of right side of Eq. (2-54) is

negligible, Eq. (2-54) c m be approximated as

~ ~ ~ $ n x (2-5 5 ) K I

Then, substituting Eq. (2-55) into (2-54), and ignoring the second term, yield

n P:,, D = y, D' (2-56)

2.5.3 Advantages and Disadvantages of the Proposed Converter

The following major advantages of the proposed converter can be identified.

(i) No need of an isolated gate drive for the auxiliary switch, because Q2 and Ql

have common source connection as s h o w in Fig. 2.1.

(ii) Generating of the gate drive signals is simple, because the on time of Q2, unlike

in the case of the active clamp topology. is fixed at a quarter of the resonance penod of

the &,-Cs,, tank.

(iii) The ZVS conditions, provided by Intervals 1 and 3, are not affected by the line

and load conditions (refer to Eqs. (2-1 5) and (2-3 1)). Hence ZVS c m always be achieved

regardless of the linenoad conditions.

(iv) Less EMI is generated. Substituting Eq. (2-3 1) into (2-32) and differentiating the

equation with respect to time,

The fxst term in the bracket on the right hand of Eq. (2-57) principally govems the fdling

current in Ln,. It indicates clearly that the snubber capacitor C,, slows down the falling

speed of the current, and hence lowenng the EMI generated.

(v) Simple in circuitry, and al1 components of the auxiliary circuit require small

power ratings, since they only handle the stored energy in Cd,.

(vi) Conduction losses are not increased. Unlike in the active clamp topology, where

extra circulating power is required to flow in and out of the clamp capacitor, the proposed

topology does not involves the extra circulating power. Hence the conduction losses are

not increased.

The disadvantage of the proposed topology is that the auxiliary switch has a hard

switching turn-off. But the switching losses in Q2 can be reduced to a very low level by

selecting a MOSFET through trading off between the least ON resistance and the least

inherent capacitance, and also by increasing the ratio of L, to Lw, which lowers the

voltage stress on 0 2 at turn-off as given by Eq. (2-25).

2.5.4 RMS, Average, Peak Current and Voltage Values

In the design, the rms, average or peak current and voltage are required to

detemine the rating requirements in selecting the components. Some of these values have

been obtained in the analysis. Other values are calculated below.

(1) Rms current in Q I

The current in Ql has a triangle waveform. Hence the ms current is

Substiîuting Eqs. (2-26) and (2-54) into (2-58),

Correcting Eq. (2-59) for a conversion efficiency less than 1, Say ~l, the r r 113 - current

becomes

(2) Rms current in 0 2

The current in Q2 is one quarter of a sine wave, as given by Eq. (2-12). Hence. it

is found that

The average current is found to be

(3) Average current in D2

The current in D2 is ûiangular. From Eqs. (2-19) and (2-24), it is found that the

average current in D, is given by

1 t - t lm.-D2 = -In$ - =

2

(4) Average current in Df,

The current in Do is triangular. From Eqs. (2-39) and (2-40), the average current in

Do is given by

2.5.5 Losses Caused by the Auxiliary Circuit

(1) Switching losses in Q2: P.,. ,, It is estimated that

where C ( , s2 is the output capacitance of 02' and

[off -2 is the OFF transient time of 02.

(2) Conduction losses in @: P,.

The losses are found to be

P C - - ~ ~ = I;L~.Y-~)~ RD---

where RDQl is the ON resistance of Q2.

(3) Conduction losses in D, and D,: P,. .,,, The conduction losses in Dl and D, are found to be

Ir,, is the fonvard voltage drop of D,.

(4) Total losses by the auxiliary circuit

PI-0 = P r - x + P C . - ~ Z + Pc-DI&?

2.5.6 Losses Removed by ZVS Operation

(1) Switching losses in QI in a hard switching operation: Ps

The hard switching will cause switching losses in Ql as estimated by

where tOfl is the OFF transient time of QI, and

Cos, ,, is the output capacitance of QI.

(2) Net saving of power due to ZVS operation

The net saving of the power due to the ZVS operation of the proposed converter is

approximately

AP = P,-A - L e z (2-70)

2.6 EXPERIMENTAL RESULTS

2.6.1 Experiment Setup

A prototype ZVS flyback converter is built based on the design presented in

Chapter 5. The circuit operates under an input dc line varying fiom 90 V to 160 V. The dc

line voltage is obtained directly from a diode bridge rectiQing an ac line voltage in a

range of 75 V to 135 V. UC3855 is used as the PWM control chip. The schematic of the

circuit is shown in Fig. II. 1 in Appendix II.

The operating conditions of the circuit are surnmarized as follows: (i) the dc line

voltage range is 90 V to 160V (corresponding to a dc line voltage range 75 V to 135 V),

(ii) the full load is 50 W, with two outputs, of which the master output is 10 W at 5 V and

the slave output is 40 W at 20V, and (iii) the switching frequency is 200 kHz.

2.6.2 Key Waveforms

Fig. 2.5 shows the theoretical wavefoms of II,, and in,, which are drawn in

MathCAD based on the equations which are found to govem ilp, and i,, in the analysis

presented in the previous sections. Fig. 2.6 shows the experimental results of the drain

voltage and current of Q I in the prototype converter. Cornparison between the theoretical

and experimental results are made in Table 2.1. It is seen that they are in good agreement.

l L I voltage ;\. ,9., - l t

i \ : : ,?., ,n 1 ! \, ; 1. : ;,J L j i i ;

\ current ; I ldf I

Fig. 2.5 Theoretical results: the drain voltage and current waveforms of Ql in Fig. 2.1, which are predicted by the steady sate analyses made in Section 2.4 and 2.5. The negative

drain current is due to the latching of the body diode of Q1 before it is turned on. Operating conditions: V,,,=13OV, Pn=50 W.f;=2001cHz

Fig. 2.6 The experimental results: the drain voltage and current wavefoms of Ql in the prototype ZVS converter of Fig. 2.1. The theoretical waveforms are shown in Fig. 2.5.

Scales: vertical--5OV/div., 1 Mdiv.; horizontal-0.5ps/div. Operating conditions: yl,=l 3 OV, P0=50W, f;=200kHz

Table 2.1 Cornparison between the theoretical and experimental results of the current, voltage and duty cycle of the main switch.

I 1 I I I I I 1 I

-

current - scales: -

-

Fig. 2.7 The drain voltage and current waveforms of Q2 in Fig. 2.1, which are predicted by the steady sate analyses in Sections 2.4 and 2.5.

Operating conditions: V,= 13 OV, <=50WYf;=200kHz

(V,,,=l30V, P,=5O W,1;=200kHz)

vg8 1 &d

210V 3.16A 220V 1 3.22A

Vpmk

273V 280V

Theoretical Experimental

D 0.23 0.22

Fig. 2.7 shows the theoretical wavefoms of u, and i,, which are drawn in

MathCAD based on the equations which are fomd to govem up and i , in the analysis

presented in the previous sections.

Fig. 2.8 shows the experimental results of the drain voltage and current of Q2 in

the prototype converter. Comparison between the theoreticai and experimental results are

made in Table 2.2. It is seen that they are in good agreement.

Fig. 2.8 The experimental results of the drain voltage and current wavefoms of Q2 in the prototype ZVS converter of Fig. 2.1. The theoretical waveforms are shown in Fig. 2.7.

Scales: verticaMOV/div. 1 Ndiv.; horizontal-0.5ps/div. Operating conditions: y,1=130V, <,=5O W,j;=200kHz

Table 2.2 Comparison between the theoretical and experimental results of the current, voltage and duty cycle of the auxiliary switch.

(ytI=1 30V, Pl,=50 W,f;=200kHz)

Theoretical Vo!

47.3V D

0.23 I,,k

2.69A ta-t2

1 . 6 9 ~

Figs. 2.9 and 2.10 show the experirnental key waveforms of the main switch Ql

and the auxiliary switch Q2, respectively, under light load condition. It is seen that ZVS

is not lost at light load.

Fig. 2.9 Experimental results: the current and voltage waveforms of the main switch QI in ZVS operation under light load condition:

V II 1 =120V, P,,=l OW' f;=ZOOkHz. Scales: vertical-50Vidiv. 1 Ndiv.; horizontal-OSps/div.

Fig. 2.10 The current and voltage waveforms of the auxiliary switch Q2 under light load condition: y,,= 120V, Po=I O W, f;=200kHz.

Scales: verticaL50V/div. 1 A/div.; horizontd-O.Sps/div.

2.6.3 Effïciency

Experimental resdts of the efficiency from the prototype converter are obtained.

The input dc voltage is obtained fiom a diode bridge rectifier which rectifies the ac line

voltage varying between 75 V to 135 V (ac). For convenience, the experimental results of

efficiency inciude the effect of this input rectifier stage.

I Li - - -'C -

ZVS Flyback convener efficiency

8 . - O 66- conventiona1 Flyback converter

58 ' input ac voltage (V)

56 75 85 95 105 115 125 135

Fig. 2.11 The overall eficiency of the converter vs. input AC voltage (the range of AC voltage corresponds to a dc input voltage range of 90 to 160V).

The eff~ciency of hard switching operation of the converter is made in cornparison here. The output power is P0=50W, and f;=ZOOkHz.

A 75 t ZVS flyback converter

6 conventional flyback converter

I Output Power (W) 50 - b

10 20 30 40 50

Fig. 2.12 The overall efficiency vs. load under given input voltage for both the proposed and conventional circuits. The efficiency measured includes the efficiency of the input ac-to-dc bridge

rectifier stage. YI,= 1 20V, 1;=200kHz.

Fig. 2.1 L shows the efficiency of the converter vs. input voltage under the full

load condition (50W). The comparison behveen the efficiencies of the ZVS and the hard

switching flyback converters is also made in Fig. 2.1 1. The comparison shows that ZVS

indeed makes a remarkable increase in efficiency: an increase of about 7% is obtained.

Fig. 2.12 shows the overall efficiency of the converter vs. load under given input

voltage for both the proposed and conventional circuits. The proposed circuit always has

higher efficiency than the conventional hard switching flyback converter.

2.7 CONCLUSIONS

In this chapter a ZVS flyback converter topology has been presented and

analyzed. The steady state operation of the circuit can be divided into five distinct

intervals. The steady state analysis of the circuit is performed and verified

experimentally .

Analysis and experiments show that the performance of the proposed converter is

enhanced with the auxiliary circuit. 7% higher eficiency has been achieved on the

prototype circuit as compared with the conventional hard switching converter. Other

major merits of the proposed ZVS flyback topology include:

(i) Lossless switching of the main switch, independent of the line and load conditions,

(ii) Simple power and control circuitry,

(iii) No increase in conduction iosses.

(iv) Ability to operate in either voltage or current mode control.

Therefore, the proposed converter topology provides an attractive alternative to

the existing ZVS flyback topologies and it is prornising in wide applications in

telecommunication and cornputer systems in the f h r e .

A ZVS FORWARD CONVERTER TOPOLOGY

3.1 INTRODUCTION

The single switch fonvard converter topology is extremely popular in

telecommunication and distributed dc bus applications. This topology offers a cost

effective solution to fil1 the void created between the low power flyback topology and the

more complex high power bridge types. Operating in continuous inductor current mode,

the fonvard converter utilizes a much lower peak current than its flyback counterpart.

This is advantageous with low voltage inputs.

As reviewed in Chapter 1, the conventional forward is not able to achieve high

power density and high efficiency. and the existing ZVS forward converters have several

previously mentioned drawbacks. Better solutions should be searched for.

This chapter presents a ZVS fonvard converter topology employs a similar

auxiliary circuit to that in chapter 2, with a little modification. The auxiliary circuit helps

to achieve ZVS in the main switch of the converter.

The converter operates in continuous mode in order to reduce the peak current in

the switch. A steady state analysis of the converter is presented in this chapter to

understand the behavior and to develop performance charactenstics.

The organization of this chapter is as follows. In section 2.2, the circuit

description is presented. In Section 2.3, the modes of operation are detailed. In Section

2.4, the steady state analysis is performed. in Section 2.5 performance is discussed and in

Section 2.6 experimental verifications are made.

3.2 CIRCUIT DESCRIPTION

Fig. 3.1 shows a ZVS fonvard converter ropology employing the sirnilar auxiliary

circuit to that in Fig. 2.1, drawn in the dashed Iine block. A modification on the auxiliary

circuit is that there is an additional small inductor L , in series with the secondary winding.

The reason of this modification is revealed by the analysis in Section 3.4.2.

-

Fig. 3.1 The proposed ZVS fonvard converter topology.

In Fig. 3.1, the basic foward circuit is comprised of (i) the input capacitor Ci,,,

(ii) the power transform T, which has three windings, the primary Np the secondary N,,

and the tertiary N, that helps to reset the core, (iii) the main switch QI, (iv) the rectifier

Do, and the fieewheeling diode D,,?, (v) the output inductor Lo, (vi) the output capacitor

Co, (vii) the blocking diode Dr, and (viii) the load Ru.

n i e auxiliary circuit consists of (i) a snubber capacitor Cd, which is in parallel

with 01: - (ii) two coupled inductors L, and La, (iii) two blocking diodes D, and 4, (iv)

an auxiliary switch Q2, and (v) a srnall inductor L-,, which is inserted into the secondary

side of the power circuit.

3.3 MODES OF OPERATION

Fig. 3.2 shows key waveforms of the proposed converter of Fig. 3.1. The

operation of the circuit can be divided into the following seven intervals. In a standard

fonvard converter, there are no Intervals 1, 2 and 4. These intemals are fulfilled by the

auxiliary circuit in order to achieve ZVS in Q I .

3.3.1 Interval 1 ( tl < t t2 )

Fig. 3.3(a). At the beginning of this intervai, 0 2 is switched ON. Thus Cm,, LoP

and L, form a resonant tank, as show in Fig. 3.4. C,,, begins to discharge through Lw

and Q2. The discharging current rises resonantly and builds up a magnetic field in the

core of Lw. In this way the discharged energy fiom C,, is transferred to the core. The

voltage of Cd drops to zero within this interval.

3.3.2 Intewal2 ( t, < t t3 )

Fig. 3.3@). At the beginning of this interval, Ql is switched ON under the zero

voltage condition. At the sarne moment, QZ is switched OFF, which stops the current in

L, rapidly. The rapidly falling current reverses the voltage polanty at the dotted ends of

the coupled inductors. Thus, & becomes foward biased and is forced to conduct,

releasing the stored energy in the core of L.v.

Intervals: 7 1 3 3 4 5 6 7 1 3 -

Gating for main sw itch O N

O tj W T s w t7 l3 l 4 r6 t7 t

G ating for auxi- A I

O N

+ + 1

A L I Voltage and - - - -!

" t d Q , /

current o f 'Y I

/ m a h sw itc h 0 1 f

I I O b t

v O ltag current o f I

'Y m a h sw itc h 0 1 f I I

O b t 4 1

V oltage and current o f aux i - \

liary sw itc h - U @ l 1 / f

b f

Secondary 4 current

O b t Currentin

2nd coupied O . ta I +

inductor t 1 h t3 t4 t5 t 6 f7 f i + & l

tim e

Fig. 3.2 Key waveforms of the proposed converter of Fig. 3.1. The converter operates in seven modes each switching cycle. Variables are defined in Fig. 3.1

* (a) interval 1 (t,< t 5 t,)

( d ) Interval 4 (rd< r l r,)

O (e) Interval 5 (t,< t 5 1,)

v (f) Interval 6 (r,< t 5 t,)

(g) Interval 7 (t,< t 2 T,+tI)

Fig. 3.3 Modes of operation of the converter of Fig. 3.1. The operation is divided into seven modes per switching cycle. The key waveforms are shown in Fig. 3.2.

The curent in Ql reflects the secondary current, which nses slowly owing to the

existence of L.$. Both Dot and D,,, are conducting to give the total current in L,, with the

current in D,, nsing and that in 4, falling linearly.

Fig. 3.4 The equivalent circuit of the discharging process in Interval 1. Variables are defined in Fig. 3.1.

Fig. 3.5 The equivalent circuit of the charging process in Interval 5. The variables are defined in Fig. 3.1.

3.3.3 Intewal3 ( t 3 < t 5 t , )

Fig. 3.3(c). At the beginning of this interval. cment in D,, reaches the value of

the current in Lu, and current in D,, falls to zero. Power is delivered to the load in the

same rnanner as in the standard fonvard converter.

3.3.4 Intewal4 ( t4 < t 5 t5 )

Fig. 3.3(d). At the beginning of this interval, QI is switched OFF. The pnmary

cwent charges C,,,. With a sufficient value of capacitance, CIlb can satisfactonly slow

down the speed of nse of the drain voltage of Q l so as to facilitate a ZVS tumoff in Q I .

Starting at the beginning of this interval, the current in Do, decreases and Do, is

forced to conduct by L,. L, and C,, f o m s a resonant tank shown in Fig. 3.5. The current

in pl and that flowing into C.$), fa11 resonantly, and the drain voltage of Ql rises

resonantly. The current in Do, rises accordingly.

33.5 Interval 5 ( S < t < t6 )

Fig. 3.3(e) shows the circuit operation during this interval. At the beginning of

this interval? the drain of Ql reaches a voltage of 2V,,). 9 is forced to conduct. Thus, the

voltage of the primary winding of T is clamps to a voltage of - V_, and the drain voltage

of Ql is clamped to 2y,,. In this way the core of T is reset. During this interval, Ls sees a

clamped voltage and the current in D,,, falls linearly.

3.3.6 Intewai 6 ( t6 < t I, )

Fig. U(f ) shows the circuit operation during this interval. At the beginning of this

interval, the current in L,% exhaust, D,, is reverse biased and Do2 freewheels the total

inductor current in L,. The voltage clamp action lasts until the current in Dr fa11 to zero at

the end of this interval.

3.3.7 Interval 7 ( fi < t TS+tl )

Fig. 3.3(g) shows the circuit operation during this interval. At the beginning of

this interval, the clamp action stops. C,, and the magnetizing inductance Lm of T form a

resonant loop. The drain voltage of Ql starts to oscillate about the input dc line voltage

y,:,,, starting fiom 2y1:,,.

Following Interval 7, the process repeats fiom Intervals 1 through 7.

3.4 STEADY STATE ANALYSIS

The operating principle has been described in last section. In this section, the

steady state analysis is performed with the assumptions made below. Based on the

analysis, the tirne v q i n g variables such as the current and voltage of the principal

components and devices are detemined, the performance of the converter is illustrated,

and the resultant quantities such as the rms? average, or peak current and voltage of the

components/devices are obtained. These quantities are used in designing the converter as

presented in Chapter 5.

The analysis below uses a similar approach to that in analyzing the flyback

converter in Section 2.4. Similady. the initial conditions can be obtained by the

previously mentioned iterative process.

3.4.1 Assumptions, Definitions and Initial Conditions

For convenience, the following assumptions are made:

(i) The steady state conditions have been established, and the converter is ninning at the

nominal output voltage Va and the static load conditions: Po-

(ii) Each component and device has ideal properties, that is,

(1) T,: the leakage inductance is ignored. and the core does not saturate,

(2) Lw, L,: the coupling factor is 1.0' and the core does not saturate,

(3) Co, pure capacitors, and the capacitance of Cc, is infinitive,

(4) Lu: the inductance of L,, is infinitive,

( 5 ) Dz? Du,, D; the fonvard voltage drop is O V, the recovery time is O s,

(6) Q I , Q2: the on resistances are O R, the inherent capacitances are O F.

The effects of the non-ideal properties of the components and devices are investigated in

Section 2.5.1.

(iii) The magnetizing inductance of the transformer, Ln,, is much larger îhan L,.

The following parameters are defined:

on--angular frequency of the resonant tank of $,,,. L, and L,(Interval l),

a,--angular fiequency of the resonant tank of C.v,l, and L,,l(Inte~al 7),

a;-angular fiequency of the resonant tank of C,, and L,(Interval4),

' --instantaneous current in 02.

IV--peak current in QZ,

i_--instantaneous current in L,, . I_--peak current in Lm,

i_--instantaneous input current.

(,IP4ak--peak magnetizing current in TF'

Iboutput current,

i,,--instantaneous current in Q I ,

is---intantaneou secondary current,

I,peak secondary current.

k--factor by which V, deviates fiom y,,, LI--reflected value of L, seen from the primary side of T ,

L,-magnetizing inductance of Tr7

Li-effective inductance of paralleling LI and L,,,,

n--reciprocai of tums ratio of T , equal to NJN,,

V--output voltage,

V --clamped voltage stress of QI when it is OFF, P-Q 1

V P m --clamped OFF voltage of QZ when it is OFF,

u,,--instantaneous drain voltage of QI, or voltage across C,$,,,,

Vo--initial drain voltage of QI per switching cycle.

According to the definitions and basic circuit theory,

J 1 L,+L, a,, = -*

C,,, La,, LI-

The analysis begins by stating the initiai conditions of Interval 1 :

(i) Both QI and 0 2 are OFF, and the drain voltage of the paralleled switches Ql and Q2

is Y,,

where k is the factor by which V, deviates from Y i , and

$J~J = $&tJ = 0 (3 -7)

(ii) The magnetihg inductor L,,, and C,), undergoes a resonance in the end of last

switching cycle, but the resonant current in Lll1 is negiigible?

illI(tl) = 0 (3 -8)

(iii) D, , Do, and Dr are reverse biased. and D, , fieewheels the total output current,

i&J = i,(tl) = O (3-9)

3.4.2 Interval 1 ( t , < t 5 t2 )

This intenta1 starts at t = t , . 0 2 is turned on and a resonant tank shown in Fig. 3.4

is fomed. The resonance process obeys the foilowing equations:

4. L,. - + rrc,, = C.:il dt

Combining Eqs. (3- 10) through (3- 12):

Giving the initial conditions determined by Eqs. (3-6) through (3-8)' the solution of Eq.

(3-1 3) is

Eq. (3-14) indicates that, if L were absent fiom the circuit of Fig. 3.1, narnely L, = 0, uQ,

could never reach zero. Under this condition, no ZVS would be achieved, To soive this

problem, L, is hence introduced.

It can be extended fiom Eq. (3- 14) that, if there exists a relation

un, will always reach zero when the fxst

impossible to satisfy Eq. (3-15) over al1

half of the resonant process finishes. But it is

the operating range, because k is not a fixed

parameter and it is detemined by the line and load conditions. For simplicity in design,

let

L , = Lap (3-1 6)

and set the duration of this interval to be a half of the resonant period. Thus, if the

condition k > O is always valid. ir,,, - will always reach zero within this duration and is

automatically clamped at zero by latching in of the body diode of Ql in the rest of this

interval. It will be shown in Section 3.4.8 that this condition c m be reached by selecting a

large 4,-

Referring to Eqs. (3-1) and ( M ) , Eq. (3-16) can be satisfied by selecting the

value of Ls as given by

Thus, Eq. (3-14) c m be rewritten as

From Eqs. (3- I l ) , (3-IO), (3-18) and the initial conditions (3-7) and (3-8). the

following variables can be determined as

Y I 1 1 i ( ) ( t - t , ) + ( T + k ) - sin[co ,, ( t - t, )] (3-19) 2L, OJ. 4,,7

Refer to Fig. 3.4, the magnetizing and the secondary currents of the transformer c m be

detennined, respectively, by

illm = =' ~ll lw L I + Li

Since D, is reverse biased and Ql is OFF.

As explained previously, at the end of this interval.

Thus, the ZVS condition for turning on of Ql is established.

The final value of each variable in Interval 1 defines the initial conditions of

Interval 2. For convenience in the following analysis, let

1 LI,, ISI = i , ( tz) =-- C I 1 Ytl -(t2 --il) " -.-(f2 - t , ) L I + LOP 2Lap 2Lap

3-43 Interval2 (t, < t 2 t,)

This interval starts at t = t2. Sirnilady to Section 2.4.3, it can be determined that

From E q . (3-30), the duration when id., flows

t" - r2 =

is determined

During (ta-t,), uQ2 will be clamped at a voltage the same as given by Eq. (2-25).

As L-< sees a constant voltage n y,, the secondar). current rises linearly

As Ln[ sees a constant voltage YI[, thus,

Hence the primary current is

As Q2 is off and QI is on,

At the end of this interval, the secondary cment reaches the value of the output

current Io

i \ U 3 ) = Ir, (3 -3 7)

Hence, fkom Eqs. (3-32) and (2-37), the duration of this interval can be detennined as

4 f3 - t , = ( I o - I J - (3 -3 8)

Y I ,

If Io < I,,, which is a case under the light load conditions, Interval 2 will not exist. It is

because the secondary current has reached 4, in Interval 1. Thus, Do, is reverse biased and

the total output current flows through Q,,. Under such conditions, the operation directly

enters Interval 3 fiom Intenirai 1.

The final value of each variable in Interval 2 defmes the initial conditions of

Interval 3.

This interval starts at r = t,. In this interval, the operation of the circuit is the same

as the standard fonvard converter: LI,, sees a constant voltage y.,, i5 is cornmanded by L, to

be constant at Io, and the total input current flows through QI. Therefore, the following

equations govern the respective variables during this interval.

The fmal value of each variable in Interval 3 defines the initial conditions of

Interval 4. For convenience in the following analysis, let

I l I l 2 = ilIl ( t4 )

3.4.5 Intewal 4 (t4 < t -< t5)

This interval starts at r = r,. Q l is tumed OFF at the beginning of this interval. C.vllb

is charged and the equivalent circuit is shown in Fig. 3.5. Thus. uQ, is govemed by the

following differential equation,

Giving the initial conditions determined by Eqs. (3-41) and (3-43). it is found that

As L , sees a voltage (y,; uQ,) and L,. sees a voltage n(yjTus,), thus,

And the input current is

As both QI and Q2 are OFF.

iQ,(t) = i&) = O

At the end of this interval, uQ, reaches 2 yll, i.e.,

uc,(4) = 2 YI, (3-5 1)

Then L,,, sees a negative voltage -y,, and Dr becomes fonvard biased and starts to

conduct, clamping u,, at 2Tl1.

The final value of each variable in Interval 4 defines the initial conditions of

Interval 5 . For convenience in the following analysis. let

I,? = i&) (3 -52)

' n t 3 = iw ('5 ) (3 -53)

This interval starts at t = t,. The core of T is reset as Dr conducts. Ltll sees a

constant voltage - ij1, and L,, sees a constant voltage -n ytl. Thus,

As Dr conducts, the tertiary current which consists of and the r e f h e d secondary

current flows into the dc line,

~ / l t ~ o = - ~ / / / ( ~ l -ni.&)

As both QI and Q2 are OFF and uu, is clarnped, therefore

ici ( 1 ) = i&) = O

q,IW =

At the end of this interval, < reaches zero

qf,) = O (3 -59)

Thus, Do,becomes reverse biased again and D , freewheeis the total output current 1,. 0,

From Eqs. (3-55) and (3-59). the duration of this interval is determined by

The final value of each variable in Interval 5 defines the initial conditions of

Interval 6.

3.4.7 Interval 6 (r, -= t 2 t,)

This interval starts at r = r,. The resetting of the core continues. If the resetting

finishes in Interval 5, this interval will be skipped and the operation enters directly into

Interval 7 fiom Interva1 5.

As Ln, sees a constant voltage -yl, and u,, is still clarnped,

The tertiary current consisting of i flows into the dc line,

i,,, (0 = -ilIl (0

As Do, is reverse biased and Ql and QZ are both OFF,

i , J f ) = iQ , ( f ) = i&) = O

At the end of this interval. ilIl fails to zero, finishing the resetting

inlO,) = 0 (3-65)

Dr becomes reverse biased again. From Eqs. (3-61) and (3-65), the duration of this

interval is detennined by

Ill13 LI11 42 =.T t , - t o = ( t , - ~ ~ ) - ( t ~ - t ~ ) = - - - (3-66) Y I 1 f i Y,,

The final value of each variable in Interval 6 defines the initial conditions of

3.4.8 Interval 7 (t, < r < t8)

This interval starts at r = t,. C , , , and L,,, undergo a resonance owing to the

difference between uQ, and the input dc line voitage Similarly to Section 2.4.6,

uc>,(t) = cl {l +cosbO(t - r d ) (3 -67)

Substituting Eq. (3-5) into (3-68),

7

Owing to the large value of L,,,, i,,, c m be ignored and regarded as O. This is consistence

with assurnption (ii) in Section 3.4.1 (Eq. (3-8)). As 4, is reverse biased and both Ql and

Q2 are OFF, thus

ia,,(t) = iQ, ( t ) = iJt) = O (3-70)

iJt) = i,,,(t) = O (3-71)

At the end of this interval, one switching cycle finishes. As in the steady state

operation, uQ, reaches Vo. Referring to Eqs. (3-6) and (3-67), the factor by which the

steady state initial drain voltage of QI deviates from y,, is detennined by

k =cos[o,(T, +t , -t,)] (3 -72)

Selecting a large LI## will result in a small a, (for exarnple. let o,T < rr) and hence k>O so

as to achieve ZVS over al1 the line/load range (refer to Section 3.4.2).

The final value of each variable in Interval 7 defines the initial conditions of

Interval 1 in the next switching cycle. which repeats the same process as in this cycle.

3.5.1 Effects of the Non-Ideal Components/Devices

Each realistic component and devices has some non-ideal properties as rnentioned

in Section 2-51. For the sarne reasons as explained in Section 2.5.1, the non-ideal

properties will not make a significant deviation fiom the operation of the circuit discussed

above.

A similar process to that in Section 2.5.1 can be followed to detennine the effects

of the Ieakage inductances, and it will not be repeated here.

3.5.2 Determination of Duty Cycle as to Regulate the Output Voltage

Refer to Fig. 3.3. In one switching cycle, L, sees a constant voltage n t - V o for a

duration of (D-lI,)T$, where D is the duty cycle of the main switch Q l and D, is the

reduction of the effectua1 duty cycle owing to L,, which is given by

Q = U? -Qf, (3-73)

and Ln sees another constant voltage -y , for the rest of the cycle, thus, the volt-second

balance of L , gives the following equation:

(D-D,) (ny,,- Q - (1 -D-D.JV0=O

which yields

( D - D, ) 17 ï<,, = y,

Assuming the output power is P,,. thus

Substituting Eq. (3-38) into (3-37), and substituting (3-26) and (3-76) into the result

Let D,, represent the duty cycle of the auxiliary switch Q2,

Dm= (12 + , I f ;

Getting (1, - . -t,) fiom Eq. (3-78) and substituthg the result and Eq. (3-17) into (3-77), it

yieIds

Eq. (3-75) indicates that, in order to regulate the output voltage at certain Line/load

conditions, the duty cycle of the main suitch should be

3.5.3 Advantages and Disadvantages of the Proposed Converter

The following major advantages of the proposed converter can be identified fiom

the above analysis.

(i) No need for an isolated gate drive for the auxiliary switch, because Q2 and Ql

have a common source connection (refer to Fig. 3.1 ).

(ii) Generating the gate drive signal is simple. because the on time of Q2, unlike in

the case of the active clamp topology. is fised ar a half of the resonance penod of the L,

L6Cd tank (refer to Section 3.4.2)

(iii) The ZVS turn-on transient of Q I , facilitated by Intervals 1, is not afZected by the

line and load conditions. T h e turn-off transient of Q I is affected by the load current Io as

shown in Eq. (3-47). With a suficient value of capacitance, C, will guarantee a ZVS

tunioff in Q I under the full load condition. Under Iight load, the rise of uQ, will be

slower. Hence, ZVS will always be achieved regardless of the line/load conditions.

(iv) Less EMI is generated owing to that C,, slows down speed of change of the

inductor current and capacitor voltage, as indicated by Eqs. (3-46) and (347).

(v) It is simple in circuitry, and al1 components of the auxiliary circuit require smdl

power ratings.

(vi) Conduction losses are not increased. Because C,, is always there to slow down

the voltage rise speed and to lower QI's voltage stress. Unlike in the existing techniques

where extra circulating power is need by the clamp circuit, the auxiliary circuit does not

draw extra power.

The disadvantage of the proposed topology is that the auxiliary switch has a hard

switching turnoff. But the switching losses in QZ can be minimized by selecting a

MOSFET through trading off between the least ON resistance and the least inherent

capacitance, and also by increasing the ratio of L,, to Lup, which lowers the voltage stress

on 0 2 at turnoff.

3.5.4 RMS or Average Current Values

In the design, the rms, average or peak current and voltage are required to

determine the rating requirements in selecting the components. Some of these values have

been obtained in the analysis. Other values are calculated below.

(1) RMS current in Ql

The current in Ql can be approximated with a square waveform (Fig. 3.2), thus,

For a conversion eficiency less than 1. Say 7, the RMS current becomes

(2) RMS current in Q2

The curent in QZ consists of two components, one is in a triangle wavefonn, the

other is a half penod of a sinusoidal waveform, as given by Eq. (3-19). Thus,

The average current is found to be

(3) -Average current in D,

The current in D, - is triangular. From Eqs. (3-22). (3-26) and (3-28). it is found

that the average current in D, is given by

(4) Average currents in Do, and D,,?

The current in D,, is of a complex waveform. The average current in Do can be

calculated as

and the average current in Do? is determined by

3.5.5 Losses Caused by the Auxiliary Circuit

(1) Switching losses in Q2: P, ,, It is found that

1 1 P , ~ ~ = - c,,-Q~ V: f , + 1, vil, JZJZLF-Q~ f,

2 3

where Co-xT uz is the output capacitance of Q2. and

t~ al is the OFF transient tirne of Q2.

(2) Conduction losses in QZ: P,. oz

The Iosses is found to be

P < - - ~ ? = I Xif-s-CJZ R I > - ~ Z

where RD-@ is the ON resistance of m. (3) Conduction losses in Dl and D,: P,. ,,,, ,

The conduction fosses in D, and D, are found to be

Pc-DIU = L'I..-I)I I c t ~ . - c ~ z + V l - . _ ~ loi-^^

where V' ., is the fonvard voltage drop of Dl. and

V' , is the forward voltage drop of D,.

(4) Total losses by the auxiliary circuit

3.5.6 Losses Removed due to ZVS Operation

(1) Switching Iosses in Ql in a hard switching operation: P,

The hard switching will cause a switching losses in Q l as given by

where tofl ,, is the OFF transient time of Ql? and

C,,, is the output capacitance of QI.

(2) Net saving of power due to the ZVS operation

The net saving of the power due to the ZVS operation of the proposed converter is

approximately

3.6 EXPERIMENTAL RESULTS

3.6.1 Experiment Setup

A prototype ZVS fonvard converter is built based on the design presented in

Chapter 5. Since the circuit outputs a power of 100 W at an output voltage of 5 V,

synchronous rectifiers are chosen in the output rectification stage of the circuit so as to

reduce the losses in the stage. An improved self-driven gate drive technique for

synchronous rectifier in the forward converter [18] is used to optimize the performance of

the synchronous rectifiers. The schematic of the prototype converter is shown in Fig. 11.2

in Appendix 11.

The operating conditions of the circuit are summarized as follows: (i) the input dc

line voltage varies h m 40 V to 60 V, (ii) the full load is 100 W at a output voltage of 5

V, and (iii) the switching fiequency is 300 kHz.

3.6.2 Key Waveforms

Fig. 3.6 shows the theoretical waveforms. which are drawn in MathCAD based on

the equations of uQl and iQl obtained in the steady state analysis in Section 3.5. Fig. 3.7

shows experimental results of the waveforms of drain voltage and current of Ql in the

prototype converter. These two figures are under the same operating conditions: V,,,=5 OV,

Po=lOOW. The cornparison between the theoretical and experimental results is made in

Table 3.1. It is seen that they are in good agreement.

Fig. 3.6 The drain voltage and current waveforms of Q1 in Fig. 3.1, which predicted by the steady state analysis made above. The negative drain current

to the latching of the body diode of Ql before it is turned on Verticai: 2A/div., 20V/div., Horizontal: O.Sps/div.

Table 3.1 Cornparison between the theoretical and experimental resdts

are is due

of the current, voltage and duty cycle of the main switch (~,,=5OV, P,,=1 OOW,f;=3OOkHz)

D VO 71 .OV 77.0V

Vpeak Ipeak 6.67A 6.80A

Theoreticai Experimental

0.29 0.3 1

1 15V 118V

Fig. 3.7 The experimental results of the drain voltage and current of Ql in a prototype ZVS converter of Fig. 3.1. The theoretical waveform is shown in Fig. 3.6

Vertical: 2Aldiv.. 2OV/div.. Horizontal: O.Sps/div.

Fig. 3.8 shows the theoretical waveforms of u,,, and io, based on the steady state -

anaiysis in Section 3.4 and 3.5. Fig. 3.8 is drawn with the software MathCAD. Fig. 3.9

shows experimental results of the waveforms of drain voltage and current of Q2 in the

prototype ZVS converter of Fig. 3.2. These two figures are under the same operating

conditions: r , 4 O V . P,l=lOOW. The cornparison between the theoretical and

expenmental results is made in Table 3.2. tt is seen that they are in good agreement.

Table 3.2 Cornparison between the theoretical and experimental results of the current. voltage and duty cycle of the auxiliary switch

(vjJ=50V, C1=l 00W,f;=300kHz) heak

3 .56A v ~ !

9.12V Theoretical vp,al, 1 15V

t I 1 I l I t I I I I Fig. 3.8 The drain voltage and current waveforms of Qt in Fig. 3.1,

which are predicted by the steady state analysis made above. Vertical: 1 A/div.. 20V/div.. Horizontal: O.Sps/div.

Fig. 3.9 The Experimental results of the drain voltage and current wavefoms of Q2 in Fig. 3.1. The theoretical waveform is shown in Fig. 3.8.

Vertical: lA/div., 2OV/div., Horizontal: 0Spsldiv.

Figs. 3.10 through 3.16 show the current and voltage wavefoms of the main and

auxiliary switches at different Iinelload conditions, veriQing the analysis in that ZVS is

always achieved in the main switch.

Fig. 3.10 Experimental results: the current and voltage of Ql at high line full load. Po= 1 00 W, V,=6OV. f.=300kHz. Scales: vertical--20V/div., 2Ndiv.; horizontal--

O.jps/div.

Fig. 3.11

A .spc

Experimental results: the current and voltage of Ql at hi& line light load. P,=20W, ~.11=60V,f;=300kHz. Scales: vertical--20V/div., ZA/div.; horizontal--O.Sps/div.

Fig. 3.12 Experimental results: the current and voltage of Ql at low line full load. Pt,= 100 W. yll=40v'f;=300kHz.

Scales: vertical--20Vldiv. 2Mdiv.: horizontal--OSps/div.

A - 5 p s

C

- 0

Fig. 3.13 Expenmental results: the current and voltage of Ql at low line light load. P,,=20 W. V,,=qOV.f;=3 00kHz.

Scales: vertical--20Wdiv.. 2Ndiv.: horizontal--0Spddiv.

curent 1

Fig. 3.14 Experimental results: the current and voltage of Q2 at medium line half load. P,=50W. C;,,=jOV.~=300kHz.

Scales: vertical--2OV:div.. 1 illdiv.: horizontal--0.5jddiv.

HAG current ,,,

Fig. 3.15 Experirnental results: the current and voltage of Q2 at high Iine light load. P,,=20 W. V,,=60V?f;=3001cHz.

Scales: vertical--2OV/div., 1 N d i v . horizontal--0.5ps/div.

Fig. 3.16 Experimental results: the curent and voltage of Q2 at low line light load. P =20W. Vt,=4OV.f,=30OkHz.

Scales: vertical--2OV/div.. 1 Ndiv. ; horizontal--0Sjddiv.

3.6.3 Effciency

Expenmental results of the efficiency from the prototype converter are obtained.

The input dc voltage varies from 40 to 60 V. The full load power is 100 W. Synchronous

rectification is used in the circuit ourput rectifying stage.

Fig. 3.17 shows the experimental results the efficiency vs. input voltage under full

the load condition (100W). The c o m p ~ s o n between the efficiencies of the ZVS and the

hard switching operation of the fonvard converter is made in Fig. 3.17. The hard

switching forward also employs synchronous rectifiers. The c o m p ~ s o n shows that ZVS

indeed makes a significant increase (about 5%) in efficiency. ZVS operation at fiequency

of 200 kHz is also tested. where the snubber capacitor and the prirnary of the coupled

inductor are adjusted to Suit for this frequency.

The efficiency is about 1% higher than that at 3001cHz The gain in efficiency is

due to the reduced switching losses in the auxiliary switch, and the gate drives of the

synchronous rectifiers.

40 45 50 55 60

Input voltage (V)

Fig. 3.17 The efficiencies vs. input voltage of the prototype converter in ZVS operation and non-ZVS operation of the forward converter

(conditions: P,,= 100 W. y,=5V).

+ ZVS operation Hard switching

0 - . -. -- - . - -- . - -- b

O 20 40 60 80 100

Output power ( W) - Fig. 3.18 The efficiencies vs. load of the prototype converter in ZVS operation and non-ZVS operation. Conditions: V,,,=50 V,f;=300 kHz.

Fig. 3.18 shows the eff~ciency vs. load under given input voltage for both the

proposed and conventional circuits. The proposed circuit always has better efficiency

than the conventional hard switching fonvard converter.

The efficiency is expected to be higher if optimized magnetics are used, and if a

PCB circuit is built. That means, using the proposed forward topology, a 90% forward

converter outputting 20A at SV is possible.

3.7 CONCLUSIONS

In th is chaprer a ZVS forward converter topology has been presented and

analyzed. The steady state operation of the circuit can be divided into seven intervals. The

steady state analysis of the circuit is perfom~ed and verified experimentally.

Analysis and experimental results silo\\- tliat the performance of the proposed

converter is enhanced with the awiliary circuit. -4bout 5% higher efficiency has been

achieved on the prototype circuit as compared with the conventional hard switching

converter. Higher efficiency is espected on PCB circuit with optimal rnagnetics. Other

major merits of the proposed ZVS fonirard topology include

(i) Lossless switching of the main switch. independent of the line and load conditions,

(ii) Simple power and control circuit,

(iii) No increase in conduction losses,

(iv) Ability to operate in either voltage or current mode control.

Therefore, the proposed converter topology wi l l liopefully be widely used in indusaial

application in the fùture.

SMALL SIGNAL MODELS AND CLOSED

Loop STABILITY

4.1 INTRODUCTION

The steady state analyses of the proposed converters have been performed in the

previous chapters, which have shown the advantages of the converters over the

conventional hard switching and existing ZVS circuits. However, only the steady state

analysis is not enough. The circuits should rolerate the line and Ioad variations, and they

should regulate the output against these variations by means of closed loop control. In

order to study the behavior of converters under these conditions, the small signai analyses

for both the converters are presented in this chapter. These analyses are also used to

optirnize the closed loop response.

This chapter presents the small signal models and the closed loop stability of the

converters. The small signal mode1 of a circuit differs with the loop structure, or the

control technique used. Normally, there are three types of control technique developed for

the dddc converters, narnely, the voltage mode control, the peak current mode control,

and the average current mode control. It has been s h o w in [1920] that the average

current mode control brings in the best dynamic performance, hence, it is discussed in

this chapter. As the flyback converter can utilize a model previously developed in [20],

only the srnall signal mode1 of the forward converter is derived below. During the

discussion, the equivalent senes resistance (ESR) of the capacitors is ignored because the

effects of ESR can be reduced with high quality capacitors and these effects is negligible

in the fiequency range of our concem (<IO0 W).

The structure of this chapter is as follows. Section 4.2 reviews the basic cnteria of

a stable closed Ioop system. Section 4.3 discusses the stabilization of the flyback

converter. Section 4.4 presents the denvation of the small signal model of the forward

converter, and discusses the stabilization issues. Section 4.5 presents the experimental

verifications of the model derived.

4.2 CRITERIA OF A DYNAMTCALLY STABLE SYSTEM

According to the Nyquist stability criteria, the closed loop stability of a switch

mode converter is optimal, if (i) the open loop gain has a slope of -20 dB/dec. in the

vicinity of the crossover frequencyf,, and (ii) the open loop transfer function has a phase

margin of about 45" to 63" [19-211. Proper compensation should be made around the loop

to meet these two criteria. Hence the loop should be tailored such that the above two

conditions are satisfred.

4.3 SMALL SIGNAL MODELS OF TIiE ZVS FLYBACK

CONVERTER

To simplify the discussion, it is assumed that the auxiliary circuit works for a very

short t h e compared to the main circuit, which is the practical case when UC3855 (shown

in Appendix 1) is employed as the PWM control chip. The duty cycle of the auxiliary

circuit Dm is about 0.07 to 0.1. Also, it is assumed that the converter operates in the

discontinuous conduction mode. Under such conditions. as analyzed in Section 2.4.2. the

effect of the auxiliary circuit on the transformer current is negligible, and hence it is

undetectable on the secondary side of the power transformer. In other words, it has litde

dynamic effect on the operation of the converter. Therefore, from the control point of

view, the auxiliary circuit cm be excluded from the closed loop. and importantly, the

analysis is that of a basic flyback converter.

Fig. 4.1 shows the block diagram of a conventional feedback control loops of the

standard flyback in the average current mode control. Fig. 4.2 shows a typical

implementation of the feedback loops of Fig. 4.1 [20].. The current loop is formed by the

following elements: (i) a current sensor resistor R,,? (ii) an error current amplifier CA, (iii)

a PWM comparator and the gate drive. and (iv) the power switch S. Current in the switch

is sensed. Because the control chip has a current synthesizer inside UC3855, the sensed

current is transformed to reconstnict the inductor current in L,,,.

Fig. 4.1 The Block diagram of the control loops.

Fig. 4.2 A typical implementation of the feedback loops of Fig. 4.1. The elernents enclosed by the dot-dash line are inside the UC3855 chip.

Through the current synthesizer, R,, reflects the actual current signal in Lm.

The voltage loop is compnsed of (i) the closed current loop, (ii) the voltage sensor

(R4 and R5), (iii) an error voltage amplifier VA, and (iv) the power circuit. The

compensation elements are selected below.

4.3.1 Small Signal Mode1 of the Current Loop of the Flyback

Converter

(1) Transfer function of the power circuit

From the previous work [20], the small-signal control-to-input gain of the flyback

current loop power circuit of Fig. 4.1 (fiom v,, at the CA output, to v,, the voltage across

RJ is given by

where, IL is the averaged inductor current in L,,,.

Incorporating this mode1 into the isolated flyback topology shown in Fig. 1.1-

where the tums ratio of the power transformer is Un, and that of the current sensor

transformer is K. the gain becomes

where F,(s) is the current sensor transfer function given by

Eq. (4-2) has a pole at O Hz and a zero at

This zero moves with IL, which corresponds to certain line and load conditions. In order

to maintain the stability under al1 line/load conditions, the crossover fiequency of the

current loop gain should be selected lower than the lowest zero given by Eq. (4.4).

Fig. 4.3 shows the bode plot of the current loop of the prototype flyback converter

(refer to the design example in Chapter j), where K=1/100, n=1/18. V0=5 V, Vw=5.5 V,

Rs=30 Q, and L,=50 pH, a n d m 0 0 kHz. In th is case it is found that the lowest value of

L, which corresponds to the full load and lowest input voltage, is about 190 kHz.

f (Hz) ----,

(a) Gain vs. frequency

(b) Phase shift vs. fiequency

Fig. 4.3 The Bode Plot of the opened current loop of the prototype fly back converter.

(2) Compensation for the closed loop stabilization

Concepts of the compensation for the closed loop stabilization c m be illustrated

with the example of the prototype converter.

The crossover fiequencyL should not go higher than the lowest zero fiequency of

the power circuit transfer function. Also, it should be seIected below one sixth of the

switching frequency [20]. In the example, iff;=200 kHz andJ=l90 kHz, then is set at

The resdt of the compensation is shown in Fig. 4.3(a). and has two poles and one

zero to give a proper loop gain. The implernentation is shown in Fig. 4.2. Thus the

transfer function of CA is determined by

where the poles and zero are found to be

In order to suppress the high fiequency noise caused by switching. it requires

additional pole around f,z by adding the network Rp-Cp, which gives

The value of each component is determined as 1201

In the example of the prototype converter, by selecting R,=3.9 kQ it is found that

C,=100 pF and R, 4 . 7 kQ. By putting a zero at J,=6 kHz' there are C, =4700 pF and

42=1 00 kHz. By Ietting Cp=l 000 pF, it yields Rp= 1.5 kn.

The compensation is shown in Fig. 4 3 a ) . Fig. 4 3 b ) shows the Bode plot of the

total open loop phase shifi. The open loop phase rnargin atf; is found to be 61 .jO.

The equivalent transfer function of the closed current loop is

G,,,(s), is an element of the voltage loop.

4.3.2 Small Signal Mode1 of the Voltage Loop of the Flyback Converter

The stability criteria for the voltage loop is the same as that for the current loop.

The compensation is needed to tailor the total voitage loop gain to fit the stability criteria.

(1) Transfer function of the power circuit

For the flyback converter output stage shown in Fig. 4.1, the small signal mode1 is

By the power balance equation,

(1, + Mu)( t + A C ) = (',rj +hl,rr)('itj +AYlj) (4- 1 6 )

where hl,, A Vo, Mllj, and A y,# are the smdl signal perturbations in the related signals.

Ignoring the second order terms and assurning a constant V _ and applying the Laplace

transformation, Eq. (4-1 6) yields the smdl signal mode1 for the output stage:

I#,<(, +y,<) = ylj[,,

where

If,= PyRU

From Eqs.(l- 14) and (3- 16)- the transfer function of the output stage is

Then the power circuit transfer function. from the output of VA to the output end of the

converter. is

Fig. 3.4 shows the Bode plot of the voltage loop gain of the prototype flyback.

(2) Compensation for the closed loop stabilization

Refemng to Fig. 4.4(a). the compensation for the voItage loop c m be achieved by

a PI controller. The implementation is s h o w in Fig. 4.2. Thus the transfer function of the

VA compensation network and the voltage sensor is

A

R3 1 1 _+ G,, (s)& ( s ) = Y-- = ( V" R.: SR&

)

In the example of the prototype flyback converter, it is found that, by selecting the

crossover frequency at 10 ldIt and choosing R,=3 kR and R,=4.5 kR, the needed

compensation requires R,=4.9 WL and C3=7.8 nF. The phase margin is thus found to be

63 -2".

J!Hd -----+

(b) Phase shift vs. fiequency

Fig. 4.4 The Bode plot of the gain of open voltage Ioop of the prototype flyback converter.

4.4 SMALL SIGNAL MODEL OF THE ZVS FORWARD

CONVERTER

Fig. 4.5 shows the block diagram of the typical control loops of a forward

topology. where the inductor current i, is controlled.

Fig. 4.5 A typical block diagram of the control loops of forward converter.

Fig. 4.6 A typical implementation of the feedback loops of Fig. 4.5. The elements enclosed by the dot-dash line are inside the UC3855 chip.

Through the current synthesizer, R,v reflects the actual current signal in La.

Fis. 4.6 shows a typical implernentation of the feedback loops of Fig. 4.5 in the

case of the fonvard topology. The current Ioop is foxmed by the folIowing elements: (i) a

current sensor resistor R,, (ii) an error current amplifier CA, (iii) a P WM comparator and

the drive, and (iv) the power switch S.

Small Signal Modeis of the Current Loop of the Forward

Converter

Transfer function of the power circuit

Current in the switch is sensed. But, owing to the current reconstruction element,

is called the 'current synthesizer' in the PWVI chip UC3855, the current in Lt,.

narnely i,. is virtually sensed and hence controlled.

~ a t i n ~ f of main:

Sensed, current: - T,

by R.,I 4

Reconstructed ,* -

synthesizeq : I

Fig. 4.7 The reconstruction of the sensed cturent in the proposed ZVS fonvard converter. The sensed switch current shown in Fig. 3.2, is reconstructed by the

synthesizer inside UC3855 to reflects the waveshape of the output inductor current. D is the main duty cycle, De is the effective duty cycle, and D, is the difference between them.

Fig. 4.7 shows the current reconsiructing function in the proposed ZVS fonvard

converter. The sensed switch current shown in Fig. 3.2, is reconsmcted by the

synthesizer inside UC3855 to reflect the waveshape of the output inductor current. D is

the main duty cycle, De is the effective duty cycle, and D, is the difference between them.

Dr is due to the effects of Ls in Fig, 3.1 and is determined by Eq. (3-79). From the loop

point of view, such a reconstruction fünction simply hides the effects of the auxiliary

circuit, making it look like a conventional forward converter. The only exception here is

that the effectua1 duty cycle is no longer D, but is

0, = ( 0 - 0,) (4-22)

Therefore, the state space average equation of the converter is,

where, n = AT, !!V,,.

Then the DC mode1 of the converter is

which is confimed by Eq. (3-75). With assumption of constant y,l and y)_ the small

signal AC mode1 is represented as

According to Eqs.(3-25), (3-26)' (XZ), (3-34), (3-37) and (3-78), it can be obtained

Substituting Eq. (3- 17) into (4-26). and substituting L+dl,,, y,,+A yll and D,+AQ for their

respective variables, and ignoring the second order tems, gives

Hence,

u Dx + 0.5% AD, =-AIo - IZ C l Y t I

A Y I 1

By the assurnption AIo = and AP:tt = 0,

In the Laplace transformation, Eq. (1-29) can be written as:

Substituting it into Eq.(4-25), and rearranging the terms!

Then the sensed voltage on the sensor resistor, on the secondary of the sensor

transformer. is

CR, = nKR,iLO (4-32)

where K is the t u s ratio of the current sensor transformer? R, the sensor resistor.

Let Vcw represent the peak to peak voltage of the saw tooth waveform, then

where v,, is the output of the current amplifier of the current loop.

Therefore, f?om Eqs. (4-31) through (4-33), the control-to-output gain of the forward

current loop power circuit (fiom v,, at CA output, to v,, the voltage across the sensor

Fig. 4.8 shows the Bode plot of the open loop gain of the current loop of the

prototype forward converter (refer to the design example in Chapter 5 and Appendix II),

where ~ 1 / 3 , L0=6 pH, L,=O.3 pH, f;=300 kHz, Rs=12.5 R, K=1/100, yn=50 V and

V,=5.5 V. Then the pole of the power circuit is found to be at 2.6 kHz.

(2) Compensation for the closed loop stabilization

The needed compensation network is similar to that in the flyback circuit, i.e.. two

pole and one zero compensation. The implementation of the compensation is shown in

Fig. 4.6. Similar process to that in the case of flyback topology is followed.

Eqs. (4-5) through (4-9) define the transfer function of the compensator and the

poles and zero. Eqs. (4-1 1) and (4-12) determine the values of R, - and C,. C, is determined

fiom Eq. (4-7) by setting the second pole. 4,. In the example of the prototype fonvard

converter. seIectin_gf,=30 kHz R,=3.3 KS2.f.=8.0 kJ3z andf,,=l00 kHz. it is found that,

R,=33 - kQ, C, =56 pF and C,=560 pF.

Fig. 4.8 (b) shows the Bode plot of the open loop phase shifi of the current loop of

the prototype forward converter. The phase rnargin is about 61 -5'.

The equivalent transfer fùnction of the closed current loop has the same definition

as in Eq. (4-14).

4.4.2 Voltage Loop of the Forward Converter

(1) The characteristic of the power circuit gain

The closed inner Ioop is an element of the voltage loop. Refening to Fig. 4.6, the

output stage of the circuit has a transfer function as given by

Then the power

tram fer h c t i o n

f (Hz) - (a) Gain vs. frequency

f (Hz)-

(b) Phase shifi vs. fiequency

converter? has a

Fig. 4.9 The Bode Plot of the open voltage loop gain and phase-shifi of the prototype forward converter.

Fig. 4.9 shows the Bode plot of the open voltage loop of the prototype forward

converter.

(2) Compensation for the closed loop stabilization

With reference to Fig. 4.9(a), the compensation can be performed by a PI

controller. The implementation is shown in Fig. 4.6. The transfer function of the VA

compensation network and the voltage sensor is defmed by Eq. (4-21). In the case of the

prototype forward converter. if selecting the crossover fiequency around 10 WIz R,=3

ki2 and R,=4.5 kS2. the components for the PI are found to be R 9 . 3 kQ and Cj=6.8 nF.

The open voltage loop gain is show in Fig. 4.1 1. The phase rnargin is 64.8'.

4.5 Experimental Results

Experimental verification of the srnall signal models discussed above is made on

the prototype forward converter. For convenience. the transfer function of the voltage

loop power circuit. G,,s(s)t is tested.

Figs. 4.10(a) and 4.1 1 (a) show the experimental results of the Bode plots of

G,,.(s). Figs. 4.10(b) and 4.1 1 (b) show the theoretical predictions of G,,,,.(s) in the same

scale as Fig. 4.10(a).

Table 4.1 The theoretical and experimental results of the power circuit transfer function.

results Experimental

results

Theoretical

phase at 100 kHz beyond

phase at 10 kHz

-89.6 deg.

phase in low freq. range

O deg.

gain in low freq. range

6.0 dB

5 .O dB

gain at 100 kHz -37.7 dB

gain at 10 kHz 3.2 dB

O deg 3.0 dB -98.0 deg 1 -180deg

-43.0 dB beyond -180 deg

>.: I/R<dB) 0: 8 O MKR 58 084.366 Hz A MAX 63.00 dB GAIbl -34.8354 dE

OdB

A 3 I N -60.00 dB ÇTART 10.000 Hz w n r i f 50.00 dea STOP 100 OOO. CG0 Hz - - -

STOP= 1000t30.QXl q Z (a) Experimental results. Vertical: 12 dB/div.

frequency - (b) Theoretical results. Vertical: 20 dB/div.

Fig. 4.10 Comparison between the experimental and theoretical gain of the open voltage loop power circuit.

Comparison between theoretical and experimental results are shown in Table 4.1,

which shows that they are in a good agreement.

-O deg.

h ? A I N -60. 00 . d 3 START 1 0 - 000 HZ B r ~ ; I ~ K - 1 eo. o d+g STOP 100 ooo, occ Hz .=S€P>LE= L 1 1 HGP\BC

(a) Experimental result. The theoretical prediction is s h o w in @). Vertical: 36 degdiv.

(b) Theoretical prediction.

Fig. 4.11 Cornparison between the phase shift of the open voltage loop power circuit transfer fiction.

Figs. 4.12 through 4.14 shows the experimental results of transient responses of

the fonvard circuit under step force. The circuit is stable under these step changes.

Experiment of the step up of the input voltage is not able to cary out for the difficulty in

getting a f a t step change in the dc line with available instruments.

Fig. 4.12 Experimental results of the fonvard converter: transient response. Io steppes up fiom 8A to 20A. Conditions: V,=50V,f;=300kHz.

Vertical--SA/div., 1 Vldiv.. Horizontal--50pldiv.

Fig. 4.13 Experirnental results of the forward converter: transient response. Io steppes down fiom 20A to 8A. Conditions: y.,r=50V,f;=300kHz.

Vertical-SNdiv., 1 V/div., Horizontal--5Ops/div.

Fig. 4.14 Experimental results of the forward converter: transient response. y,, steppes down fiom 60V to 40A. Conditions: PO=l 00Wof;=300kHz.

Vertical--5Ndiv.. O.SV/div.. Horizontal-- jOOps/div.

4.6 CONCLUSIONS

Smail signal models of the proposed circuits in the average current mode conuol

and the closed loop stability compensation have been discussed in this chapter. The

proposed flyback converter can utilized the previously established model for the standard

flyback and the compensation c m follow the conventional scheme and process.

As there is no suitable model for the proposed forward converter, the model

thus derived in this chapter. The additional inductor L, of the auxiliary circuit bnngs

pole at the fiequency in proportional to the switching frequency

the are simple and straightforward.

and Ls. Compensation of

This chapter presents the design procedures of the proposed converters. The

design is based on the required specifications, such as the input voltage range. output

voltage, output power. switching frequency, permitted ripple in the output voltage. etc..

and uses the analysis presented in the previous chapters.

Design for generating gating pattern for the auxiliary switch in the proposed

converter topologies is also presented in the case where a single output PWM control chip

other than UC3855 is employed.

The structure of this chapter is as foIlows. In Section 5.2, the design of the flyback

converter is presented and an example is given. In Section 5.3, the design of the forward

converter and an example are presented. In Section 5.4, an implementation of the gating

pattern generating for the auxiliary switch in the proposed converters is illustrate and

verified expenmentally.

5.2 DESIGN PROCEDURE OF THE FLYBACK CONVERTER

Assume the following specifications and parameters are known.

Dm,--Maximum duty cycle

f;--Switching f'kequency, Hz

P;-Full load output power, W

ytt ,--Maximum input voltage, V

y,, ,in--Minimum input voltage, V

Va--Output voltage. V

ATl,--Perrnitted peak-peak npple in y,,' V

Ay;-Perrnitted peak-peak ripple in V,,. V

5.2.1 Design of the Power Circuit

The following design procedures are referred to the circuit s h o w in Fig. 2.1. A11

parameters are in SI units.

(1) Turns ratio of the transformer, NdlV,

According to Eq. (2-56), and considering the forward voltage drop V,.. of the

rectifier diode,

where, D'(cl -Dm,) is the equivalent duty cycle of the rectifier current, and

VF is the fonvard voltage drop of the rectifier.

Eq. (5- 1) gives

and

(2) Magnetizing inductance, Lm

In the discontinuous conduction mode. fiom Eq. (2-40). there should be

Combining Eqs. (5-4) and (2-39) gives

(3) Output capacitor, Co

Fig. 5.1 shows the relationship between the output rectifier current i and load

current 5 in the case of discontinuous conduction mode operation. Assurning al1 the ripple

current component of i, flows through $, and the average current flows through R,,. It can

be calculated that

Fig. 5.1, The secondary current and the output voltage ripple in the converter of Fig. 2.1. The operation mode is assumed to be discontinuous conduction.

As IV is deterrnined by Eq. (2- 39), and

and

AV, 2 AQ/C,

The output capacitor can be found fkom Eqs. (2-39) and (5-6) tbrough (5-8):

(4) Selection of the main switch, Ql

By Eq. (2-33). the voltage rating of Q l is determined by

where: V,, is the drain to source breakdown voltage rating of QI.

The rrns current is determined by Eq. (2-60). and the average current rating is detemined

b Y

where, the constant 1.5 accounts for the worst case efficiency of 70%, and

If, ,,, is the continuous drain current rating.

From Eqs. (2-26) and (2-55), the peak pulse drain current rating is

where. r,, Q, is the pulse drain current rating.

102

Besides these ratings, a MOSFET which has the lowen ON resistance on the

product catalogue should be selected.

(5) Selection of the output rectifier, Do

The rectifier should be fast rectifier diode or Schottky diode. Its voltage rating is

determined by

v~-L!ri > v~r-rnax + (5-13)

where. VR , is the reverse voltage rating.

Its current rating is determined by

where. Io , is the average rectified current rating.

(6) Selection of the input capacitor, Ci,

The input capacitor is determined by [Z]:

where, A y l l is the allowable peak-to-peak ripple voltage in the input line. and

AI.,_ is the time for which Cl,, must supply the current in case the input line fails.

5.2.2 Design of the Auxiliary Circuit

(1) Auxiliary duty cycle,

Dm should be limited by

Dm (1 - 2 DmJ (5- 16)

In this way. the auxiliary circuit does not affect the resetting of the core of T,

Dm may also be detennined by the control chip like UC3855, where it is fixed. In

this case the design should observe the fixed factor.

(2) Snubber capacitor, C,,

The value of Cm, determines the rise time of QI's voltage at its tumoff. as

described in Eq. (2-28). For a very short duration, we c m approximate

Limit the nse of u,,, to be below yj1 within the demanded time tr. Thus, fiom Eqs. (2-29)

and (5-1 7),

On the other hand. the rise time should not exceed the gap left by 2DlIlm and DaUr. which

eives a Iimit C

From Eqs. (2-28) and (2-33). there is an approximation

Combining Eqs. (2-28). (5-19) and (5-20),

The voltage rating of the capacitor should not be less than that of Q I .

(3) Primary of the coupled inductor, Lw

As analyzed in Section 2.4.1, Dom is fixed and corresponds to a quater of the

resonant penod of the network consisting of L,, and Cd. Referring to Fig. 2.2, there exists

a relationship:

Dm = ( t z - t i ) / ~ ,

According to Eqs. (2-10) and (5-22),

which gives

The core of the coupled inducton shouId be selected so that it can handle a power

as given by

1 P. = 7 LI i&f, -

where. iop is defined by Eq. (2-1 6).

(4) Selection of the auxiliary switch, Q2

The on-resistance of Q2 should be as srna11 as possible. Its voltage rating is the

same as that of Ql. It should have a current rating capable of handling the peak

discharging current I,, and an RMS current I,,, Q2 as given by Eq. (2-6 1 ).

(5) Secondary of the coupled inductor, L,

According to Section 2.4.3, L, should be as big as possible, so as to rninimize the

voltage stress(refer to Eq. (2-25)) and hence the -off losses in PZ. But a bigger La,, will

also extend the energy releasing time.

From Eqs. (2-18) and (2-24), and with reference to Fig. 2.2, the energy releasing

time is determined by

In order to release the stored energy in the core completely within switching cycle. there

should be a limitation,

&a - &2 < (1 - DOA TS

n u s , fiom Eqs. (5-26) and (5-27), it is determined that

( 6 ) Selection of the blocking diodes, D, and D,

Both the diodes are fast recovery diodes with low voltage drop. D, is optional. and

is only applicable to cases where the releasing current of L, may reach zero before Ql is

turned OFF. or

r , - r 2 = - J E > D ~ ~ ~ T . , K t ,

Without LI,, the charged output capacitor of Q2 will discharge into Ql after the tum-off

of Q2, increasing the losses. Therefore DI is only dispensable in the design where Eq. (5-

29) is valid.

DI should be selected so that it is able to handle a peak current of IOP. As it is in

parallel with Q2 when Ql is ON and QZ is OFF, thus, fiom Eq. (2-25), its voltage stress

i s

Similarly, D, should be able to handle a peak cuITent of 1, given in Eq. (2-19). Its

voltage stress is

5.2.3 A Design Example

A prototype flyback converter works under the following conditions:

(i) Input voltage: ytl ,,=16O V. and i:,) ,in=90V - -

(ii) Outputs: two outputs, (a) Vo1=5 V, P,,=10 W, and (b) V O- ,=20V. <,=20W. Total: 5OW

(iii) Permitted ripples in the outputs: A Vo,=50 rnV (Le., 1 %) , A VO2=200 mV (Le., 1 %)

(iv) Maximum duty cycle: Dm_=0.4

(v) Switching fiequency : f;=200kHz

(vi) Auxiiiary duty cycle: DOlLr=0.075 (fixed by UC3855)

(vii) Input capacitor voltage sustaining tirne: Af,T_=lOO/j;

Table 5.1 The parameters of the prototype flyback converter

parameter

I

L n , Co, Cd

c,!, Do, DO?

selection 1/18 1 /5

50 p H 220 pF 100 pF 200 pF MBR735 MBR8 10

ratings

35V, 7SA 1 OOV, 8A

parameter

Qf

C.Wh

Lm Lm 0 2

Dp D2 Controller

selection IRFP450 3.3 nF IS p H 90 p H IRF730

HFAOSTB UC3855

ratings 500V, 14A,0.4R

400V, 5.5A. 1 .OC2 600V, 8A

Table 5.1 shows the design and selection of each component and device of the

prototype converter, which is made by following the design procedure presented above.

5.3 DESIGN PROCEDURE OF THE FORWARD CONVERTER

The design of the forward converter is also based on the specifications of the

application. Assume the following specifications and parameters are known.

D, ,,--Effective maximum d u 6 cycle

f;--Switching frequency. Hz

P,J--Full load output power? W

A y,--permitted peak-peak ripples in cl, V

y,, max--Mvia><imurn input voltage. V

P;,! ,i,,--Minimum input voltage, V

PL--Output voltage. V

Ay;-permitted peak-peak ripples in V, V

5.3.1 Design of the Power Circuit

The following design procedures are referred to the circuit shown in Fig. 2.1. Al1

parameters are in SI units.

(1) Turns ratios of the transformer, N p s , N p i

From Eq. (3-75)

where, De ,, is the effective duty cycle of the main switch, Le., De ,, =D-D,.

Taking into account the forward drop of the rectifier, it is modified as

When De ,,<OS, usually

P= * 1 NP

If Dem_>0.5, to guarantee successfûl core resetung, the turns ratio shouid be

(2) Output inductor, L,

Assume the converter is at the boundary of the continuous conduction mode

operation when its output power is a twentieth of Pf1. Hence there is [23]

which gives

(3) Output capacitor, Co

The ripple voltage can be found as given by [23]

17

Hence, Co should be chosen as

(4) Magnetizing inductance, Lm

Assume the magnetizing current accounts for Iess than one twentieth of the peak

input current. that is,

Because,

Hence,

(5) Selection of the main switch, QI

The switch should be selected so that it has the lowest ON resistance among the

product catalogue. The voltage rating is determined by Eq. (3-5 1 ) as

['D.S.S_~I L'IN

where. VDSs (,, is the drain to source breakdown voltage rating of Q I .

The rms current is determined by Eq. (3-85): and the average and peali current ratings are

determined by

Po I , i ~ - ~ i > 15

Vin-min Dmax

where, the constant 1.5 accounts for the worst case efficiency of 70%,

IFei is the continuous drain current rating, and

{,, ,,, is the pulse drain current rating.

(6) Selection of the output rectifier, Do, and Do,

The rectifiers should be fast rectifier diodes, Schottky diodes or synchronous

rectifier MOSFETs. Their voltage rating is detennined by

F R - ~ o > n Vrrr-ma.

where V,-, is the reverse voltage rating .

Its current rating is determined by

where, I, ,], and I,, ,,,, are the average current rating of Do, and Do,- respectively.

(7) Selection of the input capacitor, $,

The selection criterion for C,,, is the same as Eq. (5-1 5).

5.3.2 Design of the Auxiliary Circuit

(1) Auxilia- du@ cycle, Du,',

The maximum Da, should be limited by Eq. (5-16) so as not to affect the resetting

of the core of T,. It should be noted that, in the case of the Forward converter topology?

Dm, corresponds to half the resonant period of the network consisting of Lp. C,,,Ii and T,

(2) Snubber capacitor, C,,

The value of C-,,,, determines the rise time of the drain voltage of Ql at its turnoff.

as described in Eq. (3-46). For a very short duration, it is approximated to

Limit the nse of u,, below P;,) within the demanded

On the other hand. the rise time should not exceed

gives a limit

time tr. Thus, fiom Eq. (Mg),

(5-50)

the gap lefi by 2D and Dar, which

t s - t ~ 5 (1-2Dmm - Daw) T.v

Combining Eqs. (5-49) and (5-51).

11 I o Cwh 5 -(l - 2 Dmzu - Dam) Ts

2 v ,l,

(3) Primary of the coupled inductor, L,

From Eqs. (3-3) and (3-16).

Because D, corresponds to a half of the resonant period, Le..

Tt gives

The core of the coupled inductors should be selected so that it is able to handle the power

given by Eq. (5-25), where Iap is determined by Eq. (3-25).

(4) Additional inductor, L-v

From Eq. (3-1 7), it c m be determined that

7

L, = n- L,

Ls can be integrated into the secondary windings of the power transformer.

(5) Selection of the auxiliary switch, QZ

The on-resistance and inherent capacitances of Q2 shouid be low in the product

catalogue. Its voltage rating is the same as of Q I . The current rating should be able to

handle the peak discharging current Iap given by Eq. (3-17), and an RMS current I,,, Q,

given by Eq. (3-87): and an average current given by Eq. (3-88). C

(6) Secondary of the coupled inductor, L,

From Eq. (2-37). Lm should be large in value so as to reduce the turnoff voltage

stress on 03. However: Eq. (5-27) should aiso be satisfisd so as to release the energy

stored in the core of the coupled inductor within one switching cycle. From Eqs. (3-22):

(3-25), (3-3 1 ) and (5-27)-

(7) Selection of the blocking diodes, D, & D,

D, and D, should be able to handle a peak current of l a p and L, repectively.

Their voltage ratings should be higher than their voltage stress given by Eqs. (2-23) and

( H Z ) , respectively.

5.3.3 A Design Example

The specifications of the prototype forward converter is as follows.

(i) Input voltage: - ,,75 V, and y?, _,,,=35V -

(ii) Output: Vo=5 V, Po=lOO W

(iii) Permitted ripple in the output: AV0=50 mV (i.e., 1%)

(iv) Maximum duty cycle (effective): De - ,,,=0.4

(v) Switching fiequency :f;=3OOkHz

(vi) Auxiliary duty cycle: Dmr=0.075 (fixed by UC3 855)

(vii) Input capacitor voltage sustainkg tirne: A<ux=lOO/f;

Table 5.2 shows the design and selection of each component and device of the

prototype converter. which is made by following the design procedure presented above.

The design of the synchronous rectification stage is based on the design procedure

presented in [ 1 81.

Table 5.2 The parameters of the prototype fonvard converter

parameter selection n 1 /3

* Two in parailel in order t c

ratings

50V,75A, 9.5mQ

200V, 18A, o. 18Q

reduce the conduction losses in the switch.

parameter

c.v,rtj

Ln,7

Lm 4 0-3

Dl Br

Controller

selection IO nF

3 pH 90 p H 330 nH RF640

HFA08TB

UC3 8%

ratings

200V. 18-4: 0.18Q

600V. 8-4

5.4 GATING GENERATION FOR T E E AUXILIARY SWITCH

UC3855 can be directly employed as the PWM control chip of the proposed

converters. It produces two gating signais to drive the main and auxiliary switches. The

auxiliary gating signal has a fixed duty cycle of about 0.075. The major features of

UC3855 include (i) average current mode control, allowing better stability and easier

contml loop design? and (ii) internai current synthesizer, simpli&ing the current sensing

method (see Appendis 1).

A problem in using UC3855 is that the auxiliary duty cycle is not adjustabie. As a

result. the auxiliary duty cycle may not be the optimal one' which will result in the least

losses in the auxiliary circuit. Another problem is that UC3855 is expensive as compared

to most of the single output PWM chips.

#en a PWM chip of single output is selected as the control chip. gating for the

auxiliary switch can be generated with an additional sub-circuit as presented below.

5.4.1 Gating pattern generation by additional logic and drive circuit

Fig. 5.2 shows an example of the simple implementation of the auxiliary gating

pattern. It consists of a Schmitt trigger. a Op-Amp, inverters and AND gates. Other logic

combinations exist but the function it fulfills is the sarne: to split the original PWM pulse

from the single output PWM chip into two pulses: one for the auxiliary switch and the

other for the main switch. The additional logic and drive circuits form a splitter.

Fig. 5.3 shows key waveforms at the indicated points in Fig. 5.2. The auxiliary

duty cycle is adjusted by varying the time constant of the RB-CB network of Fig. 5.2.

Fig. 5.2, The pating generation circuit, a splitter, which generates the auxiIiary gating on basis of the original PWM signal

time

Fig. 5.3, The operationa1 waveforms in the splitter: voltage waveform at the corresponding point in Fig. 5.2

In Fig. 5.3, V, and V, appear to have the sarne wave shape. The AND gate

between point E and seemingly unnecessary, is of practical importance. This is

because d l the gates have delays in their response. In order to synchronize the two

gatings to an accurate timing sequence, a symrnetrical structure in the splitter is required,

which results in the least difference in delay for the two output gating signals.

5.4.2 The design of the splitter

(1) Selection of R, C,j and D,

The duty cycle of the auxiliary switch, or the pulse width of the auxiliary gating

signal. c m be set by the proper value of R, and C, in the spiitter in Fig. 5.2. The

following equation should be satisfied

where c,,,, is the high voltage level from the PWM chip output.

Eq. (5-58) yields

The diode D, is introduced to follow the fast &op of PWM signals. It should be a

fast diode.

(2) The voltage divider, RA, and R,,

Because V,,, is usually about 10- 1 5V, while the high output voltage V,, (logical

level) is usually 6V. a direct connection of IT,,l,, to the logic circuit may destroy it.

Therefore, the linear voltage amplifier is inserted between the PWM output and the logic

circuit. The magnitude of the amplification is less than one, and should obey the relation:

An additional capacitor CA is introduced to balance the stray capacitors of RA, and

R A , making the amplifier a purely linear device. Its value is decided experimentdly.

(3) The seleetion of the logic gates and the driver

All the logic gates should be capable of high speed response. CMOS logic circuits

are suitable for the splitter. High speed dnvers should be selected.

5.4.3 A Design Example

Table 5.3 shows the parameters of the spliner of Fig. 5.2 in a design example.

UC2844 is used as the PU'M control chip. It has only one gate drive. The splitter is thus

ernployed to generate the gate drive for the auxiliary switch. Fie. 5.4 shows the

experimental results of the gating signalsl which verïQ the design.

I C H I . SV CH2 . SV

Fig. 5.4 The expenmental results of the gating patterns generated by the splitter of Fig. 5.2.

channel 1 : original PWM signal fiom UC2844 channel2: gating for auxiliary switch Q.2 charme13 gating for main switch Q I

Table 5.3 The parameters of the splitter in a design example

' * n i e Schmik trigger and the Op-amp are subçtituted with 1

parameter

RA L RE CA

RB CR

inverters in the example.

180 kC2 parameter 1 DB IN4 148

TC74HC04P MC74HCO8A

IR21 10

91 ki2 1 Inverters* 0.22 pF 1 ~ ~ ~ g a t e 2.2 ki2 500 nF

Drivers

This thesis has discussed zero voltage switching (ZVS) flyback and forward

converter topologies. Such a topic is of special importance. because both the topologies

are very popular in industrial applications. especially in the distributed power systems of

the advanced communication and computer ne tworks.

This thesis can be summarized as follows. In chapter 1. existing ZVS flyback and

fomrard converter topologies are bnefly reviewed and their drawbacks are sumrnarized.

These topologies lose ZVS at light load. require complicated gate drive schemes. achieve

ZVS at the cost of increasing the conduction losses, have restrictions on use due to

patents.

In Chapters 2 and 3, ZVS flyback and forward converter topologies which employ

an auxiliary circuit have been presented. The modes of operation of each circuit is

identified. During each switching cycle, the flyback converter operates in five distinct

intervals and the forward converter operates in seven intervals. By selecthg the values of

the snubber capacitor and the coupled inductors, ZVS cari be always achieved. Steady

state anaIysis is perfomed. and the factors influence the performance of the circuit is

investigated. Experiments on the prototype converters are carried out and the analysis and

design are verified.

In Chapter 4, the smdl signal models and closed loop stability are discussed.

Transients responses are obtained experirnentally. Finally, in Chapter 5. design

procedures of both converters and of the gating pattern generation for the auxiliary switch

are presented and design exarnples are given.

6.2 CONCLUSIONS AND CONTRIBUTIONS

The follouing conclusions can be made.

(i) The auxi1ia.q circuit is simple, and o d y a few lo~v power rating components and

devices are required.

(ii) The gate drive scheme for the auxiliary suitch is simple. No isolated. variable

duty cycle gate drive is required by the auxiliary switch.

(iii) ZVS can be always achieved whatever line/load conditions, and no conduction

Zosses are increased.

(iv) The prototype flyback converter has about 7% higher efficiency than its hard

switching counterpart. The efficiency is rneasured under the following conditions:

switching fiequency is 200 kHz, input dc line voltage range is fiom 90 V to 160 V. two

outputs, one of which is 10 W at 5 V and the other is 40 W at 20V.

(v) The prototype forward converter has about 5% higher efficiency than its hard

switching counterpart. The efficiency is measured under the following conditions:

switching fiequency is 300 1<Hz, input dc line voltage range is fiom 40V to 60VI the load

power is 100 W at 5 V, synchronous rectifiers are employed.

(vi) The small s ipa l analysis show that the flyback converter can utilize the srnaIl

signal model previously developed for the conventional flyback. The forward converter

has a pole proportional to the switching fiequency and the additional inductance inserted

into the secondary circuit. The closed loop design based on the denved model has a good

dynarnic response.

(vii) The disadvantage of the auxiliary circuit is that it has hard switching at tum-off.

though the losses associated with it c m be reduced by increasing the ratio of the two

coupled inductors.

The major contributions of this thesis include:

(i) Systematically analyses of the proposed converters are performed,

(ii) Design procedures are developed.

(iii) Prototype converters are built and experiments are carrïed out and the analysis and

design are verified experimentally,

(vi) Higher efficiencies have been obtained.

6.3 SUGGESTIONS FOR FUTURE WORK

The following suggestions c m be made for future work.

(i) The resuits obtained in this thesis have shown the advantage of the proposed

converters. The prototype converters on printed circuit board (PCB) should be built and

use optimal magnetics to M e r optimize the performance.

(ii) To further kprove the efficiency, new synchronous rectification techniques with

resonant gate drives rnust be investigated in the proposed circuit topology.

Mohan, N., Undeland, T.M.. Ro bbins, W.P., Power Electronics: Converter,

Applicationsy and Desi@, John WiIey & Sons? 1989, pp. 1 85- 1 86.

Carsten, B., "Design techniques for transformer active reset circuits at high

fiequencies and power levels," High Frequency Power Conversion Proceedings.

1990, pp. 235-246.

Harada. K., Sakamoto, H., "Switched snubber for high frequency switching," ZEEE

PESC '90 Record. Vol.1, pp. 18 1-1 88.

Jitam, 1.' "Zero voltage PWM. double ended converter, " Higi~ Frequency Power

Conversion Proceedings. 1997, pp. 394-404.

Tsai. F., Ng? W., '' A low cost. low-loss active voltage-clamp circuit for interleaved

single-ended Fonvard P WM converter," IEEE APEC '93 Record, pp. 729-73 3.

Watson? R., Lee, F.C., Hua, G.C., "Utilization of an active-clamp circuit to achieve

sofi switching in Flyback converters', IEEE PESC ' 91 Record, pp. 909-916.

Harada K., Sakamoto, H., "On the saturable inductor commutation for zero-voltage

switching," pp. 1 89- 1 96

Kim, H. J., Leu, C. S., Fanington, R., Lee, F. C., "Clamp mode zero-voltage-

switched multi-resonant converters," IEEE PESC '92 Record, pp. 78-84.

Tang, W, Tabisz, W., Lofii, A.? Lee, F. C., Vorpenan, V., '?DC analysis and design

of Forward zero-voltage-switched multi-resonant converter,'? IEEE PESC '90

Record, pp. 333-340.

[l O] Andreycak, B., "Active clamp and reset technique enhances Fonvard converter

performance," Unitrode Design Seminar '91, Section 3, pp. 1-1 8.

[ I l ] Zaity T., Ninomiya, T., Shoyarna, M., Tanaka, H., "P WM-controlled current-mode

resonant converter using an active-clamp technique,'' IEEE PESC '96 Record, pp.

89-93.

[12] Joug., G. B., "New sofi switched PWM converter," IEEE PESC '96 Rem- pp.

63-68.

[13] Hamada. S.? Mii- T., Hiraki, E., Nakaoka. M., 3anirable reactor & lossless

capacitor-assisted sofi-switching asymmetrical PWM DC-DC converter with

Forward-Flyback transformer link." IEEE PESC '96 Record, pp. 100- 105.

[14] Steigenvald, R. L., "A review of sofi-switching techniques in high performance DC

power supplies." IEEE IECOAr '95 Proceedings. pp. 1-7.

[1 51 Pressman_ A. 1.. Switching Poiver Supply Design. McGraw-Hill. 199 1, pp. 42 1-427.

[16] Domb, M., Redl, R., Sokal, N., "Non-dissipative tum off snubber alleviates

swtiching power dissipation, secon breakdown stress, and Vm overshoot: analysis.

design procedure and experimental verification," IEEE PESC '82 Recod pp. 445-

454.

[17] Ninomiya, T., Tanaka, T., Harada, K., "Optimum design of non-dissipative snubber

by evaluation of transistor's switching loss, surge voltage, and surge current," IEEE

PESC '85, pp. 283-290.

El81 Xi, Y., Jain, P. K., Joos, G., "An irnproved gating technique for the synchronous

rectifier MOSFETs in the fomard converter topology?" presented on IEEE

CCECE797.

[ 193 Dixon, L. H., "Control loop cookbook," Unitrode Seminar SEM4 100, 1 994.

[20] Dizon, L. H., "Average current mode controI swtiching power supplies," Uniîrode

Seminar SEM-700, 1990.

[2 11 Kassakian, I. G., Schlecht, M. F., Verghese, G. C., Principles of Power

Electronics, Addison-Wesley, 1 99 1. pp. 368-379.

[22] Chryssis. G., High Frequency Switching P o w r Supplies: theoiy and design. 2nd

ed., McGraw-Hill, 1989. pp. 8-9.

[23] Mohan. N.' Undeland. T.M.. Robbins. W.P.. Power Electronics: Converter,

Applications, and Design. John Wiley & Sons. 1989. pp. 69-74.

THE CONTROL CHlP UC3855

- - INI.ORAT100

k , CIRCUIT.

UNITRODE

High Performance Power Factor Preregulator FEATURES

Coritrds Boost PWM ta Near Unity Power Factor

Fixed ~ r e ~ & n q Average Cunent Mode Control Minimizes Lin8 Current Distorù'on

Buitt-in Actiw3 Snubber (ZVT) âllows Operaiion to SOOkHz. improved EMI and Etiiciency

lnductor Current Synthesizer allows Single Cunent Transformer Current Sense for Impmved Efficiency and Noise m g i n

Acatrate Analog Multiplier with Lin9 Cornpensaor allows for Univerd Input Vdtage Operation

High Bandwidth (~MWZ), Low Offset Current Amplifier

Overvdtage and Overcunent protecu'on

Two M O Threshold Options

150pA Startup Suppiy Current Typical

Precision t % 7.5V Reference

PREUMINARY

DESCRIPTION The UCt 8 5 W provides al1 the control features neçeççary for high power. high frequency PFC bost converters. The average cwrent mode canuol method aflows for stable. low distortion AC Ilne cunerit programrning without the need for slope comperrsation. In addiion. the UC1855 utilizes an active snubbing or M (Zero Vottage Tanri- tion technique) to drarnaticaliy reduce diode reaovery and MOÇFET tum-on losses, resulting in lower €MI emissions and h i g M effidency. Boost converter mvitching frequencies up to 500Wz am m w realiz- able. requiring only an additional SrnaIl MOSFEfI diode, and induclor to resonantly soft switch tbe b o s t diode and switcti. Amrage anent sensing can be employed using a sirnpie resistive shunt œ a curent sense bar&xm8f. Using the cumnt sense transfomer rnelhod, the ifi temal current synthesizer circuit buffers the indudor currenî during the switch on-tirne. and reconstructç the inducbDr arment during the switch off-time. lrnproved signal to noise ratio and negligibie airrent serrsing lbsses make this an attradRR solution for higher power applications.

The UC1855CVB aiso features a single quadrant multiplier, squarer, and divider circuit which provides the programrning signai for the cur- rent lmp. The interna1 multiplier current limit reduces output power during low line conditions. An overvoltage protedion arcuit disables both controller outputs in ttte event of a boost output OV condition.

Low startup supply current. U M O with hysteresis, a 1% 7.5V refer- ence. voltage amplifier with softstart, input supply valtage cîamp, en- able comparator. and overcurrent comparator m p l e t e the Iiçt of features. Àvaitabte packages include: 20 pin N, DW, a, JI and L

BLOCK DlAGRAM

LIcenso Parent tom P l ~ n i a r Mdgnetlca Pin n u m k s reibr 10 DIL-20 J or N packages.

APPENDIX II

SCHEMATICS OF THE PROTOTYPE CONVERTERS

VCC

ION

VREF

VSENSE GND

Vir

20 CA t

33k t- 11560pF I CAO

zvs GTDRIVE

II 56pF

Y

in

3 3k VAOüT 15 4.3k 7

Vsn

3 I ZVDRIVE 17

CT - F --Cr --

1 1 0 0 0 ~ ~ - IN4148 - 1 N393 4 13 - ni in

300pF 1 1 13

ZV5 - 10 i

-

l b II 1 17 SS VSENSE

0

1 lu

- GND uF

1" - Fig. II.2 Prototype forward converter

~ ~ J A P F

16