Microelectronics Journal 41 (2010) 746–751

Contents lists available at ScienceDirect

Microelectronics Journal

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doi:10.1

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E-m

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(E. Stik

journal homepage: www.elsevier.com/locate/mejo

0.8 mW 12-bit SAR ADC sensors interface for RFID applications

Daniela De Venuto a,n, David Tio Castro b, Youri Ponomarev b, Eduard Stikvoort c

a DEE Politecnico di Bari, Italyb NXP Semiconductors, Leuven, Belgiumc Eindhoven, The Netherlands

a r t i c l e i n f o

Article history:

Received 6 October 2009

Received in revised form

26 June 2010

Accepted 30 June 2010

Keywords:

Low power SAR ADC

Ultra-low power latched comparator

RFID application

92/$ - see front matter & 2010 Elsevier Ltd. A

016/j.mejo.2010.06.019

esponding author.

ail addresses: d.devenuto@poliba.it (D. De Ve

nomarev@nxp.com (Y. Ponomarev), eduard.s

voort).

a b s t r a c t

The design and first measuring results of an ultra-low power 12 bit successive-approximation ADC for

autonomous multi-sensor systems are presented. The comparator and the DAC are optmised for low

power consumption. The power consumption is 0.52 mW from a 1.2 V supply with a sample clock of

3.125 kHz and 0.85 mW at 6.25 kHz. This gives 136 pJ per conversion or 66 fJ per conversion step. As per

authors’ knowledge, 66 fJ per conversion step is the best reported so far.

The ADC was realised in the NXP CMOS 0.14 mm technology; the area was 0.35 mm2. Only four

metal layers were used in order to allow 3D integration of the sensors.

& 2010 Elsevier Ltd. All rights reserved.

1. Introduction

In recent years the rapid development of radio frequencyidenification (RFID) technology has resulted in a wide variety ofapplications and devices for identification and tracking. RFIDsystems typically use small, low-cost, battery free devices calledTAGs, which use the radio signal from a specialised RFID reader forpower and communication. When queried, each TAG respondswith a unique identification number by reflecting energy back tothe reader with a technique called backscatter modulation. UsuallyTAGs are application specific, fixed function devices that have anoperating range of 10–50 cm for inductively coupled devices and3–10 m for UHF TAGs. Traditionally, RFID TAGs have been used as areplacement for barcodes in applications such as supply-chainmonitoring, asset management, and building security [1].

A number of investigators have proposed more ambitiousapplications in which the TAG is used as a sensor [2,3].

Specific applications for sensor enhanced RFID TAGs are givenin [4]. The applications include infrastructure and object mon-itoring, automatic product tamper detection, identification ofharmful agents, and biomedical devices for non-invasive mon-itoring. A commercially available RFID tag for monitoring thetemperature of frozen food during transport is described in [4].These products show that the sensor-enhanced TAGs provide

ll rights reserved.

nuto),

tikvoort@kpnplanet.nl

increased functionality. When possible, this will be for the sameprice as today’s TAGs.

At the moment of writing there are several ways for putting asensor in a TAG. Active TAGs use a battery to power thecommunication circuitry, sensors, and microcontroller. They havea range of approximately 30 m and can achieve high data ratesand sensor activity. For reasons of lifetime and volume of thebattery care has to be given to power management.

A block diagram of an RFID sensing platform is shown in Fig. 1.A crucial component in the architecture is the A/D converter. Ithas to receive the different sensor signals, and to provide highresolution with low power consumption [7,8,10].

The successive approximation (SA) algorithm suits well for lowpower, especially when the A/D is used for input signals with abandwidth well below a MHz and 10–12 bit resolution [5,6].

This paper focusses on the design of a 12-bit SAR ADC. Thepower budget is derived from the specifications of the overallarchitecture. The power consumption should be below 1 mW for abit clock of 100 kHz. The implementation has been done in theCMOS 0.14 mm technology of NXP. Starting from the specification apromising solution was found that is based on a recently publishedarchitecture [11–13]. We optimised the electronic circuit for lowdissipation in the case of a (low) bit clock of 50–200 kHz.

The design and the implementation will be discussed in thenext chapters.

2. Ultra-low power SAR ADC architecture

Fig. 2 shows the architecture of the ADC (see also [12]). The‘cold’ side of the comparator is connected to the reference voltage.

Fig. 1. RFID TAG.

SC

Clad Clad2CladSC

bit 0 (msb)

bit 1

bit 2

bit 3

bit 11(lsb)

3 > 8

thermometercoder.

. .

.

SARregisterin

AD_outCberV stab/2

Compa

Fig. 2. Implemented 12 bit SA ADC architecture.

bit0bit1bit2bit3bit4bit5bit6bit7bit8bit9

SCCladnot

comparator gives ‘1’

bit10bit11

Fig. 3. ADC timing diagram.

D. De Venuto et al. / Microelectronics Journal 41 (2010) 746–751 747

The ‘hot’ side is connected to the capacitor bank, the capacitorCber, and the switch for the input signal.

The capacitors of the capacitor bank are connected betweenthe CMOS inverter outputs of the SAR and the input of thecomparator. The ‘cold’ side capacitors are switched by the SAregister (SAR) between the stabilised supply voltage of Vstab andground.

The conversion cycle starts when the signal SC (see Fig. 2) islow and the input switch conducts. At this instant the SAR sets allbits to zero, except the MSB, which is set to one. When thecapacitors of the bank and Cber are loaded SC returns to high andthe input switch opens. With this the voltage that is offered to theA/D is stored as a charge in Cber and the capacitor bank. Thischarge is changed when the SAR changes its state and the ‘cold’side of one of the bit capacitors goes from ground to Vstab or viceversa. The SA algorithm aims at compensation of the charge onCber and the ‘hot’ side of the capacitor bank so that at the end ofthe conversion, voltage at the ‘hot’ side of the comparator isnearest to the reference voltage Vref.

In order to see what happens in the A/D we will follow theconversion in detail. After SC goes up, the comparator output maybe high or low. When it is high, the input voltage is larger than Vref

and charge is subtracted from the comparator input node. This isdone by resetting the MSB. (When the input signal was sampledwith the input switch, the MSB was 1.) Reset of the MSB induces acharge �CMSBVref in the input node of the comparator so that thevoltage in the input of the comparator goes down. When the inputof the comparator is low after SC goes up, the MSB remains 1.

Having granted the value of the MSB, the algorithm starts withthe next bit (bit1, see Fig. 2). The bit was 0 and is set to 1. Thisadds the charge of Cbit1Vref Cbit1 is the capacitance controlled bybit 1 of the SAR. In the case where the comparator output goeshigh, the bit is reset, else the bit remains 1. The same procedureapplies to the succeeding bits. At the end of the conversion thecontent of the SAR is the bit-inverse of the value that representsthe sample.

Implementation of the successive approximation algorithmrelates the reference voltage Vref to the stabilised supply voltageVstab of the CMOS invertors that drive the capacitor bank. Ingeneral, when bit k is set, the voltage in the input of thecomparator changes by DVin:

DVin ¼ VstabCbitk=ðCADþCberÞ ð1Þ

where Cbitk is the bit capacitance of bit k and CAD the sum of thebit capacitances with

CAD ¼ CMSBþCbit1þ � � � þCbit11 ð2Þ

The capacitance Cber determines the input voltage range of theADC. The peak-to-peak input range is given by

Vin, max-Vin, min ¼ VstabCAD=ðCADþCberÞ ð3Þ

In the case where Cber¼0 the input range is rail-to-rail and themid of the range is Vstab/2. In the implemented circuit Cber¼3 pF,CAD¼4 pF, and Vstab is 1.2 V, which gives an input range of0.250–0.950 V.

Fig. 3 shows the timing diagram of the conversion cycle. Asstated above, for each bit, the bit is set, the comparison is made,the register cell is reset and the next register cell is set. All clockand timing signals are generated on chip. The timing is driven by asingle external clock.

The algorithm is implemented with a shift register for thestate, a register for the bits, and a couple of gates. For the ease ofthe design and layout a bit slice architecture was applied.

Fig. 4 shows a simulation of two comparisons. From top tobottom the analogue input, the start conversion pulse (SC, Fig. 3),the ADC output, the comparator output and input are plotted. Thebit-wise increments in the input of the comparator are clear. Thecomparator input goes to the reference voltage.

3. Latched comparator

The comparator is a key component of data converters as it isthe link between the analogue and digital domains. In general,there are the continuous-time (CT) and track-and-latch (TL)comparators. Continuous-time comparators are always ready toreceive an input signal. This makes them sensitive to noise when

Fig. 4. Simulation of two conversion steps.

ref

aa

bbClad

a

b

ΔV+

-

in

Δ t

Fig. 5. Implemented latched comparator.

Fig. 6. Simulation results of the latched comparator.

Fig. 7. Layout of the comparator. The differential pair is at the left and the latches

and inverters are at the right.

D. De Venuto et al. / Microelectronics Journal 41 (2010) 746–751748

the input is near the decision point. In a TL comparator the clocksets the comparator in the latch mode. When tracking, someinternal nodes of the comparator follow the input and the outputis not available. For making a decision, the clock forces thecomparator to the latch mode and usually the input is internallydisabled. The transition of the clock is fast relative to thebandwidth of the input signal and the input signal or noise doesnot cause glitches in the output.

The latched comparator published in [11] consists of twostages. In [11] capacitors were added to the output nodes of thefirst stage. The comparator operates at high speed and withoutbias currrent. In the presented ADC we use a modified version ofthat comparator [12]. Fig. 5 shows the circuit diagram. A flipflopof two NOR gates is driven by the input stage. This simplifies thecircuit with respect to that of [11] and somewhat reduces themaximum clock frequency. Speed is not an issue for theapplication in a TAG and at the rate of 1 MHz the comparatorbehaved perfectly.

One single clock signal is used for driving the comparator sothat the clock-to-clocknot delay is not an issue. The comparisonstarts with the rising edge of the incoming clock. When the clockis low, all nodes of the input differential pair are high and the twoNOR gates have low ouptuts. Caused by the rising input clock theNMOST is switched on and the two PMOSTs are switched off.Nodes a and b (see Fig. 5) go low so that the two NOR gates canoperate as a flipflop. Which one of nodes a or b goes low firstdetermines the final state of the flipflop. Which one of nodes a or

b goes down first is controled by the input voltage of DV. (DV

causes Dt, Fig. 5). Explicit capacitors to nodes a and b proved to besuperfluous in the presented implementation.

The output of the two-NOR-gate flipflop is given to a couple oflatches so that the comparator output does not go down duringthe low phase of the input clock. In the implemented circuit oneof the two ouptuts is given to the SAR and the other one is theoutput of the ADC.

Simulation results of the comparator of Fig. 5 are shown inFig. 6. From top to bottom Fig. 6 shows the clock signal at afrequency of 30 kHz, the analogue input signal, a sine-wave of5 mV and 1 kHz frequency and the comparator outputs. Thesimulated sensitivity is better than 5 mV. This is well below the250 mV needed for the 12 bit ADC.

The layout of the comparator is shown in Fig. 7. The siliconarea is 35 mm�70 mm. In order to avoid mismatch that may causeoffset, the differential pair has a common centroid layout.

The comparator was part of an IC on multi-project wafer(MPW) in the NXP CMOS 0.14 mm technology. The test IC included2 versions of the comparator, connected to one supply pin. Fig. 8shows the measured results. The available test facility limited theoffset test to the addition of DC to the input of the comparator.Fig. 9 shows the measured bias current of the IC as a function ofclock frequency. From the 1.2 V supply the static powerconsumption is 28.2 nW. The power increases proportional toclock frequency at 11.4 nW/kHz; at 100 kHz it is 1170 nW.

Fig. 8. Measured input (red sine-wave) and output (blue square-wave) of one of

the two comparators of the test IC. (For interpretation of the references to color in

this figure legend, the reader is referred to the web version of this article.)

NI OFF 2ndy = 0.0095x + 0.0235

R2 = 0.9262

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 10 20 30 40 50 60 70 80CLK (kHz)

Idd

(uA

)

IddLineare (Idd)

Fig. 9. Measured bias current of the comparator as a function of sample-clock

frequency.

D. De Venuto et al. / Microelectronics Journal 41 (2010) 746–751 749

4. Experimental results of the low power ADC

The ADC was realised at a second test IC. Fig. 10 shows thelayout and pinning of the latter IC. Standard digital I/O moduleswere used. Logic gates and I/O pins were added for testing thedigital circuitry. The total circuit is less than 0.35 mm2 in the NXP0.14 mm CMOS IC process. Four metal layers were used in thedesign of the ADC in order to allow routing on top of circuit.

Special attention has been paid to the layout of the capacitorsof the DAC. As stated above, one plate of the capacitors is directlyconnected to the input of the comparator and the other plate ofeach capacitor is connected to a CMOS invertor output. In order toprevent bit signals coupling to the comparator input, thecapacitors were shielded. In the implementation they werebounded to 3 metal layers for the capacitors and we designed aunit cell capacitor for the array (see Figs. 11 and 12).

An oscilloscope picture of the output bits of the ADC and thestart conversion pulse is shown in Fig. 13. Table 1 gives thecurrent consumption of the digital (Iddd) and the analogue (Idda)parts of the circuit. The analogue part includes the comparatorand its latches as well as the circuit for the reference voltage. Thedigital part consists of the timing module and the SAR. Themeasurements show a current of 0.8 mA at a bit clock of 100 kHz.The measurements revealed an input range of 250–950 mV.

Fig. 14 depicts the reconstructed sine wave and its FFT. Thesecond and the third harmonic were at–68 and �67.5 dBc,respectively. The 0 dB line refers to the maximum DC inputlevel of the A/D.

Fig. 10. Overview of the ADC test IC.

Fig. 11. Layout of the shielded unit capacitive cell of the DAC.

Fig. 13. Measured AD output (red bit-stream) and the sampling clock (blue

pulses). (For interpretation of the references to color in this figure legend, the

reader is referred to the web version of this article.)

Table 1Bias current versus bit clock frequency.

Bit clock (kHz) Idda (nA) Iddd (nA)

12.5 180 110

25 190 150

37.5 210 200

50 220 215

62.5 230 300

75 240 340

87.5 250 390

100 270 440

112.5 280 490

125 290 530

250 410 1000

Fig. 14. Reconstructed sine wave (top) and the FFT (below). Input frequency is

500 Hz.

Fig. 15. Evaluation of the harmonic distortion of a sine wave input of 50 mVpp.

Fig. 12. Layout of the DAC.

D. De Venuto et al. / Microelectronics Journal 41 (2010) 746–751750

Fig. 15 shows the reconstructed sine wave and the spectrumfor an input signal of 50 mVpp; the third harmonic is at �70 dBc.The evaluation of the signal to non-harmonic ratio (SNHR) is of63 dB and the signal to noise and distortion (SINAD) is 60 dB. Thehistogram test (see Fig. 16) is based on a clipped sine wave. Itreveals a DNL of +1.4/�1.0 LSB and an INL of�3LSB, which arealmost the value for an 11 bits convertor. The measurement set-up allowed a maximum number of 2046 samples; the evaluationshave been done when averaging 32 times.

5. Discussion

For the conversion we used a charge redistribution scheme. Bythis, the capacitor array of the ADC is used for storage of the

analogue input sample. After taking the input sample, the chargethat is present at the input node is compensated by adjusting thesetting of the SAR. So we do not store the analogue input value insome hold capacitor and try to imitate that value with the outputof a DAC. We use the SAR just for getting the input charge back tozero.

The algorithm leads to a minimum number of capacitors thatmust be charged and uncharged during the conversion. The sizeand value of the unit capacitor and the thermometer codearrangement were chosen as an optimum with respect to circuitarea and power consumption.

Power consumption scales linearly with sample frequency. It is520 nW at 3.125 kHz and 850 nW at 6.25 kHz, which gives adissipation of 190 nW plus 75.6 nW per KHz of the sample clock.The figure-of-merit (FOM) given in [9] refers to the frequency ofthe conversion steps, which is the clock frequency of thecomparator or the bit clock. When using this FOM with

FOM¼ P=ð2fin2ENOBÞ ð4Þ

Fig. 16. Measured histogram and DNL.

D. De Venuto et al. / Microelectronics Journal 41 (2010) 746–751 751

the presented convertor yields 66.5 fJ per conversion step. Thislow value directly relates to the implemented charge redistribu-tion algorithm and the clocked comparator.

6. Conclusions

A low power ADC for application in sensors and TAGs waspresented. The circuit is implemented in the standard CMOS0.14 mm IC process of NXP and operates with a power supply of1.2 V. The bit clock was designed to be 100 kHz and the samplerate 6.25 kHz. The charge redistribution architecture enabledefficient power management, so that power consumption scaleslinearly with sampling rate.

The low power consumption relates to the supply voltage of1.2 V and low operating frequency. The latched comparator andthe charge redistribution A/D efficiently use the current. As aresult we demonstrated an up-to-date figure-of-merit of 66 fJ perconversion step. The measurements refer to the first silicon andimprovement by redesign is to be expected.

The novelties of the SAR A/D here proposed consist in thecomparator, the charge redistribution operated by the DAC andthe implementation of the capacitors in the layout.

Acknowledgements

This work has been carried out under the framework of an NXPSemiconductors project. The authors want to acknowledge MatSimons of ICLab, NXP, Eindhoven, for his valuable help with thedigital blocks synthesis, and Ibrahim Candan and his colleages ofAMOS, NXP, Eindhoven, for support during the measurements.

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