1/ƒ Noise in Advanced CMOS TransistorsYael Nemirovsky, Dan Corcos, Igor Brouk, Amikam Nemirovsky, and Samir Chaudhry
C omplementary metal-oxide-semiconductor (CMOS) technology is dominant in the microelec-tronics industry for a wide range of applications,
including analog, digital, RF, and sensor systems. The ad-vantages of silicon CMOS technology compared to bipolar technology as well as transistors in other semiconductors is well-established. CMOS technology scaling has been a main drive for continuous progress in the silicon based semicon-ductor industry over the past two decades [1]. The continuous downscaling of CMOS technologies towards nano feature size has increased the performance of integrated circuits considerably. However, one important limitation of MOSFET downscaling is an increase of 1/f noise (often referred to as low-frequency noise), since the 1/f noise increases as the recip-rocal of the device area [2], [3]. Furthermore, the development of nano-sized CMOS technologies has led to the observation of random telegraph signals (RTS) [4] yielding large low frequency current fluctuations. Excessive low-frequency noise introduces serious limitations on the functionality of analog and digital circuits since it deteriorates the noise figure of operational amplifiers and A/D and D/A converters. Low-frequency noise diminishes the signal-to-noise-ratio (SNR) of CMOS sensors, such as IR or CMOS image sensors [5] [6]. The 1/f noise is also of paramount importance in RF circuit applications where it gives rise to phase noise in oscillators or multiplexers [7]. The 1/f noise is a sensitive diagnostic tool to monitor radiation effects on MOSFETs [8].
To predict the impact of 1/f noise on circuit behavior, accurate noise models are required. They must be valid in all operating regimes and easy to implement in circuit simulators, such as SPICE. The physical origin of 1/f noise in MOSFETs, which underlies the models, has been discussed for nearly half a century and has been the subject of much controversy.
This paper is a review of 1/f noise in state-of-the-art advanced MOSFETs, where the channel length has deep submicron or nano-scale dimensions. The origin of 1/f noise, models of 1/f noise, and ways of measuring 1/f noise are briefly reviewed. Experimental results are reported for two different digital and mixed signal “low noise processes”: 0.18 µm and
0.13 µm of TowerJazz and 0.18 µm CMOS-SOI of IBM. These technologies represent well-established advanced MOS (metal oxide semiconductor) technologies. Our goal is to provide practicing engineers with a clear physical picture and useful tools for noise modeling, characterization, and reduction when designing circuits in advanced MOS technologies. We list references mainly from the last decade and the key publications required to follow this review. The reader can trace earlier significant publications from the citations in these papers.
The Physical Model: The Origin of 1/ƒ Noise in MOSFETsAccording to [9] and [10], the physical models are based on two approaches:
◗ Mobility fluctuations: In this model, it is assumed that the observed 1/f noise in the conductance is caused by fluctuations in the mobility of the free carriers in the conducting channel of the MOSFETs. This model was first promoted by F. N. Hooge (see [2] referenced in [9]), and
◗ Carrier number fluctuations: In this model, it is assumed that the 1/f noise is due to generation–recombination (GR) noise in the electron transitions between the conduc-tion band of the channel material and the traps in the oxide layer of the MOS transistor. This is known as the McWhorter model [5] in [10].
The following is a brief review of a revised model for carrier trapping-detrapping 1/f noise, which generalizes the McWhorter model and also exhibits the combined effects of both number and mobility fluctuations [12], [13].
According to McWhorter’s model, trapping and detrapping of electrons occur via tunneling between the conduction states of the channel electrons and the trap states in the oxide layer. The noise spectrum that follows from the McWhorter model obeys a 1/f law if several simplified assumptions are made:
◗ the capture and release processes at different traps are statistically independent,
◗ the tunneling rates, for capture and release of electrons by a trap, are proportional to exp[−x/l], where x is the distance (depth) of the trap from the semiconductor-oxide
interface and l is the tunneling distance in the oxide, typi-cally on the order of 0.1nm,
◗ the spatial distribution of traps in the oxide is uniform, ◗ there is a uniform distribution of activation barriers, Eb. (This is an implicit assumption in the original McWhorter model which is also needed to get a 1/f noise spectrum, as outlined next.)
Physical insights into the microscopic nature of the capture and release processes have been obtained from experimental studies with tiny transistors [14-19]. In these studies, conduc-tance fluctuations in the form of RTS caused by single traps were detected. The dependence of the measured capture and release rates upon temperature indicated that these processes were thermally activated, in addition to the pure tunneling previously assumed by McWhorter. Hence, the additional assumption of uniform distribution of activation barriers Eb discussed above was added.
Furthermore, in the RTS experiments, large variations in the amplitude of the conductance indicated that the channel mobility is also affected by the charging and discharging of single oxide traps. It was assumed that the varying amplitudes are related to the “strategic” location of the trap relative to the fixed interface charge centers. Accordingly, the total relative change in the channel conductance, due to the capture or release event, is equal to the sum of the relative change in the channel mobility and the relative change in the number of mobile channel electrons.
The McWhorter model, although widely accepted, appears to be oversimplified. The revised model of [12], [13] introduces a less restrictive and more general physical picture. The start-ing point, as before, is the capture and release rates (c and e, respectively) for a trap of energy E located at a point r in the oxide and related by:
(1)
where EF is the Fermi level, k is the Boltzmann constant, T is the absolute temperature and g is the degeneracy factor of the trap. The capture rate for the trap is expressed as
(2)
where Eb is the activation energy, and a is a parameter that depends on the density of states, the RMS thermal velocity, the number per unit volume of electrons in the semiconductor, and where σ(E,r) is a cross-section pre-factor.
The spatial distribution of traps on the oxide is not easy to determine, and the oxide layers are likely to be composed of regions with varying levels of disorder. Traps are more likely to be formed at regions of high disorder where the localization is strong. The revised model correlates the density of traps to the localization length, lE(r). The localization length at r is expressed by
(3)
The probability (per unit volume and per unit energy) for a trap in any small volume element in the oxide is inversely pro-portional to the localization length lE(r) therein and is equal to
(4)
where kE is a parameter that may depend on E. Thus, the revised model introduces a new set of less restrictive and more general assumptions that are summarized below.
◗ The revised assumption regarding the capture rate: σ(E,x) is determined by the microscopic details of the oxide layer and may assume any form. In particular, it is not necessar-ily proportional to exp[−x/l].
◗ The revised assumption regarding the spatial resolution: instead of a uniform distribution of traps, it is now assumed that the probability density (per unit volume and per unit energy) of traps in the oxide is inversely proportional to the localization length.
◗ The revised assumption regarding the energy distribution: the normalized distribution (i.e. the probability density) of the activation barriers may assume any form according to the material composition and fabrication process.
The spectrum of the noise generated by the traps follows “1/f” behavior even with the above set of assumptions. The starting point is the spectrum of a random telegraph signal, which has a Lorentzian shape:
(5)
The spectrum corresponding to the noise caused by all the traps in the oxide can be obtained by integrating (5) over the range of energies, E, the range of degeneracy factors, g, and over the volume, V, of the oxide layer. [12] has a calculation of the spectrum of the fluctuations in the current caused by car-rier number fluctuations as well as the spectrum of the noise caused by the combined noise that accounts for both carrier number and mobility fluctuations.
It shows that the spectrum is inversely proportional to 1/ multiplied by an expression that is the difference of two arctan functions. These functions contain all the model parameters as well as . Because of the nature of the arctan function, the effect of upon the function is small. Hence, a close 1/f behavior is observed, where 0.8<<1.2 for several decades of frequencies in the relevant range of 10-3 to 105 Hz. The arctan functions also provide the right behavior at the lower frequency forcing the spectrum to level to a fixed value instead of increasing to infin-ity if the spectrum were to be determined only by 1/.
Based on the assumptions above, the often cited SN'ot - the power spectral density (PSD) of the fluctuations in the number of occupied traps N'ot - is better understood. It is expressed by the highly simplified formula
(6)
where LW is the gate area and Not [cm-2] is the equivalent den-sity of oxide traps per unit area. Evidently, Not is determined by
Table 1— 1/ƒ noise models for the three main regions assuming long channel approximation and = 1
Operation Region and Gate Transconductance, gm
PSD of Input-referred Noise, SVg(f )
PSD of Drain Current Noise, SId(f ) = gm
2 SVg (f )
Saturation
Linear Range
Subthreshold
Notes Significant reduction of noise at subthreshold
SId(f ) follows Id in saturation and I 2d in
the linear and subthreshold regions
all the model parameters and the correcting factors “hidden” in the arctan functions expressing the actual spatial and energy distribution of the traps.
The Long-Channel Transistor Noise ModelOur methodology in [20], [21] is based on first modeling 1/f noise in MOS transistors with long-channels. We follow the well-established approach that a simple current-voltage
characteristic is useful for understanding the basic operation of the MOSFET as a circuit element. This simplified first-order model, known as the “long-channel model”, is used to obtain approximate “hand-made” circuit designs. Transistors following this model are characterized by “long chan-nels” and “well-behaved” current-voltage character-istics from subthreshold to saturation. Such transistors exhibit distinctly smaller lateral fields compared with the vertical fields, and their performance follows well-defined assumptions. As indicated in [7], the promi-nence of “short channel” effects depends on the ratio of (VGS–Vt)/L to Esat, where
Esat is the field strength at which the carrier velocity has dropped to half the value extrapolated from low-field mobility (about 4 ·106V/m). If this ratio is small, then the device still behaves as a long device; the actual channel length is irrelevant. The required channel length and chan-nel width for a given technology is also defined in [22]. In such transistors, additional effects, which are not included in the model, have negligible effect on the current-voltage characteristics.
Fig.1. Measured gate transconductance, gm, as a function of gate-source voltage, VGS, for transistors fabricated using 0.18 µm ([email protected] for NMOS and [email protected] for PMOS) and 0.13 µm ([email protected] for NMOS and [email protected] for PMOS) TowerJazz process, with the minimal L determined by the technology. VDS is determined by VDD and the transistors are biased from subthreshold to saturation.
Table 1 summarizes the 1/f noise models which are substantiated experimentally in a limited gate and drain bias region where the mobility is practically constant (in the fol-lowing section on “1/f Noise Measurements”). In addition, the transistors which follow experimentally the models of Table 1 are designed with ad-equate W and L and operated in a limited bias region and hence may still be modeled by the long channel approxima-tion, even in advanced CMOS technology.
The Short-Channel Transistor Noise SimulationsTo simulate the operation of a MOSFET circuit, a simulator requires a mathematical model to represent the characteristics of the device [23]. The physi-cal model that we derived, together with the physical insight provided by the Long-Channel Transistor Noise Model section, while essential for the design process, is a simplified, first-order model, which is adequate for transistors with relatively long channels, follow-ing the “long channel” approximations.
The characteristics of transistors with short channels are determined by several physical effects which are not included in the “first order” equations. Hence, more elaborate models, which account for short-channel effects, are required to accurately predict the performance of the circuit. Such models are devel-oped by combining empirical data with the physical laws and are essential for simulating the low frequency noise of advanced CMOS transistors. The most widely used is the Berkeley Short-channel IGFET Model (BSIM) [23], [24].
A circuit simulator such as SPICE (Simulation Program with Integrated Circuit Emphasis) is extremely valuable at the later stage of the design process to help in design optimi-zation. It provides an independent verification of operation and enables parameter optimization. The SPICE simulator uses the SPICE parameters supplied by the semiconductor company chosen for the fabrication of the chip, which are used by the device model (e.g. BSIM4). The SPICE simulator is the mathematical engine of SPICE while the SPICE model
mathematically represents the physical laws governing the device characteristics under various bias conditions. BSIM is often referred to as level 4 while BSIM3 is a level 7 and BSIM4 a level 8 model. This particular model places less emphasis on the exact physical formulation of the device, but instead relies on empirical fitting of parameters and polynomial equations to handle various physical effects. This approach is favored because it is computationally faster
than relying on more complex implicit equation sets. BSIM3 adopts a single equation to de-scribe device characteristics in various operating regions (see [13] as quoted in [23]). BSIM3 has evolved through three versions with minor modi-fications, the latest of which known as BSIM3v3 (see [15] as quoted in [23]). The newest addition to the BSIM family is
BSIM4. It was made public in the year 2000 and is known as a level 14 model; it offers improved noise modeling. BSIM4 is used successfully in 0.18 µm technologies. The manuals, codes and news about BSIM3 and 4 can be found in [24]. An-other device model, PSP [25], is being jointly developed by NXP and the Arizona State University and is considered the new standard for advanced device modeling. As opposed to BSIM, it is a surface-potential based model which allows simulating the short-channel and second-order effects with
Fig. 2. Measured drain current noise PSD, SId, as a function of frequency for a PMOS transistor (16x2.5µm/0.3µm) fabricated with the 0.18 µm TowerJazz process operating at strong inversion. The slope follows 1/fβ with 0.8<β<1.2 for four decades. (The graph was plotted using MATLAB.)
A circuit simulator such as SPICE (Simulation Program with Integrated Circuit Emphasis) is extremely valuable at the later stage of the design process to help in design optimization.
higher accuracy and it uses a truly continuous expression, valid across all bias regimes, without employing special “glueing” or smoothing functions.
Next, we discuss the models implemented on the latest publicly available version of BSIM4 (v4.6.4) in virtue of its wide spread use in commercial software applications. BSIM4 also provides the two flicker noise models available in BSIM3, although the smoothing functions implemented in them underwent significant revisions. The TowerJazz processes characterized in this work are modeled with BSIM3 for the 0.18 µm node and PSP [25] in the 0.13 µm node; IBM uses BSIM4 as a device model for its 0.18 µm process.
BSIM4In BSIM, the 1/f noise sources are described by a single equation which has been made continuous along the three operation regions: subthreshold (weak inversion), saturation
and linear (ohmic). A flag, which is selected by the semicon-ductor companies and supplied together with the other device parameters, determines which of two modes will be employed for the simulation. The first mode, or fnoiMod 0, is simpler and easy for hand calculations. It requires computing the following expression, known as SPICE2-Flicker noise:
(7)
where KF is a technological parameter, Coxe is the effective oxide capacitance, the EF (noise power dependence on fre-quency) and AF (noise power dependence on current) powers are supplied with the other device parameters. For the 0.18 µm technology, KF in NMOS is on the order of 10-27[A·F] while in PMOS KF is slightly smaller. KF depends critically on process-ing. AF has a default value of 1 although the extracted value for a process may differ significantly. EF is usually close to 1, with values generally ranging from 0.8 to 1.2.
Expression (7) corresponds to the model of long channel transistors in strong inversion (Table 1) provided that KF = q2Not, Coxe @ Cox and AF =1. In practice, Not for NMOS and PMOS increases with gate voltage. Thus, the SPICE “flicker noise coefficient” is actually voltage dependent, whereas the SPICE model fnoiMod 0 does not include such dependency.
The fnoiMod 1 model, or BSIM-Flicker noise model, provides better accuracy than the SPICE2-Flicker noise model, but a great number of measurements is required to extract all the model parameters.
This model takes into account both number and mobility fluctuations, as well as their correlation, and it uses two differ-ent expressions for strong inversion and subthreshold:
(8)
(9)
where Ids is the drain current, Weff, Leff and eff the effective chan-nel width, length and mobility, LINTNOI is an offset in the channel length modulation (CLM) calculation, Coxe is the effec-tive oxide capacitance, EF is the frequency exponent, ∆Lclm is the length reduction due to CLM, and Abulk is used to model the bulk charge effect; F is a function of the three noise parameters NOIx and the charge densities Ny
z in the different regions of the transistor. The transition between the two regions is made smoother by summing the reciprocal of the two formulas and then computing the reciprocal of this sum.
1/ƒ Noise Measurements
Experimental Setup While designing a circuit which is to be fabricated in a given technology, it is essential to choose a suitable 1/f noise model,
Fig. 3. (a) Measured drain current noise PSD, SId, at 1 Hz as a function of the mean drain current, IDS, of two transistors: an NMOS (1x5µm/0.5µm, [email protected]) and a PMOS transistor (100x0.5µm/0.5µm, [email protected]) fabricated with IBM’s SOI 0.18 µm process. SId follows Id
2 at subthreshold and Id at saturation as predicted. (See Table 1.) W=5 µm and L=0.5 µm are well above the Lmin=0.18 µm. The 1/ƒ noise behavior is not specific to CMOS-SOI and represents regular CMOS as well. The PMOS transistor, which has lower mobility, exhibits less noise as predicted. (See Table 1.) (b) Input-referred noise voltage PSD, SVg, as a function of gate-source voltage, VGS, applied to the transistors of Fig. 3a. At subthreshold (for |VGS|<|VT|@0.3V), the noise reduction is significant. The 1/ƒ noise behavior is not specific to CMOS-SOI and represents regular CMOS as well. The PMOS transistor, with its larger gate area, exhibits less noise as predicted. (See Table 1.)
reviewed in the previous sections. Noise measure-ments are time consuming and require precise control of the DC parameters of the transistors. An experimental setup which allows automatic measurement of drain current noise for different gate-source and drain-source voltage is described extensively in [20] and [26]. The gate-source voltage is controlled from the PC by a D/A converter. A transimpedance preampli-fier is used to read the drain current noise. DC coupling allows biasing the transistor drain from the preamplifier input. The gate voltage is also controlled from the PC. The dynamic signal analyzer (DSA) performs sampling, computes the Fast Fourier Transform (FFT) of the in-coming signal and calculates the density spectrum at the frequency of interest. With this experimental set-up, the drain current Power Spec-tral Density (PSD) is directly measured by the DSA. The input-referred noise is ob-tained by dividing by the square of the measured gate transconductance at each data point. The fact that the gate transconductance is mea-sured rather than calculated is crucial to minimize errors in the noise data.
MOS Technology Under StudyThe present paper focuses on CMOS transistors for analog applications which are fabricated in two different “low noise processes”: the TowerJazz (formerly Tower Semiconductors) 0.18 µm and 0.13 µm [27] as well as the IBM 0.18 µm CMOS-SOI [28]. These technologies represent well-established advanced digital CMOS along with analog components such as resistors, MIM capacitors, inductors, and deep nwells for isolation of noise-sensitive portions of the chip.
The TowerJazz process [27] is based on p-type silicon (1.5 ohm·cm) epitaxial wafers, where twin wells (n-well and p-well) are formed in an STI process with subsequent ion implantation. Gate oxide is grown by dry oxidation; its ellipsometric (physical) thickness is 3 nm and 2.2 nm, for the
Fig. 4. The SPICE technology parameter “KF” as a function of the gate overdrive (VGS-VT) applied to transistors fabricated using the IBM 0.18 µm CMOS-SOI, TowerJazz 0.18 µm, and TowerJazz 0.13 µm processes. As expected, larger transistors exhibit less spread in KF. The spread of data points belonging to the same transistor and measured at the same gate overdrive is due to increased VDS.
Fig. 5. The impact of downscaling on 1/ƒ noise. The normalized noise input-referred power spectral density is shown as a function of technology generation. The points below 100nm are taken from the ITRS roadmaps for 1/ƒ noise. The points at 130nm and above are based on measurements performed by the authors. The figure of merit is the area normalized input-referred spectral noise density, Area×SVg(f). It is normalized to 1Hz frequency and 1µm2 area. The effective gate overdrive voltage VGS-Vt is 0.2 V and VDS=VDD/2 for the most recent ITRS data. (The graph was plotted using MATLAB.)
0.18 µm process and 0.13 µm process, respectively. Cobalt silicide is formed over the polysilicon gate and source/drain regions. Aluminum lines provide the metallization in the 0.18 µm process while a copper based metallization is used in the 0.13 µm process. The IBM CMOS-SOI process offers two op-tions for gate oxide (thicker 5.2 nm; thinner 2.2 nm) and here we focus on the thinner oxide.
Measurement Methodology and Experimental ResultsMeasured data often appears confusing unless a systematic and methodological approach is adopted. It is essential to system-atically measure 1/f noise of representative transistors, with W and L well above the technology minimum gate length (Lmin), as a function of VGS , with VDS as a parameter, as outlined below.
The first step is to plot gm vs. VGS , as Fig. 1 shows. The measured transconductance is an important parameter in measuring the low frequency noise of MOSFETs since SId (ƒ)= g2
mSVg (ƒ) and hence it converts the directly measured PSD of drain current noise into the input-referred noise voltage. Furthermore, the measured transconductance also indicates the range of drain and gate bias voltages corresponding to a practically constant channel mobility. We have observed experimentally that the 1/f noise measurements exhibit a bet-ter fit to the models of Table 1 provided the gate and drain bias voltages are limited to the range where the channel mobility is practically constant. This makes sense since reduced mobility indicates that there is either a large normal electric field or significant self-heating and large parasitic source and drain resistors. As discussed in the “Long-Channel Transistor Noise Model” section, the ratio of (VGS–Vt)/L to Esat= 4 ·106V/m is a good guideline, indicating that for 0.18 µm and 0.13 µm technology, VGS–Vt should be limited to ~0.7V and ~0.5V, respectively.
The second step is to measure noise spectra as Fig. 2 shows. A well behaved 1/f noise spectrum is indicated by a slope of 1/f with 0.8<<1.2 for several decades.
The third step requires measuring the dependence of the power spectral density of the drain current on the mean drain current, as Fig. 3a shows and the PSD of the input-referred noise voltage as a function of VGS, as Fig. 3b shows. The general behavior corresponds to the predictions of the modeling of Table 1 provided that W and L are well above Lmin and the gate and drain bias voltages are limited to the region of constant mobility and where short channel effects are minimal. In the subthreshold regime, the noise is significantly reduced, as Fig. 3b shows. It is evident from Fig. 3 that the 1/f noise behavior of the CMOS-SOI is similar to regular CMOS.
Finally, from the measured noise data of relatively large-area transistors with L>Lmin and W/L >10 operating at the right voltages to reduce short channel effects, the SPICE technology parameter, KF, is extracted and is used to characterize the
noise performance of the technology as well as the sample-to-sample variations in noise performance, as Fig. 4 shows. Thus, the extraction of KF based on the above methodology is very useful for monitoring the noise performance of daily runs in fabrication facilities.
How to Benefit from Scaling Fig. 5 shows the impact of scaling, following ITRS 2009 [29] roadmap predictions, given only for N-MOSTs and using area normalized input-referred spectral noise density. SVg( f ) is calculated following the SPICE model and the predictions of Table 1. The ITRS data is normalized to active device area W × L = 1 µm2 and frequency = 1Hz. Fig. 5 also shows measured data points from [20], [21], and [30] which follow the roadmap. As expected, the Area × SVg( f ) values scale with the square of the oxide thickness and the normalized 1/f noise is reduced with the scaling down of technology in terms of reduced oxide thickness. Downscaling of the physical oxide thickness is in practice limited by the gate leakage current and hence below 0.13 µm technology. No noise reduction is expected with downscaling, as long as the gate oxide is based on dry oxida-tion and is of the order of 3 nm.
In summary, downscaling reduces the SPICE technological parameter, KF, which characterizes the 1/f noise power, pro-vided the oxide thickness is reduced and the gate area of the designed transistors is relatively large (W × L of the order of
a few square microns). The 1/f noise behavior of the CMOS-SOI under study is similar to regular CMOS, in contrast to the results in [31] and [32]. In applications where the area re-quirement cannot be met, large variations in the observed 1/f
noise of different samples are expected. In such cases the de-signer must rely on circuit approaches like correlated double sampling for noise reduction [33].
ConclusionsTo reduce the 1/f noise, transistors with L > Lmin are recom-mended. The sample-to-sample 1/f noise level spread of larger area devices (W × L larger than a few µm2) is small (within a factor of 3) while smaller area transistors exhibit large spread in the measured 1/f noise (over one order of magnitude).
In analog applications, it is very important to limit the applied saturation gate and drain voltages to values where the decrease in channel mobility is very small. When comparing different technologies, care should be given to data measured at the same bias conditions (VGS–Vt,VDS) and to restrict the longitudinal fields to (VGS–Vt)/L < Esat= 4 ·106V/m.
Acknowledgments:The Technion team highly appreciates the contribution of Ned Cahoon, Manager of IBM Foundry Marketing and Business Development, who provided the IBM samples.
The fact that the gate transconductance is measured
rather than calculated is crucial to minimize errors in the noise data.
[30] I. Brouk and Y. Nemirovsky, “Noise characterization of the 0.35 µm
CMOS analog process implemented in regular and SOI wafers”, in
Proc. 11th IEEE ICECS, pp. 171-174, Tel Aviv, Israel, Dec. 2004.
[31] J. Jomaah and F. Balestra, “Low-frequency noise in advanced
CMOS/SOI devices”, in IEE Proc. Circuits, Devices and Systems, vol.
151, no. 2, pp. 111-117, 2004.
[32] E. Simoen, A. Mercha, C. Claeys, and N. Lukyanchikova, “Low-
frequency noise in silicon-on-insulator devices and technologies”,
Solid-State Electronics, vol. 51, no. 1, pp. 16-37, 2007.
[33] E. A. M. Klumperink, S. L. J. Gierkink, A. P. van der Wel, and B.
Nauta, “Reducing MOSFET 1/f noise and power consumption by
switched biasing”, IEEE Journal of Solid State Circuits, vol. 35, no. 7,
pp. 994-1001, 2000.
Associate Prof. Yael Nemirovsky ([email protected]) (IEEE Fellow, IEE Fellow) has been a member of the Faculty of Electrical Engineering at Technion-Israel Institute of Technology since 1980. Her research interests are micro/nanoelectronics, electro-optics, MEMS/NEMS and CMOS-SOI MEMS imagers.
Dan Corcos received his B.Sc. degree in electrical engineer-ing from Politecnico di Milano (Italy) in 2008, and he is currently pursuing his Master’s degree at Technion-Israel Institute of Technology (Haifa, Israel). His current field of
For additional information and technical details, see our sister publication, the IEEE Transactions on Instrumentation and Measurement.
Chun-Yu Chen, Chieh-Hsiun Kuan, “Design and calibration of a noise measurement system”, IEEE Trans. on Instrum. and Meas., vol. 49, no. 1, pp. 77-82, 2000.
R. Saletti, B. Neri, “Low-noise automated measurement system for low-frequency current fluctuations in thin-oxide silicon structures”, IEEE Trans. on Instrum. and Meas., vol. 41, no. 1, pp. 123-127, 1992.
interest is THz detectors, as well as analog CMOS design and MEMS.
Dr. Igor Brouk received the electronic engineer degree (with honors) from the Moscow Institute of Aircraft Technology, in 1990, the M.Sc. degree in electrical engineering and the Ph.D. degree from the Technion—Israel Institute of Technology, Haifa, Israel, in 2000 and 2005, respectively. His research in-terests include CMOS photodiodes, image sensors, low noise analog readout, ion-sensitive FETs (ISFETs), RF, and analog electronics in VLSI.
Dr. Amikam Nemirovsky (B.Sc., M.Sc., D.Sc., Department of Electrical Engineering at the Technion—Israel Institute
of Technology) is currently adjunct associate professor with Dept. of EE, Kinneret College, Jordan Valley, Israel. He is interested in systems and noise analysis.
Dr. Samir Chaudhry is the Director of Design Enablement at TowerJazz, a pure-play specialty foundry. His research interests include RF CMOS and statistical modeling. Prior to joining TowerJazz, he was a Distinguished Member of Technical Staff with Bell Labs where he worked on Technology CAD and device modeling for scaled silicon technologies. Dr. Chaudhry received his PhD in Electrical Engineering from the University of Florida. He has authored over 25 publications in peer-reviewed journals and conferences and has 19 patents in the field of silicon technology.
