IEEE Transactions on Nuclear Science, Vol. NS-34, No. 6, December 1987
AN SEU TOLERANT MEMORY CELL DERIVED FROM FUNDAMENTAL STUDIES OF SEU MECHANISMS IN SRAM
H. T. Weaver, C. L. Axness, J. D. McBrayer, J. S. Browning, J. S. Fu, A. Ochoa1, Jr., R. Koga2Sandia National Laboratories, Division 1141, Albuquerque, New Mexico 87185
Abstract
A new single event upset (SEU) hardening concept,an LRAM cell, is demonstrated theoretically and ex-perimentally. Decoupling resistors in the LRAM areused only to protect against the short n-channeltransient; longer persisting pulses are reduced inmagnitude by a voltage divider, a basically new con-cept for SEU protection. In such a design, smallerresistors provide SEU tolerance, allowing higherperformance, hardened memories. As basis for the LRAMidea, techniques were developed to measure time con-stants for ion induced voltage transients inconventional static random access memories, SRAM.Time constants of 0.8 and 6.3 nsec were measured fortransients following strikes at the n- and p-channeldrains, respectively--primary areas of SEU sen-sitivity. These data are the first transient timemeasurements on full memory chips and the large dif-ference is fundamental to the LRAM concept. Teststructures of the new design exhibit equivalent SEUtolerance with resistors 5-to-10 times smaller thancurrently used in SRAM. Our advanced transport-plus-circuit numerical simulations of the SEU processpredicted this result and account for the LRAM experi-ments, as well as a variety of experiments onconventional SRAM.
Introduction
Single event upset (SEU) or soft error can occurin static random access memories (SRAM) following ahigh energy ion strike on the integrated circuit [11.Photocurrent from the strike is collected at sensitivenodes, changing the node voltage and essentially"writing" the memory cell. The magnitude and durationof the voltage transients are critical for determiningwhether or not SEU occurs. These transients aremodulated by circuit loading at the information node[2]. The rather complicated time dependence of thecircuit load and its effect on photocurrent must beaddressed in order to physically describe the SEUprocess.
Studies of charge transport and photocollectionin memory circuits, processes fundamental to SEU, haveresulted in a new memory cell design (LRAM) thatallows much smaller resistors for SEU immunity thancurrently used in conventional SRAM. Central to theLRAM concept is that ion strikes at different loca-tions within the memory cell produce very differentelectrical responses from the circuit. We found sucha difference for conventional SRAM in numerical models[3,4] and have now directly confirmed it through aseries of experiments. Our models, supported by thisrecent SRAM data, predict advantage for the LRAM andtest structures that include the new concept exhibithardening with low resistor values.
We report work in four areas. First, we havedeveloped and executed experiments that measure timeconstants for voltage transients following ion strikes
at the "off" n- and p-channel drains in SRAM, twoprimary areas of SEU sensitivity. Second, we findthat a single parameter accounts for 3D effects of thestrike and allows the model to correctly predict theSRAM response to a variety of ion strikes. Third, ano fre parameter projection is made for the charac-teristics of a novel memory cell, LRAM, that employs anew hardness concept. And fourth, the response tohigh energy ions of test structures employing the newconcept is compared to our simulations.
Experiments on SRAMThe SRAM with decoupling or feedback resistors
(RF) is illustrated by Fig. 1. Our memory is a 2pmfeature, 5V, p-well, 16 k-bit, CMOS memory fabricatedat Sandia National Labs. The experiments consist ofexposing SRAM with different decoupling resistors, RF,to ion beams of 90 MeV Cl, 220 MeV Fe, 180 MeV Ge, 200MeV I, and 360 MeV Au. The beams were generated bythe tandum Van de Graaff at Brookhaven or by thecyclotron at Berkeley. The ratio of number of upsets-to-fluence defines the SEU cross section for a set ofexperimental parameters. An example of these data isshown in Fig. 2 where cross section versus ion linearenergy transfer (LET) is shown for two SRAM withdifferent RF. We are primarily interested in two
experimental parameters; (1) the threshold LET for
TIMTE TIME Tr
Figure 1 Schematic of static memory (SRAM) showingfeedback or decoupling resistors (RF). Voltage tran-sients are illustrated for a strike on the "off" p-channel transistor drain. The transient on the leftor struck inverter information node represents thecase where the cell recovers from the strike. Thetransient on the right or unstruck inverter representsthe case where SEU occurs.
*This work performed at Sandia National Laboratories was supported by the Air Force Space Technology Center andthe Army Ballistic Missile Defense Systems Command under contract BMD SA-5-D1229-02-S08D, also USASDC W31ROD-63-D145 and W31RPD-7S-4077, DNA IACRO86-887 and the U. S. Department of Energy under contract DE-ACO4-76DPOO789.A. Ochoa is with Hughes Research, Carlsbad, CA 92008. 2R. Koga is with Aerospace Corporation, Los Angeles, CA90009.
Figure 2 Experimental SEU cross secticlinear energy transfer (LET) for two SRAMseveral ions as indicated. The lines are fdata. Also shown are the p-channel transarea A and the sum of p- and n-channel d
(An + A ). The threshold LET for n-drain
uncertain, but occurs in the LET range deincreasing from Ap to An + Ap We indicate
by Lc(n) shown on the figure. A "cut" is
along which we obtaino as a function of
shown and addition curves not shown. Th
plot determines the critical resistor forn-drain upsets.
SEU, which we define as the LET at whic
section exceeds 1E-5 cm 2 and (2) the va
cross section in flat response regionshigh LET.
A physical picture that relates the cr
data to circuit response transients is deveFig. 1. We have illustrated on the left s
figure the voltage response to a heavy ion
the drain of the "off" p-channel transivoltage rises until the drain-substrate dieforward biased, clipping the signal. M
strikes considered are of sufficient sizethis signature. Since the amplitude is efflimited by the diode clipping, increasingincreases the width of the pulse. H
recovery time, TR' as that required for the
return to the approximate switch point of t(we will use 2.5 V as this value). Physica
measure of the time needed for the circsipate the ionization charge from the strikillustration, the information node ofinverter returns to its original voltage, r
circuit recovery without soft error.
On the right side of Fig. 1 we illresponse of the unstruck inverter informIn this case SEU occurs since the node volt
permanent change from its original v
response time, TF' is defined as that requi
node to reach the defined switch point (aguse 2.5 V). For the large LET strikessideration, is primarily determined by t
RF (TF = RFC, where C is the node capacitar
For a given memory cell, the responseintrinsic property. We associate this res
withTF, a quantity we can estimate using known resis-tances and capacitances. Circuit recovery timedepends on the ion LET. We associate recovery timeIAn4Ap with -R which is not directly measureable. However,
we can varyTR by changing the strike LET, a property
wye exploit as follows. SEU will occur following astrike if the circuit responds quicker than itr'ecovers. By our definitions this situation isdescribed byTF <TR; no SEU is observed forTF >TR.Fundamental to our experimental interpretation isthat,TR = TF at SEU threshold, that is, the LET value
that first produces SEU. Thus, by measuring the LETthreshold for a given RF, we are able to estimate the
recovery time(TR= 'F = RFC) for that LET. Note that
rns versus bothRF and C are known from processing data. We find
[exposed to C = 0.03 pF for our circuits. There is some ar-its to the bitrariness in our exact definitions, but we find good
zistor drain agreement for upset-nonupset conditions between fullrain areas simulations and experiments using these rather simple
.strikes is concepts.
efined by a We can now interpret the shape of the curves inthat range Fig. 2 in terms of the timing parameters TR and TF.also shown The rapid cross section increase signals the thresholdRF for data LET and, with our definitions, this occurs whenTR =eFavs. RF TF. The cross section continues increasing to a valuele a vs. RF F
preventing equal to the sensitive area, an area that responds toa strike with a recovery time larger thanTF* At low
LET, the transient response reflects one photocollec-tion mechanism (in our case associated with the p-drain hit since the shoulder in Fig. 2 is about equal
h the cross to the p-drain area), but as the LET increases,recovery times associated with other mechanisms also
olue of the increase, ultimately to the point that TF is exceeded
for a second mechanism. This second mechanism isexhibited in the RF = 130a data of Fig. 2. This is
'oss section essentially zero resistance in our considerations. At'loped using this second threshold LET (in our case the n-drainide of this hit) the cross section increases to a value equal toi strike on the sum of the two sensitive areas. We indicate instor. The Fig. 2 the approximate onset of n-drain sensitivity byde becomes the range labled L (n).[ost of the cto produce'ectively It is important to realize that although p- andLET simply n-drain areas are SEU sensitive, the recovery timesle define a for the two strikes are not the same. Flat regions!signal to for cross section data simply reflect the condition
he inverter that recovery times exceed TF* This is graphicallyIlly rR is a illustrated by the RF = 73Kn curve of Fig. 2 where the
uit to dis- cross section only reaches the p-drain area. Thus,:e. In the the recovery time for the n-drain strike is alwaysthe struck less than TF for 73 Kfl (2.1 nsec) but the p-drain-epresenting strike recovery time exceeds 2.1 nsec. Since our
effective LET reach very large values, we are facedwith the striking implication that the n-drain
.ustrate a recovery time never exceeds the decoupling time as-nation node. sociated with 73 KO, that is a saturation effectsage shows a occurs.value. Thered for the A better estimate for the maximum or saturated
,ain we will recovery time for an n-drain strike is made using aunder con- procedure illustrated by the "cut" in Fig. 2. Thehe value of figure shows that for some RF between 0 and 73 Kn the
ice). maximum cross section will change from the sum of thedrain areas to that of the p-drain alone. Thus, by
time is an measuring a series of SRAM with resistors in this------ -'__ range, at a sufficiently high LET (= 0.8 pC/pm) tospulwe UJ.me)IJUILORV U.LIIIC
1283
insure that the flat response region has beenachieved, we can isolate the critical resistor. Weshow this result in Table I and indicate on Fig. 3 thesame result as a cross-hatched area at about LET = 0.8pC/Pm.
Increasing RF eventually leads to total elimina-
tion of SEU, which for resistors above about 30 KQ isprimarily due to p-drain strikes. We show in Fig. 3 aseries of critical resistors as a function of LET.The critical resistor is defined as that required toeliminate SEU at the given LET or alternatively, thatrequired to produce LET threshold. Saturation be-havior is very evident here for p-drain strikes. Thisresult is also listed in Table I. Note that there isa significant difference in the saturation recoverytimes for an n- and p-drain strike. This differenceprovides a critical test for any simulation. We foundthe experimental accessibility of this detailed infor-mation quite surprising.
In the above discussion we tacitly implied thatthere are only two SEU sensitive areas in the SRAM.The data support this conclusion. However, oursimulations indicate that the gate areas are sensi-tive. The problem experimentally is that the gateareas are much smaller than the drain, approximately15% of the n-drain area. Normal scatter in the dataand the somewhat imprecise definition of the sensitiveareas, obscure any experimental evidence of gatesensitivity. We will return to this point when con-sidering the LRAM.
Simulations for SRAM
Our model consists of simultaneous solution ofthe five charge transport equations within a twodimensional plane, represented as the front of thetransistor structure in Fig. 4. These solutions areaccomplished iteratively in four silicon slabs,defined by diffusions profiles, and connected electri-cally as indicated in Fig. 1 or 5. The electricalconnections provide time dependent boundary conditionsfor each silicon slab [51. All transistor parameters(field and doping dependent mobilities, lifetimes,etc.) are taken from the literature and dopingprofiles from data on the technology for the
SRAM. The difficult parameterization involves thestrike itself, illustrated in Fig. 4. For the realcase, a cylinder of charge is generated with very highcharge densities, whereas in simulation, charge isdistributed over the slab shown. The transistor widthis fixed at a relatively large value by the technologyand cannot be changed without changing the transistordrive current. Thus, the "volume" containing theinitial charge, obtained from published LET tables[6], is much larger in simulation than in actuality,yielding an initial charge density that is much toosmall.
We note that this is a fundanental 2D-3Dnot an artifact of our methodology [3,7].consequences are unknown generally, but aeffect is the reduction of recombination
problem,Its fullprimaryrates
2D/3D EFFECT IN ION STRIKE SIMULATION
Figure 4 Schematic representing a transistor struckby a high energy ion. The cylinder represents theactual case, but the simulation requires the slab forintroduction of the strike generated charge. Thewidth (W) of the transistor is fixed in the simulationrequiring that the slab volume is much larger than thecylinder volume. Differential equations are solvedonly in the front plane, leading to a 2D-3D effectthat must be corrected for in the simulations.
"L" CELL
I4TR(nle.c)
Figure 3 Plot of the critical values of RF in Fig. 1,
defined as the resistor that barely prevents SEU forthe given LET, versus LET for a series of SRAM. Datais shown for the p- and n-drain strikes. The n-draindata are taken from Fig. 2 (see L c(n) near the RF = 0curve) and from data that fall along the "cut" in thatfigure (cross-hatched region near LET = 0.8 pC/um).Simulation results are also shown as solid lines withthe single point used to calibrate the model for 2D-3Deffects indicated.
I=
Figure 5 Schematic of the LRAM memory cell. Two setsof resistors are used, one set (RF) resistivelydecouples the two inverters and protects againststrikes on the n-channel transistors while the secondset (RL) form a voltage divider with the "on" n-channel transistor to limit the voltage amplitude atthe information nodes (1 and 2) to values below theswitch point. Our experiments used cells for which RF= RL.
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immediately following the strike [8]. It is thiseffect that we address in our parameterization method.A convenient procedure is to scale the Auger recom-bination coefficient to give the "correct" initialrecombination rate. The Auger mechanism is dominant
[81 for large carrier densities (> 1E19 cm3), butfalls below Schockley-Read-Hall (SRH) rates at lowinjection levels. Thus, by increasing the Auger ratewe only affect mechanisms at early times in the tran-sient simulation, the period most seriously affectedby the 2D-3D phenomenon.
This approach was used in our early work [31, butno good method for selecting the Auger enhancementfactor was available, particularly since the dimen-sions of the strike are not precisely known. Thisleads to large uncertainty since Auger rates vary asthe cube of the carrier density. Data described inthe previous section, however, provide the neededcalibration. We increased the Auger coefficientsuntil the simulations yield the experimentally ob-served saturation recovery time for an "off" p-drainstrike (see "calibration" in Fig. 3). This required afactor of 1000 increase corresponding to a carrierdensity or volume difference of 10. These values areeasily rationalized by noting that our mesh is 0.026um and transistor width is 5 um for a area (volume per
2micron of track) of 0.13 am . For a track diameter of0.1 pm [9] we find an area ratio actually in excess of10. Although the factor appears large it only movesthe "cross-over" from Auger to SRH recombination to
about 1E18 carriers/cm3, which occurs at about 0.5nsec in the simulation. Thus, our procedure stronglyaffects the nature of the perturbation in that alarger fraction of the ionization charge quicklyrecombines, but the mechanisms governing cell responseare unchanged.
Figure 3 shows our results. Following the singlepoint "fit", the curves shown for n- and p-drainstrikes are calculated. This no free parameter set ofcalculations follows the data quite well, a par-ticularly significant result for the n-drain strikewhere an entirely different upset mechanism is trig-gered by the strike [3,4]. Further, the saturationeffect in our simulations is a direct consequence ofthe increased Auger rate in that saturation is notsimulated without this change. Quite likely in thereal world Auger is the responsible mechanism for theobserved saturation effects. This provides ourmethodology with a physical basis, although the goodexperimental agreement justifies our action a os-teriori.
LRAM Concept and Results
The resistors in the SRAM of Fig. 1 simply slowthe response of the memory cell, allowing recovery[1,9]. The cell illustrated in Fig. 5 employs resis-tors for a fundamentally different purpose. Inaddition to the normal feedback resistor, a secondresistor is placed between the p-drain and the infor-mation node of each inverter. We designate this LRAMrepresentative of the shape of the resistors in twolines of an inverter. This new resistor and the "on"n-channel transistor form a voltage divider at theinformation node, allowing cell designs that limit theion induced transient amplitude at this point tovalues below the switch point of the inverters.Consequently, a strike at the "off" p-drain can neverproduce an SEU. This concept was first suggested byOchoa [10] who verified the voltage division usingSPICE, but at that time was unable to establish theadvantage of the LRAM due to inadequacies of a SPICEanalysis for SEU simulation.
The difficult theoretical questions involve theSEU sensitivity for strikes on the n-channel transis-tor. For this it is crucial to accurately comparerecovery times for the cell following strikes atdifferent locations on the circuit. Our ability tosimulate the recovery process and the inability ofcircuit models (SPICE) to address this phenomenaprovide us with a needed advantage in the analysis ofthe LRAM. This is illustrated by the recent report[11] of a SPICE analysis of a cell identical to theLRAM. Since recovery times are, in effect, inputparameters to SPICE, the physical processes active inthe LRAM, in particular the voltage division, wascompletely missed in the study. The basic premise ofthe LRAM, and consequently its unique advantage, wassimply not reported.
Several studies have shown that SEU data can bemimicked by SPICE and trends in SEU sensitivity aresuccessfully reproduced. In essence this is ac-complished by choosing the recovery time prior tocalculation such that TF = RFC, where RF is the known
critical resistor. However, when RF is not known
there is no accurate procedure for selecting the inputparameters for analysis. This is clear in reference 1where predictions for critical resistors were an orderof magnitude too small. It is further evident in theSPICE results for the LRAM [11] where the calculatedcritical resistor is at least a factor of three dif-ferent from our experiments, in spite of significantparameter changes for each strike location.
While these deficiences of SPICE analyses areaddressed by our calculation method, the problem isnow much more involved, requiring about two hours ofCPU time of a CRAY-I to simulate the cell response toa single strike. However, the LRAM is a good il-lustration of the ability of this numerical techniqueto produce accurate predictions where SPICE analysesfail. For this problem we have demonstrated some costeffectiveness by extracting design information fromdiscretes fabricated using a new technology: informa-tion that would have been lost without thiscapability.
An interesting theoretical result of our work isthat SEU from strikes at the n-channel gate are mostdifficult to prevent. The mechanism here is a "turnon" of the n-channel transistor similar to the drainstrike [4]. This is a novel mechanism, but its pos-sibility was recognized following study of the drainstrike mechanism. Experimental evidence for gatestrike SEU is not definitive, but much better agree-ment with our data is found for gate than for drainstrikes, as we will discuss. We point out that theconcept of critical charge employed in SPICE modelshas no physical meaning for a gate strike, whichfurther illustrates the inadequacy of a circuitsimulator for this problem.
We have fabricated LRAM test structures consist-ing of a single cell with access transistors andcontrol circuits for reading and writing the unit.The memory transistors have the same gate lengths andwidths as transistors in the SRAM. Only the drainareas are smaller. A two level poly process was usedto fabricate the structures with the two sets ofresistors set at equal values. The resistors arecreated in the second level polysilicon by masking theresistor areas from the heavy doping step. Thisrequires two masks if different resistors are used,but as we show in our results, only one level isactually needed. In summary, the LRAM is created withonly one additional mask level relative to a two levelpoly process. Since the additional steps are related
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to an ion implantation process, there is little addi-tional complication due to this hardening technique.
We tested three "one-bit" memories in a series ofexperiments carried out at the Berkeley cyclotronusing Cu and Kr as the incident ions. These ionsprovided effective LET from 0.3 to 0.8 pC/pm.Initially the units, operating at 5V, were exposed toCu. When no upset was observed the operating voltagewas lowered until SEU was detected, thereby insuringthat the experiment was valid. We then systematicallyincreased the LET, at 5 V memory operation. Typicallywe would expose the unit to a fluence of about 1E6
cm 2 and check for upset. We repeated this for 15 to20 iterations, only some of which produced SEU, toinsure the upset-no upset condition. Figure 6 showsthe number of upsets as a function of LET. Accuratefluences are difficult to measure over the extremelysmall area of a single cell, thus cross sections arenot determined. However, our work implies that thecross section should reach a value of about 1.6E-7
-2cm for the single cell in our experiments, comparedto 1.1 to 1.2E-2 cm 2 for the full SRAM of Fig. 2.
Our data reflect fabrication problems experiencedwith alignment between first and second polysiliconpatterns. Misalignment at this point in the processsequence will produce a contact resistance increasebetween one of the n-channel transistor drains and thecross link containing RF. In effect, this will in-
crease the value of one of the RF resistors.
Resistance inequality in the two cross coupling linesproduces a pronounced asymmetry in the SEU sensitivityfor strikes on the two different n-channel transis-tors. We investigated this effect earlier in latches[12] where the asymmetry is designed-in. As long asthe increase in resistance is confined to a few tensof KQ, the asymmetry is manifest by a strong hardeningto strikes on the affected transistor, but with mini-mal change for strikes on the unaffected inverter.Our simulations, shown in Fig. 6, do not include thismisalignment, and only reflect behavior expected ofthe unaffected n-channel transistor. In the actualcircuit strikes on the unaffected inverter willproduce the observed threshold LET for upset, sincestrikes on the affected inverter will have thresholdsat larger LET. For this reason we focus on the SEUthreshold to make experimental comparisons.
A second problem in fabrication produced anunusually large variation in the value of resistorsacross the wafer. Test structures allowed measure-ments of the two resistors at various locations, butnot directly in the memory cell. We found that in allcases the drain and cross coupling resistor were thesame value, but that this value varied considerably.The mean resistance was about 13 KQ and most sampleswere between 10 and 20 KQ.
The data in Fig. 6 show that the SEU threshold isin the range 0.5 to 0.6 pC/Im. This observed behaviorreflects significant hardening relative to the SRAMwhere even with 20 KQ, a threshold of less than 0.3pC/jam is observed.
Our no free parameter calculation finds that fora drain strike in the LRAM, SEU is prevented com-pletely using only 10 Kg as the resistor. For a gatestrike we find SEU threshold at 0.5 pC/pm when 10 KQis used in the cell and at 0.65 pC/pm using 20 KQ.These two values define the range shown in Fig. 6.Thus, the observed range for LET threshold is inagreement with our calculations only when a gate
strike is used. This is evidence that gate--notdrain--strikes produce the SEU in our LRAM cells.
To harden the cell to 0.8 pC/pm we calculate that30 KQ is sufficient when equal resistors are used. Infact, complete hardening is also accomplished with 30KQl in the gate line and only 10 KQ in the drain line.This is about an order of magnitude less than isrequired for the SRAM and, consequently, represents asignificant advance in the concept of radiation hard-ening of memory cells.
The timing advantages of an LRAM relative to anSEU hardened SRAM depend on the memory design.However, an intrinsic cell speed can be determinedwith our simulations. The resistors have no effect onread times and delay write times by RFC, where RF is
the resistor in the gate line. We have seen that fora comon transistor geometry this resistor changesfrom 400 KQ in the SRAM to 30 KQ2 in the LRAM. Oursimulations and simple calculations based on the celllayout and technology give write times of 8.0 and 0.6nsec, respectively. Although this is a large dif-ference the more important potential application ofthe LRAM concept will occur for higher scale integra-tion where the resistor values required for resistivedecoupling may be prohibitively large. Should thatsituation occur, an LRAM will be the only practicaltechnique for using resistors in SEU hardening.
Conclusions
Our primary finding is the LRAM immunity to SEUusing resistors about one order of magnitude smallerthan currently employed in SRAM with the same transis-tor geometry. This result was predicted bysimulations of the LRAM memory cell, a projection onlypossible with the circuit-plus-transport techniquedescribed in our work.
The experimental determination of time constantsfor voltage transients following ion strikes at twodifferent locations within a full static memory is thefirst data of this type reported. Although resistorvalues that provide complete imunity have been cited[1], association with a particular strike location anddetermination of a second transient time has only now
A
NO OF SIMULATION RANGEUPSETS s FOR Lc
0
0
I -I-I I I I 10.20 0.30 0.40 0.50 0.60 0.70 0.30
LET (pC/ pm)Figure 6 Number of SEU observed for three one-bitLRAM cells, indicated with different symbols, as afunction of LET. The width of the cross-hatchedregion represents the theoretical range of thresholdLET. The range is defined by two simulations ofstrikes at the "off" n-channel gate. The first used10 KQ in the LRAM and the second used 20 Ka, where RF= RL (Fig. 5).
1286
been accomplished. The transients are longer thanexpected from analytical models [131 or from measure-ments on test diodes [14]. Long transients areevidence of modulated photocollection due to circuitloading [21 and illustrate the severe difficultyfacing experimental, as well as theoretical simula-tions of an actual SEU. Our numerical simulationsaccount for the observed SRAM characteristics. Againthe wide variety of experiments require the circuit-plus-transport method to achieve realistic numericalsimulation.
The capability of our simulation method to ac-count for the SRAM data and to project the observedLRAM behavior represents a major accomplishment forsimulations. The key feature of our simulator is theability to move the ion strike from location to loca-tion without parameter changes, allowing directcomparisons of the SEU response for different strikes.We confirmed the simulations in SRAM for n- and p-drain strikes and calculated sensitivity for gatehits. However, the gate hit responses are unobserv-able in existing SRAM data. The gate hits are thepredicted worst case for the LRAM and their simulatedcharacteristics agree with our experiments on the one-bit LRAM cells.
Table I
Summary of critical resistor values required toprevent SEU for strikes at the two indicated loca-tions. The saturation transient times are found usinga nodal capacitance of 0.03 pC.
Critical SaturationRF TR
(KQ)
n-drain Strike 20-30
p-drain Strike 200-220
(nsec)
0.6 - 0.9
6.0 - 6.6
Acknowledgements
We appreciate the technical assistance ofJ. Mansfield and discussions with P. Dressendorfer andP. Winokur.
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