Architecture Handout Part -II - Copy

College Of Computing and Informatics – Department of Computer Science

1 | P a g e - P r o f . ( D r . ) F a i z u r R .

Part –II Computer Organization and Architecture

Chapter 3- Register Transfer and Microoperations

3.6 Arithmetic logic Shift unit

Instead of individual registers performing the microoperations directly, computer system employ a

number of storage registers connected to a common operational unit called Arithmetic Logic Unit

the data in the multipleser are selected with inputs S1 and S2… Other input are Ai-1 - Shift Right



Operation and A i+1 Shift Left Operation.



Chapter 4. – Basic Computer Organization and Design

- Computer Design- Internal register, timing & Control structure and the set of instruction.

- The User of computer can control the process by means of a program.

- A program is a set of instruction that specify the opearation, opearands, and the sequence by

which processing has to occur.

- The data processing task may be altered by specifying the same instructions with different data

or a new program with different instructions.

- A computer instruction is binary code that specifies a sequence of microoperation.

o Instruction code is stored in memory.

o These are read from memory and placed in control register.

o Then to execute.

4.1 Instruction Code : this is a group of bits that instruct the computer to perform a specific operation.



4.1.1 Stored Program Organization

4.1.1.a. Accumulator (AC)





4.2 Computer Registers

- All memory Locations of registers are executed sequentially.

- This type of instruction sequencing needs a counter to calculate the address of the next

instruction.

- It is also necessary to provide a register in the control unit for storing instruction code after read

from memory.

- The computer need processor register for manipulating data and a register for holding a

memory address.

- AR has 12-bit, since this is the width of the memory address.

- PC has 12-bits holds address of next instruction to be read from the memory.

- To read an instruction, the content of PC is taken as the address for memory and a memory read

cycle is initiated. PC is then incremented by One.

- Two Registers are used for input/ output-

-INPR – Receive 8-bit character from a input device.

-OUTR- Holds 8-bit character on output device.



4.2.1 Common Bus System

- Basic Computer have eight registers, a memory unit, and a control unit..

- A more efficient scheme to transferring information in a system with many registers is to use a

common bus.





4.3 Computer Instruction

- Basic computer has three instruction code formats; each format has 16-bit. - The operation code (opcode) contains 3-bits and remaining 13 bits depends on the operation encountered. - A memory reference instruction uses 12 –bits to specify address & 1 bit to specify address mode I.

I=0 ,for direct addressing I=1, for indirect addressing



-The Hexadecimal code is equal to the equivalent hexadecimal number of the binary code used for the instruction. - By using hexadecimal equivalent we reduced the 16-bit s of an instruction code to four digit with each each hexadecimal digit being equivalent to 4-bits. - A memory reference instruction has an address part of 12- bits. - The address part is denoted by three X’s. - The last bit of an instruction is designated by the symbol i. - If last bit =0, last four bits have hexadecimal digit from 0 ,to 6.



- if last four bits have hexadecimal digit 8 to E, last bit =1.

4.4 Timing and Control There are two types of control-

- Hardwired control - Microprogrammed control

-In hardwired control logic is implemented with gates, flip-flops, decoders and other digital circuit. - The control information is stored in a control memory. - The control memory is programmed ro initiate the required sequence of microoperation. - In hardwire, wiring is required to change, if modifies or changed. - In microprogramming any changes can be done by updating microprogram in control memory. -Control Unit – It consist of two decodes, a sequence counter, and number of control logic gates. -Timing Signal- The output of the counter are decoded into 16 bit timing signal, T0 to T15. The Sequence counter SC can be incremented.

- Once a while, a counter is cleared to 0, causing the next active signal to be T0.



4.5 Instruction Cycle

-A program is executed in the computer by going through a cycle for each instruction. -Each instruction cycle is subdivided into sub cycles which consist of the following phase: - Fetch instruction from memory - decode the instruction - Read the effective address from the memory - execute the instruction The above cycle continues until the HALT instruction is encountered.



4.5.1 Fetch & Decode

- It is necessary to use timing signal T1 to provide the following connection in the bus system.

1) Enable the read input of memory 2) Place the content of memory onto the bus 3) Transfer the content of the bus to IR by enabling the LD input of IR. 4) Incrementing PC by enabling the INR input of PC.



4.5 Design of basic Computer

4.5.1 Control Logic Gates





Chapter 5. Central Processing Unit

The Processor which performs bulk of data processing operation is called CPU. It Consists of three major parts:

- ALU- Performs Microoprations - CU- Supervise the transfer of information and instruct the ALU to which operation has to

perform. - MU- Memokry Unit.

-Task provides choosing hardware for implementing machine instruction. -Following structure should be known to the language developer: - Register Set - Memory Structure - Supported data by instruction 5.1 General Register organization -Memory are needed for for storing pointer, counter, return address, temporary results and partial products during multiplication. - Registers communicate each other during performing microoperation. - For Seven CPU Registers, each register is connected to two MUX to form the two Buses A and B.



5.2 Control Word

There are 14 binary selection inputs in the unit, and their combined value specifies a Control Word.

- The 14- bit control word, consist of 4 fields.

- Three fields contains 3-bit each and one field has 5 –bits

SELA – selects 3-bits for ALU

SELB – Selects 3 – bits for ALU

SELD- Selects destination register using decoder and its seven load outputs

OPR- Selects one of the operation in ALU.

When 14-bit control word are applied to the selection inputs , specify a particular Microoperation.



Control word is specified by the four fields and the corresponding binary value for each field is detained

from the encoding.

The Binary control word for subtract Microoperation can be shown like-

A memory unit that stores control words is referred as control memory.



5.3. Stack Organization

Stack (LIFO) in CPU are used in efficient way. The items are stored in CPU in such a memory that the

item is stored last will be retrieved first.

- Stack in memory unit an address registers hold the address for the stack is called Stack

Pointer(SP).

PUSH- Insert

POP- Delete

The operation is stimulated by incrementing / decrementing the stack pointer register. Register Stack- Stack can be organized in a collection of finite number of memory words / register. SP contains a binary no whose value is equal to the address of the word that is currently on the top of the stack.



5.4. Memory Stack

-Stack pointer can be checked by using two processor register. -One to hold upper limit and the other to hold lower limit.



5.5 Reverse Polish Notation (RPN)

Evaluation of Arithmetic Expression



5.4 Instruction Format

It is a function of control unit within the CPU to interpret each instruction code and to provide necessary

control function needed to process the instruction.

- The bits of instruction are divided into groups called fields

o Operation code field - operation to be performed

An Address field – designates memory address

A mode field – The way the operand or effective address is determined.

- Operation computer instruction executed on some data stored in memory Register. Operand

residing in memory specified by their memory address.

- Operand in process register specified with address register.

Register Adress- It is a binary number of k bits that defines one of the 2k register in the CPU.

Thus 16 Bit processor register will have register address field of 4-bits.

The Binary 0101 will designates R5. Most Computer may have any of three computer Organization.

- Single Accumulator Organization - General register Organization - Stack Organization

Accumulator register uses one address field, in Assembly Language. An Arithmetic addition can be represented in Assembly Language Like

ADD X



to evaluate

Two Address Instruction to evaluate

One Address Instruction to evaluate – all operation are done between AC and memory Operand.

Zero Address Instruction



5.5. Characteristics of RISC and CISC

RISC- Reduced Instruction Set Computer CISC – Complex Instruction Set Computer

- Relatively few instruction - A Large Variety of Instruction 100-200.

- Relatively few addressing modes - Some instruction perform specified task

- Memory Access limited load and - A large variety of addressing modes 5-20

Instruction

- All operation are done within the - Variable length instruction formats

Limitation of CPU

- Fixed length, easily decoded instruction - Instruction that manipulate in memory

Format.

- Single Cycle instruction execution

- Hard wired rather than Micro program

Control.

5.6 Overlapped Register Window

Date post:	06-Feb-2023
Category:	Documents
Upload:	independent
View:	0 times
Download:	0 times

Architecture Handout Part -II - Copy

Documents