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EEDG-6306 ASIC Design 2014 Fall Project
Mini Stereo Digital Audio Processor(MSDAP)
Department of Electrical EngineeringThe University of Texas at Dallas
Guided By Dr. Dian Zhou Mr. Zhaori Bi Professor Teaching Assistant Prepared By Aalay D. Kapadia (adk130330)
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Outline• Project Definition• Introduction• Computation Method• Specification• Simulation Results• Physical Design Synthesis & Simulations
• Results• Conclusion
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Project Definition• Paper on A Mini Stereo Digital Audio Processor (MSDAP) by
Zhangnong Jiang (Electrical Engineering Department, UCLA) http://www.utdallas.edu/~mxl095420/EE6306/MSDAP%20paper.pdf
• http://www.utdallas.edu/~zxb107020/EE6306/Project/index.html
• Tools to be Used:• Xilinx ISE 14.7• I-sim simulator• Design vision• ICC Chip Design
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Introduction• Digital audio processing plays an important role in many
applications where the audio requires specific formats for reproduction, transmission or storage.
• The fundamental function of the Mini Stereo Digital Audio Processor (MSDAP) is to implement a finite impulse response (FIR) digital filter.
• The performance of the MSDAP is expected to be the same as that of two general DSP chips for implementing two-channel FIR digital filtering in audio applications.
• The FIR digital filtering involves the following linear convolution:
• Where x(n) and y(n) are input and output audio sequences, and h(k) are filter coefficients with the filter order N.
• From convolution equation, the linear convolution calls for N+1multiplications and N additions.
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• For linear-phase FIR filters, the symmetry and anti-symmetry of filter coefficients can save multiplications by half .
• A hardware multiplier, either a fixed-point or a floating-point version, is invariantly integrated on a general DSP chip so that it can accommodate a variety of application requirements.
• For more and more embedded system integrated as system on chip (SOC) design, power dissipation becomes a key issue of integrated circuit design.
• By using programmable FIR filtering structure with one-bit shifter, only addition/subtraction operation will be needed and thus performed in a very high efficiency.
• An excellent programmable FIR filtering structure using only a one-bit shifter was proposed in.
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Computation Method• Hardware complexity of FIR filter design can be reduced by
coding the filter coefficients efficiently. • When the coefficients h(k) is coded by using the minimum-
number power-of-two (POT) digits, multiplications can thus be performed at a very high efficiency.
• For example, suppose that• h(k)=0.1172 and a good approximation,
• is available, the multiplication h(k)x(n-k) shows that the computation procedure
• uses only three shifts and three addition/subtractions, and it is several times more efficient than using a general multiplier with the same precision.
• Optimal POT coefficients for an FIR filter are usually obtained by using integer optimization techniques.
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• It is noted that filter coefficients with a big POT digit such as +2-16 or -2-16 in digital audio system is enough.
• For the linear convolution, it can be transformed as following expression by using programmable FIR filtering structure
• And
• Where
• and rj is the total number of the POT digits ±2-j Occurred among all filter POT coefficients.
• By way of illustrating the equivalence between linear convolution and our calculation, we consider a design example that is a 7th-order FIR filter performing
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• The MSDAP will be able to implement FIR filter with order N =7. Each u j is computed by 8 input data(x[n] to x[n-7]) and 8 coefficients.
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Specification
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• Figure shows the working environment of the MSDAP chip. Audio data is transmitted between analog-to-digital converter (ADC) and digital-to-analog converter (DAC).• Controller extracts audio data from a frame and sends audio data to the MSDAP chip in stereophonic mode.
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• In stereophonic mode, controller transmits stereophonic audio in which the two channels are sampled simultaneously
• The left channel conveys audio data in InputL pin for the MSDAP chip, while the right channel does in InputR pin.
• At the same time, controller receives both left channel and right channel of output data from OutputL and OutputR pins of the MSDAP chip.
• Then, controller packs output data in the frame format and transmits to DAC.
• It is expected that another kind of frame format will be used between controller and the MSDAP chip to convey audio data that are sampled at frequency of 768 KHz.
• Each frame is divided into 16 time slots, numbered from 0 to 15. Therefore, the frame rate is at frequency of 48 KHz (768 KHz/16). The audio sample frame format is illustrated as follows:
• Time slots 0 to 15 present the audio sample word. The sign bit is carried by time slot 0. The most significant bit (MSB) is carried by time slot 1.
• The audio sample word is linear in 2’s Complement binary form. • Positive numbers correspond to positive analog voltages at the input
of the ADC.
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• The number of bits per word can be specified to 16. The data clock rate is fixed at 768 KHz and the system clock rate is 6.2MHz.
• When each input data is read, the result should be calculated and send to output at the same time.
• For worst case, each u j Term adds 8 inputs and total cycle is 128. If system clock is 8 times faster than data clock rate, the minimum system clock rate can be achieved.
• One format of coefficients can be defined like this way: each coefficient has 16 bits and the leftmost bit is the most significant bit (MSB).
• Each input sample occupies two bits. One bit is sign bit and the other is value bit. If one input sample is untended, its value bit is 0 and its sign bit is 0as well.
• If one input sample is attended, its value bit is 1.Furthermore, if this attended input sample is involved in addition, its sigh bit is 0, and otherwise it is 1.
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Specification ResultsData Clock 768kHzSystem Clock 6.2M HzM em ory 1M B
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Analysis of Application in term of Operation and I/O requirement:
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State Nam e O perationNext State Alternate O peration
Alternate Next State
State 0 Initialization
W hen Start is high,Chip starts its initialization process like clearing State 1 - State 1
State 1 Rj ready InReady sets to high. State 2 - State 2
State 2 Rj Receive
Frame is high and chip reads Rj values and stores in memories State 3 - State 3
State 3 Coefficient readyIn Ready sets high for
Coefficeints. State 4 - State 4
State 4 Coefficient Receive
Frame is high and chip reads coefficients values and stores in memories State 5 - State 5
State 5 Input Data ready In Ready sets high for Input Data reception State 6
If Reset goes low,All previously sent input data goesfor clearing State 7
State 6Input Data Receiving &
Calculation
Frame is high and chip reads Input Data values and stores in memories and simultaneously works on stored
Rj,Coefficients and Input Data generate Output Data which will be sent out when OutReady is high .After all when chip detects Reset it will go into clearing mode State 7
Two channel 800 consecutive 16bits-Zeros would drive the
chip going to sleep mode. (i.e. left channel detected 1000 consecutive 0s, right
channel no consecutive 0s. The chip is awake). State 8
State 7 Reseting(Clearing)
In Ready goes to '0',All M emory for Input and Output Data values are erased and reset to zero.Then InReady is
again high for State 5 for new Input Data. State 5
If it is reset again it will remain in same
state State 7
State 8 Sleeping
Chip will go to sleep mode means it will
receive data but won't work on it because there are strings of zero as
input. W hen ever there is data detected except zero it will again go to
state 6. State 6
In Ready goes to '0',All M emory for
Input and Output Data values are erased and reset to zero.Then
InReady is again high for State 5 for new
Input Data. State 7
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State Transitions:State0 To
State1
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State Transitions:State1 To
State2
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State Transitions:State2 To
State3
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State Transitions:State3 To
State4
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State Transitions:State4 To
State5
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State Transitions:State5 To
State6
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State Transitions:State6 To
State7
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State Transitions:State7 To
State5
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State Transitions:State5 To
State7
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• There are some assumptions in the functionality. When the chip receives 800 consecutive zero input samples, all the data in memories and registers are zero except the coefficients.
• It is the same way of clearing state. Thus, the chip can skip clearing state and turn from working state to sleeping state.
• If the external controller detects that InReady =’0’sent by the chip, controller will not transmit Dclk, frame, and any input sample to the chip until the InReady=’1’ is detected.
• If the external controller detects that InReady=’1’sent by the chip, the continuing time frame will not be more than 16 data clock cycles to ensure the coefficients be filled correctly. It is noted that there is no Reset will be activated in state 0, 1 or 2.
• The finite state machine (FSM) is a common functional block for the system.FSM sends the control signal to each functional block in right and left channels.
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Signal Nam e Type O peration StateStart Input It will turn on the chip State 0
InReady Output
It will send signal to controller that chip is ready to receive
inputs from outside
From 1 TO 8 All require it to be '1' except State 7 where chip goes to
clearing mode and InReady becomes '0'
Frame Input
It will send signal to chip from controller that this is the end of one piece of data and W hen new piece of data comes Frame signal will again go high.In our case for input it is set for 16bit and output
it is set to be 40 bit.All Require Frame to be'1' for
States 2,4,6
OutReady Output
It will send signal to controller that chip is ready to send 40 bit FIR coefficient values to outside
For state 6 OutReady should be '1' and for state 8 for sleeping mode it
goes to '0'
R̀eset_n Input
It is low value reset where system chip starts reseting when
Reset_n goes low State 7 (To go into clearing mode)
InputL,InputR Input
It is signal from where all the inputs come serially on chip for
left and right side State 2,4,6,8
OutputL,OutputR Output
It is signal to send output to outside from chip after
calculation State 6
SCLK Input
It is reference clock for on chip calculation and signals which are output from chip. It runs on freq.
26.88M Hz State 1 to 8
DCLK Input
It is reference clock for Data input from outside,It is given as
on freq. 768kHz State 2,4,6,8
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Expected Output
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Output Obtained
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Given Architecture
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Given Architecture
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Proposed Architecture
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MSDAP Chip
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ALU Design
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Critical Path
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Timing Budget
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Post Synthesis Simulation (Multisim)
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Layout After Design Optimization
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Layout After Routing
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Final Layout Design
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MSDAP Layout
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Design Report
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Conclusion• In this project, the low-power and low-cost stereo audio
processor which can process stereo audio in real time has been presented and designed in TSMC 0.18μm CMOS technology.
• The linear convolution of FIR filter of MSDAP chip is based on programmable FIR filtering structure, which only uses adder and shifter at computation and has simplified the hardware design complexity.
• The data clock rate is 768KHz and system clock rate is 6.2MHz.
• The total chip area is about 2.263mm2 and power dissipation is about 48 mW.
• These figures are lower than those of DSP chips that provide equivalent processing performance.
• With lower power dissipation and chip area, this design is suit for integrated on SOC chip efficiently.
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Acknowledgement• I am indebted to the VLSI CAD lab at the University of
Texas at Dallas, in the United States, and for their technical supports of this work.
• I am indebted to the Teaching assistant Mr. Zhaori Bi and Dr. Dian Zhou for their help and guidance.
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References:
• Paper on A Mini Stereo Digital Audio Processor (MSDAP) by Zhangnong Jiang (Electrical Engineering Department, UCLA)
• “Modern VLSI Design,” by Wayne Wolf, Prentice Hall, ISBN 0-13-061970-1.
• “Modern ASIC Design”, by Dian Zhou, ISBN 978-7-03-031766-7, Science Press, China, 2011.
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Questions
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