INTEGRATION, the VLSI journal 41 (2008) 183–192 Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters Hamed Aminzadeh , Mohammad Danaie, Reza Lotfi Integrated Systems Laboratory, EE Department, Ferdowsi University of Mashhad, Mashhad, Iran Received 2 May 2006; received in revised form 1 May 2007; accepted 9 May 2007 Abstract Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired specifications. Simulation results are presented to show the effectiveness of the methodology. r 2007 Elsevier B.V. All rights reserved. Keywords: Cascode compensation; Design methodology; Frequency compensation; Operational amplifiers; Power optimization; Settling time; Switched- capacitor circuits 1. Introduction Operational amplifiers (opamps) are widely employed in analog and mixed-signal circuits such as regulators, filters and data converters for buffering, filtering, amplification of signals and many other purposes. Single-stage opamps have superior frequency response and are faster compared to multistage opamps. However, as their achievable open- loop DC gain may not be satisfying particularly in low- voltage applications, they might not be able to adequately suppress the open-loop non-linear effects of the amplifier to achieve the required accuracy [1,2]. In order to increase the closed-loop accuracy, two-stage opamps with higher open-loop DC gain could be used instead. Frequency compensation is evidently essential to prevent instability in the closed-loop multistage amplifiers behavior. A number of compensation techniques have been reported in the literature, e.g., [1–4]. Among possible compensation alter- natives proposed for two-stage opamps, Ahuja-style or cascode compensation [3] has recently become very popular. This is due to the fact that it usually leads to lower power consumption (with similar speed) or higher speed (with similar power consumption) and higher power supply rejection ratio (PSRR) when it is compared to more traditional methods such as Miller compensation. Never- theless, these advantages are at the cost of more complexity in the design, optimization and robustness of a cascode- compensated amplifier. Perhaps, the main reason for such complexity is the increase in the order of the system up to three when the compensation is applied to a two-stage opamp. This results in a considerable designing effort for the designer to find the optimized transistor dimensions before implementing the circuit into silicon die. The aim of this paper is to simplify this problem by performing a new fundamental analysis, based upon the meaningful and user- friendly open-loop system-level parameters instead of their closed-loop counterparts. As a result, the analysis leads to relatively simpler design equations. This originates from the fact that in previous methodologies [5,6], the designer should firstly determine the required closed-loop specifica- tions. Next, the open-loop requirements like DC gain, unity-gain bandwidth (GBW) and phase margin such that those closed-loop specifications are satisfied are specified. However, as the analysis performed here is based on open-loop specifications, the methodology is able to directly determine the required open-loop parameters. In addition, as the desired accuracy for a given settling time is ARTICLE IN PRESS www.elsevier.com/locate/vlsi 0167-9260/$ - see front matter r 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2007.05.003 Corresponding author. E-mail address: [email protected] (H. Aminzadeh).
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0167-9260/$ - se
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INTEGRATION, the VLSI journal 41 (2008) 183–192
www.elsevier.com/locate/vlsi
Design of high-speed two-stage cascode-compensated operationalamplifiers based on settling time and open-loop parameters
Hamed Aminzadeh�, Mohammad Danaie, Reza Lotfi
Integrated Systems Laboratory, EE Department, Ferdowsi University of Mashhad, Mashhad, Iran
Received 2 May 2006; received in revised form 1 May 2007; accepted 9 May 2007
Abstract
Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the
design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational
amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of
transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired
specifications. Simulation results are presented to show the effectiveness of the methodology.
r 2007 Elsevier B.V. All rights reserved.
Keywords: Cascode compensation; Design methodology; Frequency compensation; Operational amplifiers; Power optimization; Settling time; Switched-
capacitor circuits
1. Introduction
Operational amplifiers (opamps) are widely employed inanalog and mixed-signal circuits such as regulators, filtersand data converters for buffering, filtering, amplification ofsignals and many other purposes. Single-stage opampshave superior frequency response and are faster comparedto multistage opamps. However, as their achievable open-loop DC gain may not be satisfying particularly in low-voltage applications, they might not be able to adequatelysuppress the open-loop non-linear effects of the amplifierto achieve the required accuracy [1,2]. In order to increasethe closed-loop accuracy, two-stage opamps with higheropen-loop DC gain could be used instead. Frequencycompensation is evidently essential to prevent instability inthe closed-loop multistage amplifiers behavior. A numberof compensation techniques have been reported in theliterature, e.g., [1–4]. Among possible compensation alter-natives proposed for two-stage opamps, Ahuja-style orcascode compensation [3] has recently become verypopular. This is due to the fact that it usually leads tolower power consumption (with similar speed) or higher
e front matter r 2007 Elsevier B.V. All rights reserved.
speed (with similar power consumption) and higher powersupply rejection ratio (PSRR) when it is compared to moretraditional methods such as Miller compensation. Never-theless, these advantages are at the cost of more complexityin the design, optimization and robustness of a cascode-compensated amplifier. Perhaps, the main reason for suchcomplexity is the increase in the order of the system up tothree when the compensation is applied to a two-stageopamp. This results in a considerable designing effort forthe designer to find the optimized transistor dimensionsbefore implementing the circuit into silicon die. The aim ofthis paper is to simplify this problem by performing a newfundamental analysis, based upon the meaningful and user-friendly open-loop system-level parameters instead of theirclosed-loop counterparts. As a result, the analysis leads torelatively simpler design equations. This originates fromthe fact that in previous methodologies [5,6], the designershould firstly determine the required closed-loop specifica-tions. Next, the open-loop requirements like DC gain,unity-gain bandwidth (GBW) and phase margin such thatthose closed-loop specifications are satisfied are specified.However, as the analysis performed here is based onopen-loop specifications, the methodology is able todirectly determine the required open-loop parameters. Inaddition, as the desired accuracy for a given settling time is
H. Aminzadeh et al. / INTEGRATION, the VLSI journal 41 (2008) 183–192184
important in many applications (such as in switched-capacitor circuits), the relationship between opamp band-width and its settling time is also presented here. For agiven settling time, the relation makes it possible to directlydetermine how much bandwidth is needed for the opampto settle within a particular settling error. The effect ofzeros in the opamp transfer function, traditionallyneglected, is taken into account in this work as well. Thismakes the analysis more accurate.
Based on these innovations, straightforward yet accurateexpressions for the design of high-speed cascode-compen-sated opamps are presented. The methodology can pavethe way for easier use of two-stage opamps in switched-capacitor applications. It is also helpful to determine theoptimized transistor dimensions when the settling time andpower consumption are to be minimized.
The rest of the paper is organized as follows. In Section2, a new open-loop settling-based analysis for single-stageopamps is presented. This part is essential for making thesimilar analysis for higher-order cases comprehensible. InSection 3, the analysis is developed to two-stage cascode-compensated opamps. Sections 4 and 5 present theproposed methodology and simulation results, respectively,and at last, Section 6 concludes the paper.
2. Single-stage opamps
2.1. Small-signal section settling analysis
The open-loop transfer function of a single-stage opampwith one left-half-plane (LHP) pole and no zero is asfollows [1,2]:
AVðsÞ ¼A0
1þ s=o0, (1)
where A0 and o0 are the open-loop DC gain and �3 dBangular frequency, respectively. In closed-loop configura-tion, the total settling error (eSS,t) at a particular moment isa function of the required accuracy. The total settling errorshould be specified according to the application require-ments. This parameter is comprised of two differentsections, originated from finite opamp open-loop DC gain(eSS,A) and finite open-loop gain-bandwidth product (eSS).In a system with negative feedback, one can easily showthat the contribution of by eSS,A to the total error is asfollows [1]:
eSS;A ¼1
1þ A0bffi
1
A0b, (2)
where b is the feedback factor of the closed-loop amplifier.Hence the total error can be obtained from:
eSS;t ¼ eSS þ 1=A0b. (3)
On the other hand, the relationship between small-signalsettling time (tSS) and eSS in a single-stage opamp (with anapproximated transfer function as (1)) is [1]
eSS ¼ expð�tSS=tÞ ¼ expðbGBW tSSÞ. (4)
In this equation, tSS and t are the small-signal settlingtime and the closed-loop time-constant, respectively (t ¼ 1/(bGBW)). Moreover GBW represents the angular open-loop unity-gain frequency where |AV(jo)| becomes equal tounity. From (4), the following relationship between tSS andGBW can be obtained:
tSS ¼ nt ¼ n1
bGBW, (5)
where n is the number of required time-constants, in whichthe error caused by the finite bandwidth becomes less thaneSS. It is a function of eSS and can be expressed by:
n ¼ f ðeSSÞ ¼ lnð1=eSSÞ. (6)
2.2. Total settling analysis
The analysis performed here, includes all single-stageopamps with estimated single-pole transfer functions i.e.the effect of parasitic poles and zeros should be ignored.Fig. 1 could be an instance. As it is clear, the tail currentcan be expressed by:
ITail ¼ 2I i ¼ CL SR ¼ CL VSwing=tLS, (7)
where SR, VSwing and tLS are the opamp output slew-rate,the maximum peak-to-peak differential voltage swing andthe large-signal settling time, respectively. CL and Ii are theload capacitor and the current of each input transistor,respectively. The goal of the analysis performed in this partis to find the optimized open-loop GBW for which thenegative feedbacked opamp be able to settle to the desiredamplitude (within the required accuracy). Note that therelationship should be obtained for the maximum stepamplitude (as the worst case) so that the required accuracy
ARTICLE IN PRESS
Mi
MC
ML
Mtail
Mi
MC
ML
IL
Ii
VDD
VDD
VDD
B
Vin+
Vin–
VCMFB1
VB1
VB2
B
A A
VB3
VO+
VO–
VCMFB2
VCMFB2
CC
CC
CL
CL
A B
CC
RL
CL
VO
CA
RoA
CB
Vin
RoBg
miV
ing
mLV
B
gmC
1
gmC
VA
Fig. 2. A fully differential two-stage cascode-compensated opamp and its
small-signal equivalent.
H. Aminzadeh et al. / INTEGRATION, the VLSI journal 41 (2008) 183–192 185
for all amplitudes is guaranteed. If there existed arelationship between GBW and tLS, it would be possibleto express the total settling time in terms of GBW. As it willbe seen later, such a relationship is achievable if therequired current to satisfy large-signal settling constraintsis set equal to the one required to satisfy small-signalsettling constraint [6]. This also leads to optimizedequations because if the large-signal and small-signalsettling times are predetermined independently (as pro-posed in [7]), the tail current should be chosen as themaximum value that satisfies both of them. However, thelarge-signal and small-signal currents can be set equal byappropriately choosing the gate overdrive (effective)voltage of input transistors (Veffi) [6]:
I tail ¼ 2I i ¼ gmi V effi ¼ CL VSwing=tLS, (8)
where gmi is the transconductance of input transistors.Since:
GBW ¼ A0o0 ¼gmi
CL, (9)
the relationship between tLS and GBW becomes:
tLS ¼VSwing
V effi GBW. (10)
The total settling time (tS) is comprised of both small-signal and large-signal sections. The analysis for the small-signal section is performed in previous part. By adding (5)and (10), the total settling time becomes equal to:
tS ¼ tSS þ tLS ¼1
bln ð1=eSSÞ þ
VSwing
V effi
� �1
GBW. (11)
Thus the relationship between GBW and tS becomes:
GBW ¼n
bþ
VSwing
V effi
� �1
tS. (12)
This equation shows, as predicted, that if the requiredeSS or VSwing are decreased, the needed GBW for a givensettling time reduces. It also shows that increasing b candecrease the required GBW for a particular settling time.
To obtain the required slew-rate (SR) for a particularsettling time, the following well-known relationship couldbe used:
SR ¼2I i
CL¼
2I i
V effiCLV effi ¼
gmi
CLV effi ¼ V effiGBW . (13)
3. Two-stage cascode-compensated opamps
Fig. 2 shows a two-stage cascode-compensated opampand its small-signal equivalent. It is composed of atelescopic-cascode amplifier as its first stage and acommon-source amplifier as its second stage. Similaranalysis can be applied to a two-stage cascode-compen-sated opamp with folded-cascode topology for its first stagetoo. In the small-signal equivalent circuit, CA, CB and CL
and also RoA, RoB and RL are the total capacitances andresistances seen at nodes A, B and VO, respectively. The
transconductance of each transistor is also modeled with itscorresponding gm. In this figure, each half circuit employsone active capacitor to avoid instability in the closed-loopoperation. An active capacitor consists of a current buffer(MC) in series with a passive capacitor (compensationcapacitors (CC) in Fig. 2) [4]. In cascode compensationscheme, active capacitors are used to reduce the directloading of the passive compensation capacitor on opampoutput. As a result, non-dominant poles are moved torelatively higher frequencies. After compensation byneglecting the effect of high-frequency parasitic poles andzeros, the open-loop transfer function has one dominantand two non-dominant poles. Non-dominant poles arecomplex if their damping factor (x0) is smaller than unity.The transfer function has also two zeros, one at the right-half-plane (RHP) and the other at the LHP. The RHP zerois the result of the feedforward current which flows fromnode A to the output (through CC) [4].After solving the small-signal equations and making
appropriate simplifications, the open-loop transfer func-tion can be approximated as follows [4]:
The transfer function can be written in symbolic form as:
AVðsÞ ffiA0ð1� s2=z2Þ
ð1þ s=o0Þð1þ sð2x0=on0Þ þ s2=o2n0Þ
. (15)
In this equation, A0, z1,2 ¼7|z| and o0 represent theopamp open-loop DC gain, the magnitude of its zeros and
ARTICLE IN PRESSH. Aminzadeh et al. / INTEGRATION, the VLSI journal 41 (2008) 183–192186
the magnitude of the dominant pole, respectively. It isrelatively hard to observe the effect of zeros in the transferfunction shown in (15), and thus most previous studiesneglect their effect [4–7]. An elegant and efficient way tomake the analysis more accurate is to properly model theeffect of zeros in the generic second-order polynomial ofdenominator. Hence, the new values of damping factor (x0)and natural frequency (on0) called as effective dampingfactor ðx00Þ and effective natural frequency ðo0n0Þ can bedefined such that the effects of zeros are taken intoaccount:
1� s2=z2
1þ sð2x0=on0Þ þ s2=o2n0
¼1
1þ sð2x00=o0n0Þ þ s2=o0n0
2.
(16)
The equation in the form of (16) does not result instraightforward relations between the effective dampingfactor and effective natural frequency with small-signalparameters. However, Taylor expansion of zeros can beused to rewrite (16) as:
By ignoring higher than second-order terms that arenegligible when the zeros are located at high frequencies,(17) is simplified into:
1þ sð2x00=o0n0Þ þ s2=o0n0
2� 1þ sð2x0=on0Þ
þs2ð1=o2n0 þ 1=z2Þ. ð18Þ
It has to be noted that approximation (18) may nothold true in the case of low-frequency zeros; in whichhigher-order terms may become important. A criterionfor the minimum magnitude of zeros is obtained inAppendix A.
Comparing (14) with (15), x0 and on0 are obtained asfollows:
According to this expression, the relationship betweenphase margin (PM) and GBW can be estimated as follows:
PM ¼ 180� � tan�1bGBW
o0
� �� tan�1
2x00ðbGBW=o0n0Þ
1� ðbGBW=o0n0Þ2
!. ð22Þ
As o0 is the dominant pole, the second term can beapproximated as 901, therefore:
tanðPMÞ ¼1� ðbGBW=o0n0Þ
2
2x00ðbGBW=o0n0Þ
� �. (23)
Note that (22) is derived based upon the assumptionthat the effect of non-dominant parasitic poles and zeroson the loop-gain transient frequency (where |bAV(jo)|becomes equal to unity) is negligible. Hence this para-meter is approximated as bGBW, similar to single-poleopamps. This is done to simplify the analysis and toexpress the equation in a more useful form. Thisapproximation is fairly valid in typical values of phasemargin. From (23), the relationship between GBW and PM
As it is seen, assuming b and o0n0 to remain unchanged,the lower the effective damping factor, the higher theGBW would be. This however may not be advantageousbecause for the same value of phase margin, the relativedistance between the effective natural frequency ðo0n0Þ andthe GBW decreases. This could finally cause an inducedpeak in the interested frequency region and significantlydegrade the stability. Keeping x00 tanðPMÞ greater thana threshold around unity is essential for the closed-loop stability and a lower x00 should be compensated by ahigher PM.To further continue with the analysis, it is essential to
note that if non-dominant poles are larger than GBW, thefollowing relationship between GBW and gmi is valid [1]:
GBW ¼ A0o0 ¼gmi
CC. (25)
For two-stage cascode-compensated opamps, similarprocedure as the case of single-stage opamps can be carriedout to obtain the relationship between GBW and tS.In particular when the first-stage slewing is dominant,the obtained relation is similar to (12) (the only modifica-tion in the analysis is to replace the load capacitorwith compensation capacitor (CC) in the expressions ofGBW and SR from (7) to (9)). In this case, it is alsoessential to determine the modified formula of time-constant coefficient (n) (the ratio between small-signal settling time and 1/bGBW similar to (6)). Theequivalent formula in third-order systems is non-linear andcomplicated. Moreover, it is not just a function of small-signal settling error like single-stage opamps (Eq. (6)).
ARTICLE IN PRESSH. Aminzadeh et al. / INTEGRATION, the VLSI journal 41 (2008) 183–192 187
In this case, we have:
n ¼tSS
1=bGBW¼ f ðeSS; x
00;PMÞ. (26)
The analysis for extracting the exact relationship hasbeen carried out in Appendix B in details. The result that isshown in (B.8) is not linear and cannot be expressed withconventional mathematical functions in a closed format.Consequently, MATLAB is used to numerically find thetime-constant coefficient for predetermined values of PM,x00 and eSS. The final values are shown in Table 1 foreSS ¼ 0.05%. The results for PM ¼ 891 are also presentedin this table to be compared with the results of (6) (forsingle-stage opamps with PM ¼ 901). As it is seen, they areapproximately the same.
By training a Radial Basis Function (RBF) neuralnetwork with numerical values obtained in MATLAB,the 3D surface of Fig. 3 is obtained. As it can be seen bothin Table 1 and Fig. 3, there is a minimum point for thetime-constant coefficient somewhere around PM ¼ 701
Table 1
Time constant coefficient (n) vs. phase margin (PM) and effective damping
factor (x00) for small-signal settling error (eSS) equal to 0.05%
PM x00
0.5 0.6 0.7 0.8 0.9 1
101 295.3 90.63 59.812 49.348 42.507 40.573
201 130.06 58.24 40.293 33.145 31.34 29.613
301 74.584 40.149 28.578 24.329 22.581 20.889
401 44.963 26.911 18.919 16.956 15.41 15.832
501 27.573 17.466 12.284 10.87 11.218 9.8727
551 21.612 12.689 9.4958 8.2693 8.7534 9.1247
601 16.201 9.7662 7.0011 7.2211 6.507 6.8769
651 11.427 7.128 4.8382 5.2276 5.6526 6.0463
701 7.2782 5.6927 4.7437 4.1885 4.1078 4.76
751 6.1976 5.8045 5.6007 5.4397 5.2231 5.1993
801 6.4961 6.3998 6.3373 6.2932 6.2622 6.2398
851 7.0286 7.0103 6.9987 6.9917 6.9868 6.9837
891 7.4857 7.4851 7.4848 7.4845 7.4844 7.4843
Tim
e-C
onst
ant C
oeff
icie
nt
1
50
100
150
200
250
0
Effective Damping Factor00.20.40.60.8
020
4060
80100
Phase Margin (˚)
Fig. 3. Time-constant coefficient (n) vs. phase margin (PM) and effective
damping factor (x00) for small-signal settling error (eSS) equal to 0.05%.
and x00 ¼ 0:9. Although the required GBW for a given tSin that point is minimized, it may not be the best choice forpower optimization. A more optimized point will beobtained later.For the case that the second-stage slew-rate is dominant,
it might be useful to say that the relation between GBW
and tS is not the same as (12). In Fig. 2, this occurs when[8]:
ITail
CC4
2IL
CC þ CL, (27)
where IL is the second-stage bias current. With the second-stage SR being dominant one can show that:
2IL ¼ ðCC þ CLÞSR ¼gmi
GBWþ CL
� �VSwing=tLS. (28)
Hence the GBW can be written as:
GBW ¼n
bþ
VSwing
2IL=gmi
� �1
tS � CLVSwing=2IL. (29)
4. The proposed design methodology
It is now possible to present a simple well-defined designmethodology for two-stage cascode-compensated opampsbased on the derived equations. But it is essential to specifysome parameters before applying the methodology. Theseparameters are the load and the compensation capacitors(CL,CC), the total settling time (tS), the overdrive voltageof input transistors (Veffi), the feedback factor (b), theopen-loop DC gain (A0), the peak-to-peak output voltageswing (VSwing) and finally the total settling error (eSS,t).With eSS,t, b and also A0 in hand, the small-signal error canbe obtained from (3). The optimized value of time-constantcoefficient with its corresponded effective damping factorand phase margin should also be determined. The designprocedure starts with determining the required transcon-ductance for input transistors to satisfy the requiredsettling time:
gmi ¼ CCn
bþ
VSwing
V effi
� �1
tS. (30)
This equation is obtained by combining (12) with (25).Now by substituting o0n0 and also x00o
0n0 with their
corresponding values from (20) into (24) and performingsome routine algebra, the relations between gmC, gmL andgmi can be obtained:
An initial value for the parasitic capacitor of the firststage (CB) is required for calculation. In fact, it can then be
ARTICLE IN PRESS
p2
H. Aminzadeh et al. / INTEGRATION, the VLSI journal 41 (2008) 183–192188
updated during simulation. After determining gmi, gmC andgmL, the tail current of the first stage amplifier can beobtained from:
ITail ¼ 2I i ¼ gmiV effi ¼ CCV effin
bþ
VSwing
V effi
� �1
tS. (33)
The current of the second stage can then be derived byequating the second-stage slew-rate with the first-stageslew-rate:
SR1 ¼ SR2 ) IL ¼1
21þ
CL
CC
� �ITail. (34)
The current of the folded branch in such two-stageopamps which have their first stage folded can then beobtained by choosing a reasonable value for the foldedbranch transistors (MCs) overdrive voltage and using (31).
Since for a constant overdrive voltage, the transconduc-tance of MOS transistors is linearly proportional to theirbias currents (when biased in saturation region), in order tominimize the power consumption, the optimized PM andx00 are obtained such that the following summation isminimized:
Ptot / gmiV effi þ gmCV effC þ gmLV effL. (35)
As in the right-hand side of (35), only small-signalparameters are observable it might be thought that thisoptimization just minimizes the power consumption whichrelates to the small-signal section of the response. But as inderiving (30)–(32), both linear and nonlinear sections aretaken into account, minimizing (35) somehow optimizesthe total power. Based on this observation, MATLAB isused to find the optimized point such that (35) isminimized. The corresponding point is approximatelyplaced somewhere around PM ¼ 651 and x00 ¼ 0:7. Itsposition does not strongly dependant on the feedbackfactor or the small-signal settling error (it is always locatedsomewhere around PM ¼ [651,701] and x00 ¼ [0.6,0.7]). Thevalues of time-constant coefficient (n) for different small-signal settling errors in the highlighted point are presentedin Table 2 to facilitate further utilizations of themethodology. As it is seen in Table 2, by decreasing therequired accuracy of the closed-loop topology, the time-constant coefficient also decreases. This in turn reduces the
Table 2
Time-constant coefficient vs. small-signal settling error (eSS) for phase
margin (PM) and effective damping factor (x00) equal to 651 and 0.7,
needed GBW and gmi for a particular value of settling time.A lower gmi also lowers the required values of gmC and gmL.As a result, less accurate opamps can be integrated bylower power consumptions and smaller areas.
5. Simulation results
Circuit-level results were obtained using BSIM3 0.18 mmmixed-signal 1P6M, 1.8V models using HSpice. To verifythe effectiveness of the derived equations, an opamp withthe structure shown in Fig. 2 was designed. The opamp isthen employed in the unity-gain flip-around sample-and-hold amplifier (SHA) illustrated in Fig. 4. In this structure,sampling capacitors (CSs) are charged by the input in thesampling phase (p1). The output voltage is then forced tosettle to the input sampled signal by the stored charge whenthe capacitors are connected to the output in the holdingphase (p2). In p2, the opamp load capacitance including theoutput stage transistors parasitics, the next stage inputcapacitance and the serial result of SHA samplingcapacitance with opamp input parasitic capacitance (Cin)was approximately 5 pF. According to the noise con-straints, the compensation capacitors were chosen equal to3 pF. The required dynamic range also makes us to choosethe peak-to-peak output voltage swing of the SHA equal to1.5Vp–p. The overdrive voltage of input transistors was alsochosen to be 0.3V. Regarding the needed accuracy in50MS/s sampling frequency, the required small-signalsettling error was calculated to be less than 0.05% in10 ns settling time. In addition, as it was proposed inSection 4, the phase margin and the effective dampingfactor values were chosen equal to 651 and 0.7, respectively.From Table 2, the required time-constant coefficient (n)was obtained to be 4.83. Using (30), the input transistorstransconductance was obtained as gmi ¼ 2.95mA/V.The transconductance of cascode transistors was also
calculated from (31) to be gmC ¼ 13.64mA/V. At last, byassuming an initial value for CB equal to 1 pF, thetransconductance of the second-stage input transistorswas obtained to be gmL ¼ 6.18mA/V. According to the
Fig. 6. Nominal settling behavior of the designed SHA.
6 7 8 9 10 11 12 13 140
5
10
1
20
2
30
Time (ns)
Iteration = 100 Mean = 9.676 ns Sigma = 0.7378 ns
Fig. 7. Statistical distribution of 0.1% settling time resulting from 100
Monte Carlo simulations due to local mismatches.
H. Aminzadeh et al. / INTEGRATION, the VLSI journal 41 (2008) 183–192 189
actual value of CB this value was revised throughsimulations to be gmL ¼ 6.51mA/V. Simulation resultsfor the same transconductance values are shown in Table 3.In fact, in this circuit, the feedback factor of the SHA in theholding phase is obtained from:
b ¼CS
CS þ Cin. (36)
The nominal opamp loop-gain frequency response isshown in Fig. 5. Fig. 6 depicts the nominal settlingbehavior of the SHA. The nominal settling time illustratedin Table 3 is calculated for 0.1% total error (correspondingto 0.05% small-signal settling error) and for the full-swingdifferential voltage. As it is seen, the SHA settling behaviorand its settling time match very well with the expectedresults.
The robustness of the designed SHA against mismatcheswas also considered through simulations. To confirm that theacquired settling time is rather insensitive to mismatches,Monte Carlo simulations have been performed. Fig. 7illustrates the 0.1% settling time distribution for 100iterations, assuming 3. Sigma ¼ 1% capacitor mismatcherror and taking into account the circuit parametermismatches according to the transistor dimensions. Themean value of the settling time is 9.676ns with a standarddeviation of 0.738ns. The effect of compensation capacitormismatches to the open-loop GBW of the opamp was alsoinvestigated. The mean value of the GBW is 147.44MHz witha standard deviation of 360KHz.
The efficiency of the proposed methodology is alsoconfirmed during the design of a switched-capacitoramplifier shown in Fig. 8. In this figure, CS and CF arethe sampling and feedback capacitors, respectively. Both ofthem are charged by the input in the sampling phase (p1).Then in the amplification phase (p2), the total storedcharge is transferred to CF when CS is connected to theinput common mode (VCM) and CF to the output. Thefeedback factor of this topology (in p2) is equal to:
b ¼CF
CF þ CS þ Cin. (37)
A multiply-by-two amplifier (with ideal b ¼ 0.5) isdesigned by setting CS ¼ CF. A Class-AB two-stagefolded-cascode opamp is used for the amplifier [6]. Theopamp structure is depicted in Fig. 9. In this topology,
additional class-AB capacitors are employed to charge anddischarge the load capacitor faster. As a result, the secondstage slew-rate will not become dominant. Moreover, as
ARTICLE IN PRESS
+
-
-
+
Vin
VCM,i
p1
p1
p1
p1
p1
p1
p2
p2
CS
CS
CF
CF
p1
+
- -
+
VOp2
p2VCM
Cin
Cin
Fig. 8. The employed switched-capacitor amplifier.
ML1+
MC+
Mi+M
i–
VCMFB
Vin+ V
in–
CL
CL
VO–
MC–
VB1
MTail
CCC
C
VO+C
ABC
AB
AA
BB
ML2+
ML1–
ML2–
VDD
VB2
VB2
Fig. 9. The two-stage Class-AB folded-cascode opamp employed in the
switched-capacitor amplifier.
Table 4
Simulated and calculated results
Parameter Simulation Calculation
Feedback factor 0.49 0.5
Peak-to-peak swing (Vp-p) 1.8 1.8
DC Gain (dB) 78 80
Effective damping factor 0.613 0.6
Phase margin (1) 67.34 70
Nominal GBW (MHz) 512 530
Total settling error (%) 0.04 0.04
Nominal settling time (ns) 5.816 6
VSwing = 1.8 Vp-p
0 1 2 3 4 5 6 7 80
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Time (ns)
Out
put (
V)
Fig. 10. Nominal settling behavior of the designed switched-capacitor
amplifier.
H. Aminzadeh et al. / INTEGRATION, the VLSI journal 41 (2008) 183–192190
the transistors of the second-stage (ML1 and ML2) areemployed to amplify the first-stage output signal, the totalload transconductance value (gmL) that is determined by(32) becomes gmL1+gmL2. Therefore, implementation oflarge gmL values becomes possible with lower biasingcurrents. However, as there is no remaining node for thecommon-mode feedback voltage in the second stage,auxiliary amplifiers are required to sustain common-modesignals in their nominal values [8].
Another advantage of this topology is the fact that thefirst-stage cascode transistors (MCs) and the input transis-tors are not located at a same branch. Hence, the choice oftheir transconductances and overdrive voltages can bemore relaxed. But extra current is required to bias thecascode transistors.
The amplifier was designed to satisfy the requiredspecification. The load capacitors were approximatelyequal to 15 pF. The compensation capacitors have alsobeen chosen equal to 6 pF. The peak-to-peak outputvoltage swing was equal to 1.8Vp–p. The required small-signal settling error was calculated to be less than 0.02% in6 ns total settling time. The phase margin and effectivedamping factor were chosen to be 701 and 0.6, respectively.The amplifier opamp was designed according to theproposed methodology. Table 4 compares the simulatedand calculated results. Fig. 10 depicts the nominal settlingbehavior of the amplifier.
At last, it is important to note that although both of thesimulated circuits were fully differential, but the methodol-ogy is not limited to such structures. In other words, it ispossible to design and optimize single-ended topologies bythe proposed methodology as well. This has also beenobserved in simulations.
6. Conclusion
A fundamental analysis based on the settling time ofoperational amplifiers has been performed both for single-stage and two-stage cascode-compensated architectures. Byconsidering the effect of zeros in the cascade-compensatedopen-loop transfer function, the optimized relationshipbetween gain-bandwidth product and settling time isobtained. The relationships between gain-bandwidth pro-duct, settling time and open-loop parameters are alsoderived. The results are used to propose a straightforwarddesign methodology for high-speed two-stage cascode-compensated opamps. Simulation results confirm that theproposed design procedure is able to meet all the givenspecifications. The advantages of this methodology are:
�
The methodology is based upon the optimized rela-tionship between settling time and open-loop para-meters. Hence, it can be very helpful in the design of
ARTICLE IN PRESSH. Aminzadeh et al. / INTEGRATION, the VLSI journal 41 (2008) 183–192 191
switched-capacitor circuits without much blind effort onadjusting open-loop parameters.
� The methodology is straightforward and flexible and
can be easily utilized in an analog knowledge-basedCAD tool.
� The effect of zeros in the transfer function has not been
ignored.
Appendix A
As it was mentioned formerly, approximation (18) mightnot hold true if the zeros are located at relatively lowerfrequencies. The details of the analysis leading to (18) havebeen presented in this Appendix A. Based upon theanalysis, a constraint for the magnitude of zeros such thatthe error in approximation (18) remains negligible issuggested. Eq. (17) can be written as:
1þ sð2x00=o0n0Þ þ s2=o0n0
2¼
1þ sð2x0=on0Þ þ s2=o2n0
1� s2=z2
¼ ð1þ sð2x0=on0Þ þ s2=o2n0Þ 1þ
s2
z2þ
s4
z4þ
s6
z6þ � � �
� �.
ðA:1Þ
Therefore we can write:
1þ sð2x00=o0n0Þ þ s2=o0n0
2¼ 1þ sð2x0=on0Þ
þ s2ð1=z2 þ 1=o2n0Þ þ s3ð2x0=ðon0z
2Þ
þ s4ð1=z4 þ 1=o2n0z
2Þ þ s5ð2x0=ðon0z4ÞÞ
þ s6ð1=z6 þ 1=o2n0z
4Þ þ � � � . ðA:2Þ
As a result:
1þ sð2x00=o0n0Þ þ s2=o0n0
2¼ 1þ sð2x0=on0Þ
� 1þs2
z2þ
s4
z4þ � � �
� �þ s2ð1=z2 þ 1=o2
n0Þ
� 1þs2
z2þ
s4
z4þ � � �
� �¼ 1þ ðsð2x0=on0Þ þ s2ð1=z2 þ 1=o2
n0ÞÞ
� 1þs2
z2þ
s4
z4þ � � �
� �. ðA:3Þ
As it is seen in (A.3), we should be able to ignore theterm ð1þ s2=z2 þ s4=z4 þ � � �Þ. As we are only interested onthe frequencies up to the loop-gain transient frequency(which is approximately equal to bGBW) we can sets ¼ jo ¼ jbGBW to imply this term as:
1þðjbGBW Þ2
z2þðjbGBW Þ4
z4þ � � � ¼ 1�
b2GBW 2
z2
þb4GBW 4
z4� � � � . ðA:4Þ
For an error less than 10%, the largest term should besmaller than 0.1. Therefore, we can obtain the following
constraint for the magnitude of zeros:
b2GBW 2
z2o0:1) jzj4
ffiffiffiffiffi10p
bGBW . (A.5)
Appendix B
The equivalent definition of time-constant coefficient as(6) in two-stage cascode-compensated opamps is derivedhere. The goal is to obtain a relationship between thisparameter and open-loop specifications. In contrary with(6) for first-order systems, due to the complexity of theequations governing the settling behavior of a third-ordersystem, the relationship between time-constant coefficient,small-signal settling error and open-loop parameters isnon-linear and complicated. The required analysis has beenperformed in [9] and the relations between open-loop andclosed-loop parameters of third-order systems are obtainedthere. By employing the Taylor expansion of zeros indenominator and ignoring their effect in nominator of theopen-loop transfer function, the settling error is obtainedfrom [5,6,9]:
Denoting od as the closed-loop dominant pole, a isobtained from:
a ¼od
xon. (B.3)
In above equations, x and on are the closed-loopdamping factor and natural frequency, respectively; therelationship between these two parameters and open-loopspecifications are [9]:
ARTICLE IN PRESSH. Aminzadeh et al. / INTEGRATION, the VLSI journal 41 (2008) 183–192192
As it is seen in (B.1), (B.4) and (B.7), when the phasemargin, effective damping factor and small-signal settlingerror are specified, a, x and W ¼ ontSS can numerically beobtained. After these parameters are specified, (B.6) can beused to obtain the time-constant coefficient:
n ¼tSS
1=bGBW¼
axW
1þ 2ax2¼ f ðeSS; x
00;PMÞ. (B.8)
References
[1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-
Hill, 2001.
[2] K.N. Leung, P.K.T. Mok, Analysis of multistage amplifier frequency
compensation, IEEE Trans. Circuits Systems I: Fund. Theory 48 (9)
(2001) 1041–1056.
[3] B.K. Ahuja, An improved frequency compensation technique for
CMOS operational amplifiers, IEEE J. Solid-State Circuits 18 (1983)
629–633.
[4] P.J. Hurst, S.H. Lewis, J.P. Keane, F. Aram, K.C. Dyer, Miller
compensation using current buffers in fully differential CMOS two-
stage operational amplifiers, IEEE Trans. Circuits Systems I: Fund.
Theory 51 (2) (2004) 275–285.
[5] A. Feldman, High-speed, low-power sigma-delta modulators for RF
base-band channel applications, Ph.D. Dissertation, University of
California, Berkeley, 1997.
[6] R. Lotfi, M. Taherzadeh, M. Yaser Azizi, O. Shoaei, Low power
design for low-voltage fast-settling operational amplifier in switched
capacitor applications, integration, VLSI J. 36 (2003) 175–189.
[7] M. Waltari, Circuit techniques for low-voltage and high-speed A/D
converters, Ph.D. Dissertation, Helsinki University of Technology,
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[8] S. Rabii, B.A. Wooley, A 1.8-V digital-audio sigma-delta modulator in
0.8-mm CMOS, IEEE J. Solid-State Circuits 32 (6) (1997) 783–796.
[9] A. Marques, Y. Geerts, M. Steyaert, W. Sansen, Settling time analysis
of third-order systems, Proceedings of the IEEE International
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505–508.
Hamed Aminzadeh was born in Mashhad, Iran, in
1982. He received his B.Sc. and M.Sc. degrees
(with honors) in 2004 and 2006, respectively, both
in Electronics Engineering. His research interests
include: design of low-voltage low-power analog
and mixed-signal integrated circuits for CMOS
sub-micron technologies and digitally calibrated
analog-to-digital and digital-to-analog converters.
He has been the author and co-author of several
conference and journal papers.
Mohammad Danaie was born in Mashhad, Iran,
in 1982. He received his B.S. degree in Electrical
Engineering from the Ferdowsi University of
Mashhad in 2005 with honors. He is currently an
M.Sc. student in Ferdowsi University of Mash-
had working on mathematical modeling of
photonic crystals. His research interests include:
low-power analog circuit design, CMOS analog-
to-digital converters and photonic crystals.
Reza Lotfi was born in Mashhad, I.R. Iran in
1977. He received his B.Sc. degree from the
Ferdowsi University of Mashhad (FUM), Mash-
had, Iran, in 1997 (with honors), the M.Sc. degree
from Sharif university of Technology, Tehran,
Iran, in 1999, and the PhD from the University of
Tehran, Tehran, Iran, in 2004 all in Electrical
Engineering.
He was with EMAD Semicon, Tehran, Iran, as
a Senior Design Engineer from 1998-2003 work-
ing on low-voltage analog and mixed-signal integrated circuits for wireless
receivers and with NIKTEK, Tehran, Iran, from 2003–2007 as a Senior
Design Engineer and Project Manager working on high-speed high-
resolution data converters. Since 2004, he has joined FUM as an assistant
and director of Integrated Systems Lab (ISL). He has also been a Guest
Lecturer in several institutions. His research interests include: low-voltage
low-power analog and mixed-signal integrated circuits, high-speed and
high-resolution data converters and RF integrated systems.
Dr. Lotfi was awarded the Outstanding Graduating Student award in
FUM in 1997 and an International Kharazmi Youth Innovation Festival
