Digital Electronics (2131004) B.E. 3rd SEMESTER

Digital Electronics

(2131004)

B.E. 3rd SEMESTER

LABORATORY MANUAL

2014

Compiled by Guided by

Nitin J. Bathani Dr. K. R. Parmar

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

L.D.COLLEGE OF ENGINEERING, AHMEDABAD.

CERTIFICATE

This is to certify that Mr. /Ms.

_____________________________________________ Roll No.

_______________ and Enrolment no._______________________ Of fourth

semester of B.E____________________ Class has satisfactorily completed

his/her one full semester in “2131004 DIGITAL ELECTRONICS”

satisfactorily in partial fulfilment of Bachelor of Electronics and

communication Engineering degree to be awarded by Gujarat Technological

University.

H.O.D

Faculty – (E&C Department)

Date: - …. /… /…….

L.D. College of Engineering EC Department

Digital Electronics| Compiled By :- Nitin Bathani 1

LIST OF EXPERIMENTS Lab Name of Experiments Pg Date of

performan

ce

Asses

sment

Faculty

Signature

1. To study and implement logic gates

by using transistors as well as ICs.

12

2. Implement Boolean function

F=xy+x’y’+y’z using AOI logic as

well as Universal GATES

16

3. To construct a full subtractor using

Demultiplexer IC 74182

18

4. To construct a 4 bit X-OR GATE

by using 8*1 multiplexer.

20

5. To construct and verify logic

diagram of BCD adder using IC

74283.

22

6. To implement decimal to binary

converter by using priority encoder

74148 and represent decimal no.

into seven segment display.

25

7. To Design mod-4 Counter using J-K

Flip-Flop.

27

8. To study shift register using IC 7495

in all its modes i.e.

SIPO/SISO, PISO/PIPO.

29

9. To verify the Function table of 4 bit

ALU - IC 74181.

34

10 To study and find out the logic gate

parameters of any ICs

37

11 Project:

41



Integrated Circuits

IC No. Description

74LS00 Quad 2-Input NAND Gate

74LS01 Quad 2-Input NAND Gate; Open Collector Outputs

74LS02 Quad 2-Input NOR Gate

74LS03 Quad 2-Input NAND Gate; Open Collector Outputs

74LS04 Hex Inverter

74LS05 Hex Inverter; Open Collector Outputs

74LS06 Hex Inverter; Open Collector High Voltage Outputs

74LS07 Hex Buffer; Open Collector High Voltage Outputs

74LS08 Quad 2-Input AND Gate

74LS09 Quad 2-Input AND Gate; Open Collector Outputs

74LS10 Triple 3-Input NAND Gate

74LS11 Triple 3-Input AND Gate

74LS12 Triple 3-Input NAND Gate; Open Collector Outputs

74LS13 Dual 4-Input NAND Schmitt Triggers

74LS14 Hex Schmitt-Trigger Inverter

74LS15 Triple 3-Input AND Gate; Open Collector Outputs

74LS16 Hex Inverter; Open Collector 15V Outputs

74LS17 Hex Driver; Open Collector 15V Outputs

74LS19 NAND Schmitt Trigger; Totem Pole Output

74LS20 Dual 4-Input NAND Gate

http://www.skot9000.com/ttl/datasheets/0.pdf






















74LS21 Dual 4-Input AND Gate; Open Collector Outputs

74LS22 Dual 4-Input NAND Gate; Open Collector Outputs

74LS23 2x Four input NOR with Strobe

74LS25 2x Four input NOR with Strobe

74LS26 Quad 2-Input NAND Gate; OC (15V)

74LS27 Triple 3-Input NOR Gate

74LS28 Quad 2-Input NOR Gates

74LS30 8-Input NAND Gate

74LS31 Delay Element

74LS32 Quad 2-Input OR Gate

74LS33 Quad 2-Input NOR Gate; Open Collector Outputs

74LS37 Quad 2-Input NAND Gates

74LS38 Quad 2-Input NAND Gates; Open Collector Outputs

74LS39 4x Two input NAND, Open collector

74LS40 Dual 4-Input NAND Gates

74LS42 BCD to DECIMAL Decoder

74LS45 Four-to-Ten (BCD to Decimal) DECODER, High current

74LS46 BCD to Seven-Segment DECODER, Open Collector, lamp test and leading zero handling

74LS47 BCD to 7-Segment Decoder; Open Collector Outputs (15V)

74LS48 BCD to 7-Seg Decoder; Outputs Active high

74LS49 BCD to 7-Seg Decoder-Outputs Active High

74LS50 2x (Two input AND) NOR (Two input AND), expandable

74LS51 Dual AND-OR-INVERT Gates
























74LS53 NOR of Four Two input ANDs, expandable

74LS54 4-Wide AND-OR-INVERT Gate

74LS55 4-Wide; 2-Input AND-OR-INVERT Gate

74LS56 Frequency Divider

74LS57 Frequency Divider

74LS64 4-3-2-2 AND-OR-INVERT

74LS65 4-3-2-2 AND-OR-INVERT

74LS68 Dual 4-Bit Decade or Binary Counter

74LS69 Dual 4-Bit Decade or Binary Counter

74LS70 1x gated JK FLIPFLOP with preset and clear

74LS72 1x gated JK FLIPFLOP with preset and clear

74LS73 Dual J-K Flip-Flop

74LS74 Dual D-Type Flip-Flop

74LS75 Dual 2-Bit D-Type Flip-Flop


74LS77 4-Bit D-Type Latch


74LS83 4-Bit Full Adder

74LS85 4-Bit Comparator

74LS86 Quad Exclusive OR Gate

74LS90 Decade Counter

74LS91 8-Bit Shift Register

74LS92 Divide-By-12 Counter























74LS93 4-Bit Binary Counter

74LS94 Four bit SHIFT register

74LS95 4-Bit Shift Register with Parallel Inputs and Outputs

74LS96 5-Bit Shift Register with Parallel Inputs and Outputs

74LS107 Dual J-K Master Slave Flip-Flop


74LS112 Dual J-K Flip-Flop with Preset and Clear



74LS116 2x Four bit LATCH with clear

74LS121 Monostable Multivibrator

74LS122 Retriggerable Monostable Multivibrator


74LS124 2x Clock Generator or Voltage Controlled Oscillator

74LS125 Quad Line Driver; 3-State Outputs

74LS126 Quad Line Driver; 3-State Outputs

74LS128 4x Two input NOR, Line driver


74LS132 Quad 2-Input NAND Schmitt Trigger

74LS133 13-Input NAND Gate

74LS134 Twelve input NAND, Tri-state

74LS135 4x Two input XOR (exclusive or)

74LS136 Quad 2-Input Exclusive OR Gates


















74LS137 3-Line to 8-Line Demultiplexer with Address Latch

74LS138 3-Line to 8-Line Demultiplexer

74LS139 2-Line to 4-Line Decoder/Demultiplexer

74LS140 2x Four input NAND, 50 ohm Line Driver

74LS143 Four bit counter and latch with 7-segment LED driver

74LS145 BCD to Decimal Decoder/Driver

74LS147 10-Line to 4-Line Priority Encoder


74LS150 16-1 SELECTOR (multiplexer)

74LS151 8-Line to 1-Line Multiplexer

74LS153 Dual 4-Line to 1-Line Multiplexer

74LS154 4-Bit Binary Decoder/Demultiplexer

74LS155 Dual 2-Bit Binary Decoders/Demultiplexer

74LS156 Dual 2-Bit Binary Decoders/Demultiplexer

74LS157 Quad 2-Line to 1-Line Multiplexer

74LS158 Quad 2-Line to 1-Line Multiplexer

74LS159 4-16 DECODER (demultiplexer), Open collector

74LS160 4-Bit Synchronous Programmable Counter




74LS164 8-Bit Shift Register with Parallel Outputs

74LS165 8-Bit Shift Register with Parallel Inputs























74LS166 8-Bit Shift Register with Parallel Inputs

74LS168 Up/Down 4-Bit Synchronous Counter

74LS169 Up/Down 4-Bit Synchronous Counter

74LS170 16-Bit RAM; Open Collector Outputs

74LS173 4-Bit Quad D-Type Flip-Flops; 3-State Outputs

74LS174 Hex D-Type Flip-Flop

74LS175 Quad D-Type Flip-Flop

74LS180 Four bit parity checker

74LS181 4-bit Arithmetic Logic Unit

74LS182 Look Ahead Carry Generator

74LS183 Dual Carry-Save Full Adder

74LS190 Synchronous Up/Down Decade Counter

74LS191 Synchronous Up/Down 4-Bit Binary Counter

74LS192 Synchronous Up/Down Decade Counter

74LS193 Synchronous Up/Down 4-Bit Binary Counter

74LS194 4-Bit Bidirectional Shift Register

74LS195 4-Bit Parallel-Access Shift Register

74LS196 Programmable Decade Counter

74LS197 Programmable Decade Counter

74LS198 Eight bit parallel in and out bidirectional SHIFT register

74LS199 Eight bit parallel in and out bidirectional SHIFT register, JK serial input

74LS221 Dual Monostable Multivibrator; Schmitt-Trigger Input

74LS240 Octal Inverting Buffer/Transciever; 3-State Outputs






















74LS241 Octal Buffer/Transciever; 3-State Outputs

74LS242 Quad 3-State Bus Transceiver

74LS243 4-Bit Bidirectional Bus Driver

74LS244 Octal 3-State Noninverting Buffer

74LS245 Octal 3-State Noninverting Bus Transceiver

74LS247 BCD to 7-Seg Decoder/Display Driver OC (15V)



74LS251 8-Line to 1-Line Multiplexer; 3-State Outputs

74LS253 Dual 4-Input Data Selecttor/Multiplexer 3-State

74LS256 Dual 4-Bit Addressable Latch

74LS257 Quad 2-Line to 1-Line Multiplexers; 3-State Outputs

74LS258 Quad 2-Line to 1-Line Multiplexers; 3-State Outputs

74LS259 8-Bit Adressable Latch

74LS260 Dual 5-Input NOR Gate

74LS266 Quad Exclusive NOR Gate

74LS269 8-BIT BIDIRECTIONAL BINARY COUNTER

74LS273 Octal D-Type Flip-Flop; Common Clock and Clear

74LS279 Quad SR-Flip-Flops

74LS280 9-Bit Parity checker

74LS283 4-Bit Full Adder

74LS290 4-Bit Decade/Binary Counter

74LS298 Quad 2-Line to 1-Line Multiplexers with Latch


























74LS299 8-Bit Bidirectional Universal Shift Register

74LS322 8-Bit Sign-Extend Shift Register

74LS323 8-Bit Universal Shift Register with Latch

74LS348 8-Line to 3-Line Priority Encoder with 3-State Outputs

74LS352 Dual 4-Line to 1-Line Multiplexers

74LS353 Dual 4-Line to 1-Line Multiplexers with 3-State Outputs

74LS365 Hex Bus Line Drivers

74LS366 3-State Hex Line Driver

74LS367 Hex Bus Line Drivers

74LS368 Hex Inverting Bus Line Drivers

74LS373 Octal D-Type Latch

74LS374 Octal D-Type Flip-Flop

74LS375 Quad D-Type Latch

74LS377 Octal D-Type Flip-Flop

74LS378 Hex D-Type Flip-Flop

74LS379 Quad D-Type Flip-Flop

74LS386 Quad 2-Input Exclusive OR Gates

74LS390 Dual Decade Counters

74LS393 Dual Decade Counters

74LS395 4-Bit Shift Register with 3-State Outputs

74LS398 Quad 2-Input Register

74LS399 Quad 2-Input Register

74LS490 Dual Decade Counter


























74LS521 8-BIT IDENTITY COMPARATOR

74LS533 Octal D-Type Transparent Latche

74LS534 Octal Invering D-Type Flip-Flop

74LS538 1-OF-8 DECODER WITH 3-STATE OUTPUTS

74LS540 8-Bit Inverting Line Driver

74LS541 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

74LS543 OCTAL REGISTERED TRANSCEIVER, NON-INVERTING, 3-STATE

74LS544 OCTAL REGISTERED TRANSCEIVER, INVERTING, 3-STATE

74LS568 4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS)

74LS569 4-Bit Synchronous Counter

74LS574 8-Bit D-Type Flip-Flop/Bus Driver

74LS579 8-BIT BIDIRECTIONAL BINARY COUNTER (3-STATE)

74LS620

OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS (INVERTING AND

NONINVERTING)

74LS623 Octal Bus Transcievers

74LS629 Voltage Controlled Oscilator

74LS640 Octal Bus Transciever

74LS646 Octal Bus Transciever

74LS648 Octal Bus Transciever/Register

74LS657

OCTAL BIDIRECTIONAL TRANSCEIVER WITH 8-BIT PARITY GENERATOR

CHECKER (3-STATE OUTPUTS)

74LS669 4-Bit Synchronous Up/Down Counter

74LS670 4-By-4 Register File; 3-State Outputs

74LS682 8-Bit Magnitude/Identity Comparator

























74LS684 8-Bit Magnitude Comparators

74LS688 8-Bit Magnitude Comparators


74LS779 8-BIT BIDIRECTIONAL BINARY COUNTER (3-STATE)

74LS795 Octal Buffer with 3-State Outputs

74LS848 8-Line to 3-Line Priority Encoder with 3-State Outputs

74LS2245 25Ohm Octal Bidirectional Transceiver With 3-State Inputs and Outputs

74LS3893

QUAD FUTUREBUS BACKPLANE TRANSCEIVER (3 STATE + OPEN

COLLECTOR)









5-2

FAST AND LS TTL DATA

QUAD 2-INPUT NAND GATE

• ESD > 3500 Volts

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 5474

4.54.75

5.05.0

5.55.25

V

TA Operating Ambient Temperature Range 5474

–550

2525

12570

°C

IOH Output Current — High 54, 74 –0.4 mA

IOL Output Current — Low 5474

4.08.0

mA

SN54/74LS00


LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1

ORDERING INFORMATION

SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC

141

D SUFFIXSOIC

CASE 751A-02

5-3


SN54/74LS00

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

S b l P

Limits

U i T C di iSymbol Parameter Min Typ Max Unit Test Conditions

VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs

VIL Input LOW Voltage54 0.7

VGuaranteed Input LOW Voltage for


Vp g

All Inputs

VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIHVOH Output HIGH Voltage74 2.7 3.5 V

CC , OH , IN IHor VIL per Truth Table

VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VIN = VIL or VIHVOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA

VIN = VIL or VIHper Truth Table

IIH Input HIGH Current20 µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH Current0.1 mA VCC = MAX, VIN = 7.0 V

IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V

IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

ICC

Power Supply CurrentTotal, Output HIGH 1.6 mA VCC = MAXICCTotal, Output LOW 4.4

mA VCC MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)

S b l P

Limits


tPLH Turn-Off Delay, Input to Output 9.0 15 ns VCC = 5.0 V

tPHL Turn-On Delay, Input to Output 10 15 nsCC

CL = 15 pF

5-2



• ESD > 3500 Volts

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA

SN54/74LS00


LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1



141

D SUFFIXSOIC

CASE 751A-02

5-3


SN54/74LS00


S b l P

Limits






Vp g

All Inputs











ICC


mA VCC MAX



S b l P

Limits




CL = 15 pF

5-1


HEX INVERTER

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA

SN54/74LS04

HEX INVERTER

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1



141

D SUFFIXSOIC

CASE 751A-02

5-2


SN54/74LS04


S b l P

Limits






Vp g

All Inputs











ICC

Power Supply CurrentTotal, Output HIGH 2.4 mA VCC = MAXICC p

Total, Output LOW 6.6

mA VCC MAX



S b l P

Limits




CL = 15 pF

5-1


QUAD 2-INPUT AND GATE

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA

SN54/74LS08

QUAD 2-INPUT AND GATE

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1



141

D SUFFIXSOIC

CASE 751A-02

5-2


SN54/74LS08


S b l P

Limits






Vp g

All Inputs











ICC


mA VCC MAX



S b l P

Limits




CL = 15 pF

5-1


DUAL 4-INPUT NAND GATE

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA

SN54/74LS20

DUAL 4-INPUT NAND GATE

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1



141

D SUFFIXSOIC

CASE 751A-02

5-2


SN54/74LS20


S b l P

Limits






Vp g

All Inputs











ICC

Power Supply CurrentTotal, Output HIGH 0.8 mA VCC = MAXICC p

Total, Output LOW 2.2

mA VCC MAX



S b l P

Limits




CL = 15 pF

5-1


QUAD 2-INPUT OR GATE

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA

SN54/74LS32

QUAD 2-INPUT OR GATE

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1



141

D SUFFIXSOIC

CASE 751A-02

5-2


SN54/74LS32


S b l P

Limits






Vp g

All Inputs











ICC


mA VCC MAX



S b l P

Limits


tPLH Turn-Off Delay, Input to Output 14 22 ns VCC = 5.0 V


CL = 15 pF

5-1


BCD TO 7-SEGMENTDECODER/DRIVER

The SN54/74LS47 are Low Power Schottky BCD to 7-Segment Decod-er /Drivers consisting of NAND gates, input buffers and seven AND-OR-IN-VERT gates. They offer active LOW, high sink current outputs for drivingindicators directly. Seven NAND gates and one driver are connected in pairsto make BCD data and its complement available to the seven decodingAND-OR-INVERT gates. The remaining NAND gate and three input buffersprovide lamp test, blanking input / ripple-blanking output and ripple-blankinginput.

The circuits accept 4-bit binary-coded-decimal (BCD) and, depending onthe state of the auxiliary inputs, decodes this data to drive a 7-segment displayindicator. The relative positive-logic output levels, as well as conditionsrequired at the auxiliary inputs, are shown in the truth tables. Outputconfigurations of the SN54/74LS47 are designed to withstand the relativelyhigh voltages required for 7-segment indicators.

These outputs will withstand 15 V with a maximum reverse current of250 µA. Indicator segments requiring up to 24 mA of current may be drivendirectly from the SN74LS47 high performance output transistors. Displaypatterns for BCD input counts above nine are unique symbols to authenticateinput conditions.

The SN54/74LS47 incorporates automatic leading and/or trailing-edgezero-blanking control (RBI and RBO). Lamp test (LT) may be performed at anytime which the BI /RBO node is a HIGH level. This device also contains anoverriding blanking input (BI) which can be used to control the lamp intensityby varying the frequency and duty cycle of the BI input signal or to inhibit theoutputs.

• Lamp Intensity Modulation Capability (BI/RBO)• Open Collector Outputs• Lamp Test Provision• Leading/Trailing Zero Suppression• Input Clamp Diodes Limit High-Speed Termination Effects

14 13 12 11 10 9

1 2 3 4 5 6

VCC

7

16 15

8

f g a b c d e

B C LT BI / RBO RBI D A GND

CONNECTION DIAGRAM DIP (TOP VIEW)

PIN NAMES LOADING (Note a)

HIGH LOW

A, B, C, DRBILTBI /RBO

a, to g

BCD InputsRipple-Blanking InputLamp-Test InputBlanking Input orRipple-Blanking OutputOutputs

0.5 U.L.0.5 U.L.0.5 U.L.0.5 U.L.1.2 U.L.

Open-Collector

0.25 U.L.0.25 U.L.0.25 U.L.0.75 U.L.

2.0 U.L.15 (7.5) U.L.

NOTES:a) 1 Unit Load (U.L.) = 40 µA HIGH, 1.6 mA LOW.b) Output current measured at VOUT = 0.5 V

The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial (74) Temperature Ranges.

SN54/74LS47

BCD TO 7-SEGMENTDECODER/DRIVER

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 620-09

N SUFFIXPLASTIC

CASE 648-08

161

16

1



161

D SUFFIXSOIC

CASE 751B-03

LOGIC SYMBOL

VCC = PIN 16GND = PIN 8

7 1 2 6 3 5

13 12 11 10 9 15 14 4

A B C D LT RBI

a b c d e f gBI/RBO

INPUTS OUTPUTS

TRUTH TABLE

5-2


SN54/74LS47

14 15

LOGIC DIAGRAM

NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS

0 1 2 3 4 5 6 7 8 9 10 11 12 13

INPUT

BLANKING INPUT ORRIPPLE-BLANKINGOUTPUT

RIPPLE-BLANKINGINPUT

LAMP-TESTINPUT

A

B

C

D

a a

b b

c c

d d

e e

f f

g g

OUTPUT

DECIMALOR

FUNCTIONLT RBI D C B A BI/RBO a b c d e f g NOTE

0 H H L L L L H L L L L L L H A

1 H X L L L H H H L L H H H H A

2 H X L L H L H L L H L L H L

3 H X L L H H H L L L L H H L

4 H X L H L L H H L L H H L L

5 H X L H L H H L H L L H L L

6 H X L H H L H H H L L L L L

7 H X L H H H H L L L H H H H

8 H X H L L L H L L L L L L L

9 H X H L L H H L L L H H L L

10 H X H L H L H H H H L L H L

11 H X H L H H H H H L L H H L

12 H X H H L L H H L H H H L L

13 H X H H L H H L H H L H L L

14 H X H H H L H H H H L L L L

15 H X H H H H H H H H H H H H

BI X X X X X X L H H H H H H H B

RBI H L L L L L L H H H H H H H C

LT L X X X X X H L L L L L L L D

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

NOTES:(A) BI/RBO is wire-AND logic serving as blanking Input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held

at a HIGH level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blankingof a decimal 0 is not desired. X = input may be HIGH or LOW.

(B) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level regardless of the state ofany other input condition.

(C) When ripple-blanking input (RBI) and inputs A, B, C, and D are at LOW level, with the lamp test input at HIGH level, all segment outputsgo to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition).

(D) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level, and a LOW level is applied to lamp test input,all segment outputs go to a LOW level.

5-3


SN54/74LS47




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C

IOH Output Current — High BI /RBO 54, 74 –50 µA

IOL Output Current — Low BI /RBOBI /RBO

5474

1.63.2

mA

VO (off) Off-State Output Voltage a to g 54, 74 15 V

IO (on) On-State Output Current a to gOn-State Output Current a to g

5474

1224

mA


S b l P

Limits


VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Theshold Voltagefor All Inputs


VGuaranteed Input LOW Threshold Voltage


Vp g

for All Inputs


VOH Output HIGH Voltage BI /RBO 2 4 4 2 VVCC = MIN, IOH = –50 µA,

VOH Output HIGH Voltage, BI /RBO 2.4 4.2 V CC , OH µ ,VIN = VIN or VIL per Truth Table

VOLOutput LOW Voltage 54, 74 0.25 0.4 V IOL = 1.6 mA VCC = MIN, VIN = VIN or

VOLp g

BI /RBO 74 0.35 0.5 V IOL = 3.2 mACC , IN IN

VIL per Truth Table

IO (off)Off-State Output Currenta thru g 250 µA

VCC = MAX, VIN = VIN or VIL per TruthTable, VO (off) = 15 V

VO (on)On-State Output Voltage 54, 74 0.25 0.4 V IO (on) = 12 mA VCC = MAX, VIN = VIH

V T th T blVO (on)p g

a thru g 74 0.35 0.5 V IO (on) = 24 mACC IN IH

or VIL per Truth Table



IILInput LOW Current BI /RBOAny Input except BI /RBO

–1.2–0.4 mA VCC = MAX, VIN = 0.4 V

IOS BI /RBO Output Short Circuit Current (Note 1) –0.3 –2.0 mA VCC = MAX, VOUT = 0 V

ICC Power Supply Current 7.0 13 mA VCC = MAX



S b l P

Limits


tPHLtPLH

Propagation Delay, AddressInput to Segment Output

100100

nsns VCC = 5.0 V

tPHLtPLH

Propagation Delay, RBI InputTo Segment Output

100100

nsns

VCC 5.0 VCL = 15 pF

AC WAVEFORMS

VIN

VOUT

1.3 V 1.3 V

1.3 V 1.3 V

tPHL tPLH

Figure 1 Figure 2

1.3 V 1.3 V

1.3 V1.3 V

tPLHtPHL

VIN

VOUT

5-1


QUAD 2-INPUTEXCLUSIVE OR GATE

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND

TRUTH TABLE

IN OUT

A B Z

L L LL H HH L HH H L




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA

SN54/74LS86

QUAD 2-INPUTEXCLUSIVE OR GATE

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1



141

D SUFFIXSOIC

CASE 751A-02

5-2


SN54/74LS86


S b l P

Limits






Vp g

All Inputs











ICC Power Supply Current 10 mA VCC = MAX



S b l P

Limits


tPLHtPHL

Propagation Delay,Other Input LOW

1210

2317 ns

VCC = 5.0 V

tPLHtPHL

Propagation Delay,Other Input HIGH

2013

3022 ns

CCCL = 15 pF

5-1


4-BIT SHIFT REGISTER

The SN54/74LS95B is a 4-Bit Shift Register with serial and parallelsynchronous operating modes. The serial shift right and parallel load are acti-vated by separate clock inputs which are selected by a mode control input.The data is transferred from the serial or parallel D inputs to the Q outputssynchronous with the HIGH to LOW transition of the appropriate clock input.

The LS95B is fabricated with the Schottky barrier diode process for highspeed and is completely compatible with all Motorola TTL families.

• Synchronous, Expandable Shift Right• Synchronous Shift Left Capability• Synchronous Parallel Load• Separate Shift and Load Clock Inputs• Input Clamp Diodes Limit High Speed Termination Effects

NOTE:The Flatpak version has thesame pinouts (ConnectionDiagram) as the Dual In-LinePackage.



14 13 12 11 10 9

1 2 3 4 5 6

8

7

VCC Q0 Q1 Q2 Q3 CP1 CP2

DS P0 P1 P2 P3 S GND


HIGH LOW

S Mode Control Input 0.5 U.L. 0.25 U.L.DS Serial Data Input 0.5 U.L. 0.25 U.L.P0–P3 Parallel Data Inputs 0.5 U.L. 0.25 U.L.CP1 Serial Clock (Active LOW Going Edge) Input 0.5 U.L. 0.25 U.L.CP2 Parallel Clock (Active LOW Going Edge) Input 0.5 U.L. 0.25 U.L.Q0–Q3 Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L.

NOTES:a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

Temperature Ranges.




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA

SN54/74LS95B

4-BIT SHIFT REGISTER

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1



141

D SUFFIXSOIC

CASE 751A-02

5-2


SN54/74LS95B

LOGIC DIAGRAM

Q0 Q1 Q2 Q3

S

DS

CP1

CP2

P0 P2 P3

R

S Q

P1

R

S Q

R

S Q

R

S Q


= PIN NUMBERS

6

1

2 3

8

4 5

9

1112 1013

FUNCTIONAL DESCRIPTION

The LS95B is a 4-Bit Shift Register with serial and parallelsynchronous operating modes. It has a Serial (DS) and fourParallel (P0–P3) Data inputs and four Parallel Data outputs(Q0–Q3). The serial or parallel mode of operation is controlledby a Mode Control input (S) and two Clock Inputs (CP1) and(CP2). The serial (right-shift) or parallel data transfers occursynchronous with the HIGH to LOW transition of the selectedclock input.

When the Mode Control input (S) is HIGH, CP2 is enabled. AHIGH to LOW transition on enabled CP2 transfers paralleldata from the P0–P3 inputs to the Q0–Q3 outputs.

When the Mode Control input (S) is LOW, CP1 is enabled. A

HIGH to LOW transition on enabled CP1 transfers the datafrom Serial input (DS) to Q0 and shifts the data in Q0 to Q1, Q1to Q2, and Q2 to Q3 respectively (right-shift). A left-shift is ac-complished by externally connecting Q3 to P2, Q2 to P1, andQ1 to P0, and operating the LS95B in the parallel mode (S =HIGH).

For normal operation, S should only change states whenboth Clock inputs are LOW. However, changing S from LOWto HIGH while CP2 is HIGH, or changing S from HIGH to LOWwhile CP1 is HIGH and CP2 is LOW will not cause any changeson the register outputs.

MODE SELECT — TRUTH TABLE

OPERATING MODEINPUTS OUTPUTS

OPERATING MODES CP1 CP2 DS Pn Q0 Q1 Q2 Q3

ShiftL X I X L q0 q1 q2ShiftL X h X H q0 q1 q2

Parallel Load H X X Pn P0 P1 P2 P3

L L X X No ChangeL L X X No ChangeH L X X No Change

Mode Change H L X X UndeterminedL H X X UndeterminedL H X X No ChangeH H X X UndeterminedH H X X No Change

L = LOW Voltage LevelH = HIGH Voltage LevelX = Don’t CareI = LOW Voltage Level one set-up time prior to the HIGH to LOW clock transition.h = HIGH Voltage Level one set-up time prior to the HIGH to LOW clock transition.Pn = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the Pn= HIGH to LOW clock transition.

5-3


SN54/74LS95B


S b l P

Limits






Vp g

All Inputs









IIL Input HIGH Current –0.4 mA VCC = MAX, VIN = 0.4 V




AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

S b l P

Limits


fMAX Maximum Clock Frequency 25 36 MHzV 5 0 V

tPLH CP to Output18 27 ns

VCC = 5.0 VCL = 15 pFPLH

tPHLCP to Output

21 32 nsCL = 15 pF

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)

S b l P

Limits


tW CP Pulse Width 20 ns

V 5 0 V

ts Data Setup Time 20 ns

V 5 0 Vth Data Hold Time 20 ns VCC = 5.0 V

ts Mode Control Setup Time 20 ns

th Mode Control Hold Time 20 ns

5-4


SN54/74LS95B

DESCRIPTION OF TERMS

SETUP TIME(ts) —is defined as the minimum time requiredfor the correct logic level to be present at the logic input prior tothe clock transition from HIGH to LOW in order to be recog-nized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time following

the clock transition from HIGH to LOW that the logic level mustbe maintained at the input in order to ensure continued recog-nition. A negative HOLD TIME indicates that the correct logiclevel may be released prior to the clock transition from HIGH toLOW and still be recognized.

AC WAVEFORMS

Figure 1

Figure 2

The shaded areas indicate when the input is permitted to change for predictable output performance.

1.3 V 1.3 V 1.3 V 1.3 V

1.3 V

th(H)ts(H)ts(L)

th(L)

tWl/fmax

tPHL tPLH

*The Data Input is(DS for CP1) or (Pn for CP2).

D

CP1 or CP2

Q

1.3 V 1.3 V

1.3 V

1.3 V1.3 V

1.3 V

1.3 V1.3 V

1.3 V 1.3 V

ts(L)

ts(H)th(L)

ts(L)ts(H)

ts(L) ts(H)th(H)

tW

th(L OR H)

STABLE(H → L ONLY)

S

CP1

CP2

tW

1.3 V 1.3 V

1.3 V

1.3 V

(L → H ONLY) (L → H ONLY)

5-1


DUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOP

The SN54/74LS112A dual JK flip-flop features individual J, K, clock, andasynchronous set and clear inputs to each flip-flop. When the clock goesHIGH, the inputs are enabled and data will be accepted. The logic level of theJ and K inputs may be allowed to change when the clock pulse is HIGH andthe bistable will perform according to the truth table as long as minimum set-upand hold time are observed. Input data is transferred to the outputs on thenegative-going edge of the clock pulse.

LOGIC DIAGRAM (Each Flip-Flop)

Q5(9)

CLEAR (CD)15(14)J3(11)

Q6(7)

SET (SD)4(10)

K2(12)

1(13)CLOCK (CP)

MODE SELECT — TRUTH TABLE

OPERATING MODEINPUTS OUTPUTS

OPERATING MODESD CD J K Q Q

SetReset (Clear)*UndeterminedToggleLoad “0” (Reset)Load “1” (Set)Hold

LHLHHHH

HLLHHHH

XXXhlhl

XXXhhll

HLHqLHq

LHHqHLq

* Both outputs will be HIGH while both SD and CD are LOW, but the output statesare unpredictable if SD and CD go HIGH simultaneously.

H, h = HIGH Voltage LevelL, I = LOW Voltage LevelX = Don’t Carel, h (q) = Lower case letters indicate the state of the referenced input (or output)l, h (q) = one set-up time prior to the HIGH to LOW clock transition.

SN54/74LS112A

DUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 620-09

N SUFFIXPLASTIC

CASE 648-08

161

16

1


SN54LSXXXJ CeramicSN74LSXXXN PlasticSN74LSXXXD SOIC

161

D SUFFIXSOIC

CASE 751B-03

LOGIC SYMBOL


4

3

1

2

15

5

6

SDJ

CP

K CDQ

Q

10

11 9

13

12

14

7

SDJ

CP

K CDQ

Q

5-2


SN54/74LS112A




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA


S b l P

Limits






Vp g

All Inputs


V O HIGH V l54 2 5 3 5 V V MIN I MAX V V






IIH Input HIGH Current

J, KSet, ClearClock

206080

µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH CurrentJ, KSet, ClearClock

0.10.30.4

mA VCC = MAX, VIN = 7.0 V

IILInput LOW Current J, K

Clear, Set, Clk–0.4–0.8 mA VCC = MAX, VIN = 0.4 V


ICC Power Supply Current 6.0 mA VCC = MAX



S b l P

Limits


fMAX Maximum Clock Frequency 30 45 MHzV 5 0 V

tPLH Propagation Delay, Clock 15 20 nsVCC = 5.0 VCL = 15 pFPLH

tPHL

p g y,Clear, Set to Output 15 20 ns

CL = 15 pF

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)

S b l P

Limits


tW Clock Pulse Width High 20 ns

V 5 0 VtW Clear, Set Pulse Width 25 ns

VCC = 5 0 Vts Setup Time 20 ns

VCC = 5.0 V

th Hold Time 0 ns

5-1


10-LINE-TO-4-LINEAND 8-LINE-TO-3-LINEPRIORITY ENCODERS

The SN54/74LS147 and the SN54/74LS148 are Priority Encoders. Theyprovide priority decoding of the inputs to ensure that only the highest orderdata line is encoded. Both devices have data inputs and outputs which areactive at the low logic level.

The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implieddecimal zero condition does not require an input condition because zero isencoded when all nine data lines are at a high logic level.

The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). Byproviding cascading circuitry (Enable Input EI and Enable Output EO) octalexpansion is allowed without needing external circuitry.

The SN54/74LS748 is a proprietary Motorola part incorporating a built-indeglitcher network which minimizes glitches on the GS output. The glitchoccurs on the negative going transition of the EI input when data inputs 0–7are at logical ones.

The only dc parameter differences between the LS148 and the LS748 arethat (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 onthe LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have afan-in of 3 on the LS748 versus a fan-in of 2 on the LS148.

The only ac difference is that tPHL from EI to EO is changed from 40 to45 ns.

SN54/74LS147(TOP VIEW)

SN54/74LS148SN54/74LS748

(TOP VIEW)

4 5 6 7 8 C B GND

D 3 2 1 9 AVCC NC

14 13 12 11 10 9

1 2 3 4 5 6 7

16 15

8

D 3 2 1 9

A4

5 6 7 8 C B

OUTPUT INPUTS OUTPUT

INPUTS OUTPUTS

4 5 6 7 E1 A2 A1 GND

VCC EO GS 3 2 1 0 A0

14 13 12 11 10 9

1 2 3 4 5 6 7

16 15

8

EO GS 3 2 1 0

A04

5 6 7 EI A2 A1

OUTPUTS INPUTS OUTPUT

INPUTS OUTPUTS

SN54/74LS147SN54/74LS148SN54/74LS748

10-LINE-TO-4-LINEAND 8-LINE-TO-3-LINEPRIORITY ENCODERS

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 620-09

N SUFFIXPLASTIC

CASE 648-08

161

16

1



161

D SUFFIXSOIC

CASE 751B-03

5-2


SN54/74LS147 • SN54/74LS148 • SN54/74LS748

SN54/74LS147FUNCTION TABLE

INPUTS OUTPUTS

1 2 3 4 5 6 7 8 9 D C B A

H H H H H H H H H H H H HX X X X X X X X L L H H LX X X X X X X L H L H H HX X X X X X L H H H L L LX X X X X L H H H H L L HX X X X L H H H H H L H LX X X L H H H H H H L H HX X L H H H H H H H H L LX L H H H H H H H H H L HL H H H H H H H H H H H L

SN54/74LS148SN54/74LS748

FUNCTION TABLE

INPUTS OUTPUTS

EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO

H X X X X X X X X H H H H HL H H H H H H H H H H H H LL X X X X X X X L L L L L HL X X X X X X L H L L H L HL X X X X X L H H L H L L HL X X X X L H H H L H H L HL X X X L H H H H H L L L HL X X L H H H H H H L H L HL X L H H H H H H H H L L HL L H H H H H H H H H H L H

H = HIGH Logic Level, L = LOW Logic Level, X = Irrelevant

FUNCTIONAL BLOCK DIAGRAMS

SN54/74LS147 SN54/74LS148

1

2

3

4

5

6

7

8

9

(11)

(12)

(13)

(1)

(2)

(3)

(4)

(5)

(10)

(9)

(7)

(6)

(14)

A

B

C

D

0

1

2

3

4

5

6

7

EI

(10)

(11)

(12)

(13)

(1)

(2)

(3)

(4)

(5)

(15)EO

(14)GS

(8)A0

(7)A1

(6)A2

5-3


SN54/74LS147 • SN54/74LS148 • SN54/74LS748

FUNCTIONAL BLOCK DIAGRAMS (continued)

SN54/74LS748

G31

G2

G3

G4

G5

G6

G7

G8

G1

G9

G10

G11

G12

G130

1

2

3

4

5

6

7

EI

(10)

(11)

(12)

(13)

(1)

(2)

(3)

(4)

(5)

(15)EO

(14)GS

(9)A0

(7)A1

(6)A2

G29

G18

G23

G28

5-4


SN54/74LS147 • SN54/74LS148 • SN54/74LS748




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA


S b l P

Limits






Vp g

All Inputs







IIH

Input HIGH CurrentAll OthersInput 0 (LS748)Inputs 1–7 (LS148)Inputs 1–7 (LS748)

20404060


IIHAll OthersInput 0 (LS748)Inputs 1–7 (LS148)Inputs 1–7 (LS748)

0.10.20.20.3


IIL

Input LOW CurrentAll OthersInput 0 (LS748)Inputs 1–7 (LS148)Inputs 1–7 (LS748)

–0.4–0.8–0.8–1.2



ICCH Power Supply Current Output HIGH 17 mA VCC = MAX, All Inputs = 4.5 V

ICCL Output LOW 20 mAVCC = MAX, Inputs 7 & E1 = GNDAll Other Inputs = 4.5 V


5-5


SN54/74LS147 • SN54/74LS148 • SN54/74LS748

AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C)SN54/74LS147

S b lFrom To

W f

Limits

U i T C di iSymbolFrom

(Input)To

(Output) Waveform Min Typ Max Unit Test Conditions

tPLHAny Any

In-phase 12 18ns

C 15 FtPHLAny Any

poutput 12 18

nsCL = 15 pF,

tPLHAny Any

Out-of-phase 21 33ns

L p ,RL = 2.0 kΩ

tPHLAny Any

poutput 15 23

ns

SN54/74LS148SN54/74LS748

S b lFrom To

W f

Limits

U i T C di iSymbolFrom

(Input)To

(Output) Waveform Min Typ Max Unit Test Conditions

tPLH1 thru 7 A0 A1 or A2

In-phase 14 18ns

C 15 F

tPHL1 thru 7 A0, A1, or A2

poutput 15 25

ns

C 15 F

tPLH1 thru 7 A0 A1 or A2

Out-of-phase 20 36ns

C 15 F

tPHL1 thru 7 A0, A1, or A2

poutput 16 29

ns

C 15 F

tPLH0 thru 7 EO

Out-of-phase 7.0 18ns

C 15 FtPHL

0 thru 7 EOp

output 25 40ns

C 15 pFtPLH

0 thru 7 GSIn-phase 35 55

ns

CL = 15 pF,RL = 2.0 kΩ

tPHL0 thru 7 GS

poutput 9.0 21

ns RL = 2.0 kΩ

tPLHEI A0 A1 or A2

In-phase 16 25ns

tPHLEI A0, A1, or A2

poutput 12 25

ns

tPLHEI GS

In-phase 12 17ns

tPHLEI GS

poutput 14 36

ns

tPLHEI EO

In-phase12 21

tPHL EI EOIn-phaseoutput 28

304045

ns (LS148)(LS748)

5-1


8-INPUT MULTIPLEXERThe TTL/MSI SN54/74LS151 is a high speed 8-input Digital Multiplexer.

It provides, in one package, the ability to select one bit of data from up to eightsources. The LS151 can be used as a universal function generator togenerate any logic function of four variables. Both assertion and negationoutputs are provided.

• Schottky Process for High Speed• Multifunction Capability• On-Chip Select Logic Decoding• Fully Buffered Complementary Outputs• Input Clamp Diodes Limit High Speed Termination Effects


14 13 12 11 10 9

1 2 3 4 5 6 7

16 15

8

VCC

I3

I4 I5 I6 I7 S1S0 S2

I2 I1 I0 Z Z E GND


HIGH LOW

S0–S2EI0– I7ZZ

Select InputsEnable (Active LOW) InputMultiplexer InputsMultiplexer Output (Note b)Complementary Multiplexer Output

(Note b)

0.5 U.L.0.5 U.L.0.5 U.L.10 U.L.10 U.L.

0.25 U.L.0.25 U.L.0.25 U.L.

5 (2.5) U.L.5 (2.5) U.L.

NOTES:a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

Temperature Ranges.

SN54/74LS151

8-INPUT MULTIPLEXER

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 620-09

N SUFFIXPLASTIC

CASE 648-08

161

16

1



161

D SUFFIXSOIC

CASE 751B-03

LOGIC SYMBOL


1110

9

6 5

7 4 3 2 1 15 14 13 12

E I0 I1 I2 I3 I4 I5 I6 I7S0S1S2 Z Z

5-2


SN54/74LS151

LOGIC DIAGRAM

S2

S1

S0

E

I0 I1 I2 I3 I4 I5 I6 I7

Z Z

1412

6

7

34

5

9

11

12

10

1315


= PIN NUMBERS


The LS151 is a logical implementation of a single pole,8-position switch with the switch position controlled by thestate of three Select inputs, S0, S1, S2. Both assertion andnegation outputs are provided. The Enable input (E) is activeLOW. When it is not activated, the negation output is HIGHand the assertion output is LOW regardless of all other inputs.The logic function provided at the output is:

Z = E ⋅ (I0 ⋅ S0 ⋅ S1 ⋅ S2 + ⋅ I1 ⋅ S0 ⋅ S1 ⋅ S2 + I2 ⋅ S0 ⋅ S1 ⋅ S2+ I3 ⋅ S0 ⋅ S1 ⋅ S2 + I4 ⋅ S0 ⋅ S1 ⋅ S2 + I5 ⋅ S0 ⋅ S1 ⋅ S2 + I6 ⋅ S0

⋅ S1 ⋅ S2 + I7 ⋅ S0 ⋅ S1 ⋅ S2).The LS151 provides the ability, in one package, to select

from eight sources of data or control information. By propermanipulation of the inputs, the LS151 can provide any logicfunction of four variables and its negation.

TRUTH TABLE

E S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 Z Z

H X X X X X X X X X X X H LL L L L L X X X X X X X H LL L L L H X X X X X X X L HL L L H X L X X X X X X H LL L L H X H X X X X X X L HL L H L X X L X X X X X H LL L H L X X H X X X X X L HL L H H X X X L X X X X H LL L H H X X X H X X X X L HL H L L X X X X L X X X H LL H L L X X X X H X X X L HL H L H X X X X X L X X H LL H L H X X X X X H X X L HL H H L X X X X X X L X H LL H H L X X X X X X H X L HL H H H X X X X X X X L H LL H H H X X X X X X X H L H

H = HIGH Voltage LevelL = LOW Voltage LevelX = Don’t Care

5-3


SN54/74LS151




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA


S b l P

Limits






VGuaranteed Input LOW Voltage forAll Inputs



VCC MIN, IOH MAX, VIN VIHor VIL per Truth Table











S b l P

Limits


tPLHtPHL

Propagation DelaySelect to Output Z

2718

4330 ns

V 5 0 V

tPLHtPHL

Propagation DelaySelect to Output Z

1420

2332 ns

V 5 0 V

tPLHtPHL

Propagation DelayEnable to Output Z

2620

4232 ns

VCC = 5.0 V

tPLHtPHL

Propagation DelayEnable to Output Z

1518

2430 ns

VCC 5.0 VCL = 15 pF

tPLHtPHL

Propagation DelayData to Output Z

2016

3226 ns

tPLHtPHL

Propagation DelayData to Output Z

1312

2120 ns

AC WAVEFORMS

Figure 1 Figure 2

VIN

VOUT

1.3 V

tPHL

1.3 V

1.3 V

tPLH

1.3 V

VIN

VOUT

1.3 V

tPHL

1.3 V 1.3 V

1.3 V

tPLH

TL/F/6394

DM

54LS154/D

M74LS154

4-L

ine

to16-L

ine

Decoders

/D

em

ultip

lexers

May 1989

DM54LS154/DM74LS154 4-Line to 16-LineDecoders/Demultiplexers

General DescriptionEach of these 4-line-to-16-line decoders utilizes TTL circuit-

ry to decode four binary-coded inputs into one of sixteen

mutually exclusive outputs when both the strobe inputs, G1

and G2, are low. The demultiplexing function is performed

by using the 4 input lines to address the output line, passing

data from one of the strobe inputs with the other strobe

input low. When either strobe input is high, all outputs are

high. These demultiplexers are ideally suited for implement-

ing high-performance memory decoders. All inputs are buff-

ered and input clamping diodes are provided to minimize

transmission-line effects and thereby simplify system de-

sign.

FeaturesY Decodes 4 binary-coded inputs into one of 16 mutually

exclusive outputsY Performs the demultiplexing function by distributing data

from one input line to any one of 16 outputsY Input clamping diodes simplify system designY High fan-out, low-impedance, totem-pole outputsY Typical propagation delay

3 levels of logic 23 ns

Strobe 19 nsY Typical power dissipation 45 mW

Connection and Logic Diagrams

Dual-In-Line Package

TL/F/6394–1

Order Number DM54LS154J,

DM74LS154WM or DM74LS154N

See NS Package Number J24A, M24B or N24A

TL/F/6394–2

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range

DM54LS b55§C to a125§CDM74LS 0§C to a70§C

Storage Temperature Range b65§C to a150§C

Note: The ‘‘Absolute Maximum Ratings’’ are those valuesbeyond which the safety of the device cannot be guaran-teed. The device should not be operated at these limits. Theparametric values defined in the ‘‘Electrical Characteristics’’table are not guaranteed at the absolute maximum ratings.The ‘‘Recommended Operating Conditions’’ table will definethe conditions for actual device operation.

Recommended Operating Conditions

Symbol ParameterDM54LS154 DM74LS154

UnitsMin Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.7 0.8 V

IOH High Level Output Current b0.4 b0.4 mA

IOL Low Level Output Current 4 8 mA

TA Free Air Operating Temperature b55 125 0 70 §C

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions MinTyp

Max Units(Note 1)

VI Input Clamp Voltage VCC e Min, II e b18 mA b1.5 V

VOH High Level Output VCC e Min, IOH e Max DM54 2.5 3.4V

Voltage VIL e Max, VIH e MinDM74 2.7 3.4

VOL Low Level Output VCC e Min, IOL e Max DM54 0.25 0.4Voltage VIL e Max, VIH e Min

DM74 0.35 0.5 V

IOL e 4 mA, VCC e Min DM74 0.25 0.4

II Input Current @ Max VCC e Max, VI e 7V0.1 mA

Input Voltage

IIH High Level Input Current VCC e Max, VI e 2.7V 20 mA

IIL Low Level Input Current VCC e Max, VI e 0.4V b0.4 mA

IOS Short Circuit VCC e Max DM54 b20 b100mA

Output Current (Note 2)DM74 b20 b100

ICC Supply Current VCC e Max (Note 3) 9 14 mA

Note 1: All typicals are at VCC e 5V, TA e 25§C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICC is measured with all outputs open and all inputs grounded.

Switching Characteristics at VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)

From (Input)RL e 2 kX

Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units

Min Max Min Max

tPLH Propagation Delay Time Data to30 35 ns

Low to High Level Output Output

tPHL Propagation Delay Time Data to30 35 ns

High to Low Level Output Output

tPLH Propagation Delay Time Strobe to20 25 ns

Low to High Level Output Output

tPHL Propagation Delay Time Strobe to25 35 ns

High to Low Level Output Output

2

Function TableInputs Outputs

G1 G2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

L L L L L L L H H H H H H H H H H H H H H H

L L L L L H H L H H H H H H H H H H H H H H

L L L L H L H H L H H H H H H H H H H H H H

L L L L H H H H H L H H H H H H H H H H H H

L L L H L L H H H H L H H H H H H H H H H H

L L L H L H H H H H H L H H H H H H H H H H

L L L H H L H H H H H H L H H H H H H H H H

L L L H H H H H H H H H H L H H H H H H H H

L L H L L L H H H H H H H H L H H H H H H H

L L H L L H H H H H H H H H H L H H H H H H

L L H L H L H H H H H H H H H H L H H H H H

L L H L H H H H H H H H H H H H H L H H H H

L L H H L L H H H H H H H H H H H H L H H H

L L H H L H H H H H H H H H H H H H H L H H

L L H H H L H H H H H H H H H H H H H H L H

L L H H H H H H H H H H H H H H H H H H H L

L H X X X X H H H H H H H H H H H H H H H H

H L X X X X H H H H H H H H H H H H H H H H

H H X X X X H H H H H H H H H H H H H H H H

H e High Level, L e Low Level, X e Don’t Care

3

5-1


4-BIT ARITHMETICLOGIC UNIT

The SN54/74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which canperform all the possible 16 logic, operations on two variables and a variety ofarithmetic operations.

• Provides 16 Arithmetic Operations Add, Subtract, Compare, Double,Plus Twelve Other Arithmetic Operations

• Provides all 16 Logic Operations of Two Variables Exclusive — OR,Compare, AND, NAND, OR, NOR, Plus Ten other Logic Operations

• Full Lookahead for High Speed Arithmetic Operation on Long Words• Input Clamp Diodes

NOTE:The Flatpak versionhas the same pinouts(Connection Diagram) asthe Dual In-Line Package.


22 21 20 19 18 17

1 2 3 4 5 6 7

24 23

8

VCC

B0

A1 B1 A2 B2 B3A3 G

A0 S3 S2 S1 S0 Cn M9 10 11 12

F0 F1 F2 GND

16 15 14 13

Cn+4 A=BP F3


HIGH LOW

A0–A3, B0–B3S0–S3MCnF0–F3A = BG

P

Cn+4

Operand (Active LOW) InputsFunction — Select InputsMode Control InputCarry InputFunction (Active LOW) OutputsComparator OutputCarry Generator (Active LOW)OutputCarry Propagate (Active LOW)OutputCarry Output

1.5 U.L.2.0 U.L.0.5 U.L.2.5 U.L.10 U.L.

Open Collector10 U.L.

10 U.L.

10 U.L.

0.75 U.L.1.0 U.L.

0.25 U.L.1.25 U.L.

5 (2.5) U.L.5 (2.5) U.L.

10 U.L.

5 U.L.

5 (2.5) U.L.

NOTES:a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)b. Temperature Ranges.

SN54/74LS181

4-BIT ARITHMETICLOGIC UNIT

LOW POWER SCHOTTKY


SN54LSXXXJ CeramicSN74LSXXXN Plastic

LOGIC SYMBOL


7

8

6543

9 10 11 13

15

17

14

16

2 1 23 22 21 20 19 18

CnM

S0S1S2S3

A0 B0 A1 B1 A2 B2 A3 B3

F0 F1 F2 F3

Cn+4A = B

G

P

24

1

J SUFFIXCERAMIC

CASE 623-05

24

1

N SUFFIXPLASTIC

CASE 649-03

5-2


SN54/74LS181

2

LOGIC DIAGRAM

S0 S1 S2 S3

Cn M

A = B Cn+4

A0 B0 A1 A2 A3B1 B2 B3

F0 F1 F2 F3 P G14

1

6

7

3

8

45

9 11 1610 13 15


= PIN NUMBERS

212223 20 1819

17


The SN54/74LS181 is a 4-bit high speed parallel ArithmeticLogic Unit (ALU). Controlled by the four Function Select Inputs(S0 . . . S3) and the Mode Control Input (M), it can perform allthe 16 possible logic operations or 16 different arithmeticoperations on active HIGH or active LOW operands. TheFunction Table lists these operations.

When the Mode Control Input (M) is HIGH, all internalcarries are inhibited and the device performs logic operationson the individual bits as listed. When the Mode Control Input isLOW, the carries are enabled and the device performsarithmetic operations on the two 4-bit words. The deviceincorporates full internal carry lookahead and provides foreither ripple carry between devices using the Cn+4 output, orfor carry lookahead between packages using the signals P(Carry Propagate) and G (Carry Generate), P and G are notaffected by carry in. When speed requirements are notstringent, the LS181 can be used in a simple ripple carry modeby connecting the Carry Output (Cn+4) signal to the Carry Input(Cn) of the next unit. For high speed operation the LS181 isused in conjunction with the 9342 or 93S42 carry lookaheadcircuit. One carry lookahead package is required for eachgroup of the four LS181 devices. Carry lookahead can beprovided at various levels and offers high speed capability

over extremely long word lengths.The A = B output from the LS181 goes HIGH when all four F

outputs are HIGH and can be used to indicate logicequivalence over four bits when the unit is in the subtractmode. The A = B output is open collector and can bewired-AND with other A = B outputs to give a comparison formore then four bits. The A = B signal can also be used with theCn+4 signal to indicate A>B and A<B.

The Function Table lists the arithmetic operations that areperformed without a carry in. An incoming carry adds a one toeach operation. Thus, select code LHHL generates A minus Bminus 1 (2s complement notation) without a carry in andgenerates A minus B when a carry is applied. Becausesubtraction is actually performed by complementary addition(1s complement), a carry out means borrow; thus a carry isgenerated when there is no underflow and no carry isgenerated when there is underflow.

As indicated, the LS181 can be used with either active LOWinputs producing active LOW outputs or with active HIGHinputs producing active HIGH outputs. For either case thetable lists the operations that are performed to the operandslabeled inside the logic symbol.

5-3


SN54/74LS181

FUNCTION TABLE

MODE SELECTINPUTS

ACTIVE LOW INPUTS& OUTPUTS

ACTIVE HIGH INPUTS& OUTPUTS

S3 S2 S1 S0LOGIC(M = H)

ARITHMETIC**(M = L) (Cn = L)

LOGIC(M = H)

ARITHMETIC**(M = L) (Cn = H)

L L L L A A minus 1 A AL L L H AB AB minus 1 A + B A + BL L H L A + B AB minus 1 AB A + BL L H H Logical 1 minus 1 Logical 0 minus 1L H L L A + B A plus (A + B) AB A plus ABL H L H B AB plus (A + B) B (A + B) plus ABL H H L A ⊕ B A minus B minus 1 A ⊕ B A minus B minus 1L H H H A + B A + B AB AB minus 1H L L L AB A plus (A + B) A + B A plus ABH L L H A ⊕ B A plus B A ⊕ B A plus BH L H L B AB plus (A + B) B (A + B) plus ABH L H H A + B A + B AB AB minus 1H H L L Logical 0 A plus A* Logical 1 A plus A*H H L H AB AB plus A A + B (A + B) plus AH H H L AB AB plus A A + B (A + B) Plus AH H H H A A A A minus 1

L = LOW Voltage LevelH = HIGH Voltage Level**Each bit is shifted to the next more significant position**Arithmetic operations expressed in 2s complement notation

LOGIC SYMBOLS

ACTIVE LOW OPERANDS ACTIVE HIGH OPERANDS

7

8

6543

9 10 11 13

15

17

14

16

2 1 23 22 21 20 19 18

CnM

S0S1S2S3

A0 B0 A1 B1 A2 B2 A3 B3

F0 F1 F2 F3

Cn+4A = B

G

P

LS1814 BIT ARITHMETIC

LOGIC UNIT

7

8

6543

9 10 11 13

15

17

14

16

2 1 23 22 21 20 19 18

CnM

S0S1S2S3

A0 B0 A1 B1 A2 B2 A3 B3

F0 F1 F2 F3

Cn+4A = B

G

P

LS1814 BIT ARITHMETIC

LOGIC UNIT




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA

VOH Output Voltage — High (A = B only) 54, 74 5.5 V

5-4


SN54/74LS181


S b l P

Limits






Vp g

All Inputs




V

Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA

V V MINV

p gExcept G and P 74 0.35 0.5 V IOL = 8.0 mA VCC = VCC MIN,

VOL Output G 54, 74 0.7 V IOL = 16 mA

VCC VCC MIN,VIN = VIL or VIHper Truth Table

Output P5474

0.60.5 V IOL = 8.0 mA

per Truth Table

IOH Output HIGH Current 54, 74 100 µAVCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table

IIH

Input HIGH CurrentMode InputAny A or B InputAny S InputCn Input

206080100


IIHMode InputAny A or B InputAny S InputCn Input

0.10.30.40.5


IIL

Input LOW CurrentMode InputAny A or B InputAny S InputCn Input

–0.4–1.2–1.6–2.0



I

Power Supply Current 54 32

A V MAXICC

pp ySee Note 1A 74 34

mA VCC = MAXICC

See Note 1B54 35

mA VCC = MAX

See Note 1B74 37

Note 1.With outputs open, ICC is measured for the following conditions:A. S0 through S3, M, and A inputs are at 4.5 V, all other inputs are grounded.B. S0 through S3 and M are at 4.5 V, all other inputs are grounded.


5-5


SN54/74LS181

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, Pin 12 = GND, CL = 15 pF)

S b l P

Limits


tPLHtPHL

Propagation Delay,(Cn to Cn+4)

1813

2720 ns

M = 0 V, (Sum or Diff Mode)See Fig. 4 and Tables I and II

tPLHtPHL

(Cn to F Outputs)1713

2620 ns

M = 0 V, (Sum Mode)See Fig. 4 and Table I

tPLHtPHL

(A or B Inputs to G Output)1915

2923 ns

M = S1 = S2 = 0 V, S0 = S3 = 4.5 V(Sum Mode) See Fig. 4 and Table I

tPLHtPHL

(A or B Inputs to G Output)2121

3232 ns

M = S0 = S3 = 0 V, S1 = S2 = 4.5 V(Diff Mode) See Fig. 5 and Table II

tPLHtPHL

(A or B Inputs to P Output)2020

3030 ns


tPLHtPHL

(A or B Inputs to P Output)2022

3033 ns


tPLHtPHL

(AX or BX Inputs to FX Output)2113

3220 ns


tPLHtPHL

(AX or BX Inputs to FX Output)2121

3232 ns


tPLHtPHL

(AX or BX Inputs to FXH Outputs)3826 ns


tPLHtPHL

(AX or BX Inputs to FXH Outputs)3838 ns


tPLHtPHL

(A or B Inputs to F Outputs)2226

3338 ns

M = 4.5 V (Logic Mode)See Fig. 4 and Table III

tPLHtPHL

(A or B Inputs to Cn+4 Output)2525

3838 ns

M = 0 V, S0 = S3 = 4.5 V, S1 = S2 = 0 V(Sum Mode) See Fig. 6 and Table I

tPLHtPHL

(A or B Inputs to Cn+4 Output)2727

4141 ns

M = 0 V, S0 = S3 = 0 V, S1 = S2 = 4.5 V(Diff Mode)

tPLHtPHL

(A or B Inputs to A = B Output)3341

5062 ns

M = S0 = S3 = 0 V, S1 = S2 = 4.5 VRL = 2.0 kΩ(Diff Mode) See Fig. 5 and Table II

AC WAVEFORMS

Figure 5 Figure 6

Figure 4

1.3 V 1.3 V

1.3 V1.3 V

1.3 V 1.3 V

1.3 V1.3 V

1.3 V1.3 V

1.3 V1.3 V

1.3 V 1.3 V

INPUT

INPUTA INPUT

B INPUT

tPLH

tPLHtPLH

tPHL

tPHLtPHL

OUTPUT

OUTPUTOUTPUT

5-6


SN54/74LS181

SUM MODE TEST TABLE I FUNCTION INPUTS: S0 = S3 = 4.5 V, S1 = S2 = M = 0 V

P

Input

Other InputSame Bit Other Data Inputs

Output

Parameter

InputUnderTest

Apply4.5 V

ApplyGND

Apply4.5 V

ApplyGND

OutputUnderTest

tPLHtPHL

Al Bl NoneRemaining

A and B Cn Fl

tPLHtPHL

Bl Al NoneRemaining

A and B Cn Fl

tPLHtPHL

Al Bl None CnRemaining

A and B Fl+1

tPLHtPHL

Bl Al None CnRemaining

A and B Fl+1

tPLHtPHL

A B None NoneRemaining

A and B, CnP

tPLHtPHL

B A None NoneRemaining

A and B, CnP

tPLHtPHL

A None BRemaining

BRemaining

A, CnG

tPLHtPHL

B None ARemaining

BRemaining

A, CnG

tPLHtPHL

A None BRemaining

BRemaining

A, CnCn+4

tPLHtPHL

B None ARemaining

BRemaining

A, CnCn+4

tPLHtPHL

Cn None NoneAllA

AllB

Any For Cn+4

5-7


SN54/74LS181

DIFF MODE TEST TABLE II FUNCTION INPUTS: S1 = S2 = 4.5 V, S0 = S3 = M = 0 V

P

Input


Output

Parameter

InputUnderTest

Apply4.5 V

ApplyGND

Apply4.5 V

ApplyGND

OutputUnderTest

tPLHtPHL

A None BRemaining

ARemaining

B, CnFl

tPLHtPHL

B A NoneRemaining

ARemaining

B, CnFl

tPLHtPHL

Al None BlRemaining

B, Cn

RemainingA Fl+1

tPLHtPHL

Bl Al NoneRemaining

B, Cn

RemainingA Fl+1

tPLHtPHL

A None B NoneRemaining

A and B, CnP

tPLHtPHL

B A None NoneRemaining

A and B, CnP

tPLHtPHL


A and Bl, CnG

tPLHtPHL

B None A NoneRemaining

A and B, CnG

tPLHtPHL

A None BRemaining

ARemaining

B, CnA = B

tPLHtPHL

B A NoneRemaining

ARemaining

B, CnA = B

tPLHtPHL


A and B, Cncn+4

tPLHtPHL


A and B, CnCn+4

tPLHtPHL

Cn None NoneAll

A and B None Cn+4

LOGIC MODE TEST TABLE III

P

Input


Output

F i IParameter

InputUnderTest

Apply4.5 V

ApplyGND

Apply4.5 V

ApplyGND

OutputUnderTest Function Inputs

tPLHtPHL

A None B NoneRemaining

A and B, CnAny F

S1 = S2 = M = 4.5 VS0 = S3 = 0 V

tPLHtPHL


A and B, CnAny F

S1 = S2 = M = 4.5 VS0 = S3 = 0 V

5-1


4-BIT BINARY FULL ADDERWITH FAST CARRY

The SN54/74LS283 is a high-speed 4-Bit Binary Full Adder with internalcarry lookahead. It accepts two 4-bit binary words (A1–A4, B1–B4) and aCarry Input (C0). It generates the binary Sum outputs (∑1–∑4) and the CarryOutput (C4) from the most significant bit. The LS283 operates with either ac-tive HIGH or active LOW operands (positive or negative logic).

14 13 12 11 10 9

1 2 3 4 5 6 7

16 15

8

VCC

Σ2

B3 A3 Σ3 A4 Σ4B4 C4

B2 A2 Σ1 A1 B1 C0 GND


NOTE:The Flatpak versionhas the same pinouts(Connection Diagram) asthe Dual In-Line Package.


HIGH LOW

A1–A4 Operand A Inputs 1.0 U.L. 0.5 U.L.B1–B4 Operand B Inputs 1.0 U.L. 0.5 U.L.C0 Carry Input 0.5 U.L. 0.25 U.L.∑1–∑4 Sum Outputs (Note b) 10 U.L. 5 (2.5) U.L.C4 Carry Output (Note b) 10 U.L. 5 (2.5) U.L.

NOTES:a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial

(74) Temperature Ranges.

SN54/74LS283

4-BIT BINARY FULL ADDERWITH FAST CARRY

LOW POWER SCHOTTKY



J SUFFIXCERAMIC

CASE 620-09

N SUFFIXPLASTIC

CASE 648-08

161

16

1

161

D SUFFIXSOIC

CASE 751B-03

LOGIC SYMBOL

5 3 14 12 6 2 15 11

97

4 1 13 10

A1 A2 A3 A4 B1 B2 B3 B4

∑1 ∑2 ∑3 ∑4


C0 C4

5-2


SN54/74LS283

LOGIC DIAGRAM

C0 A1 B1 A2 B2 A3 B3 A4 B4

∑1 ∑2 ∑3 ∑4 C4VCC = PIN 16GND = PIN 8

= PIN NUMBERS

C1 C2 C3

14

1

267 3

4

5

9

1112

1013

15


The LS283 adds two 4-bit binary words (A plus B) plus theincoming carry. The binary sum appears on the sum outputs(∑1–∑4) and outgoing carry (C4) outputs.

C0 + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = ∑1 + 2 ∑2+ 4 ∑3 + 8 ∑4 + 16C4Where: (+) = plus

Due to the symmetry of the binary add function the LS283can be used with either all inputs and outputs active HIGH(positive logic) or with all inputs and outputs active LOW(negative logic). Note that with active HIGH inputs, Carry Inputcan not be left open, but must be held LOW when no carry in isintended.

Example:

C0 A1 A2 A3 A4 B1 B2 B3 B4 ∑1 ∑2 ∑3 ∑4 C4

logic levels L L H L H H L L H H H L L H

Active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1 (10+9=19)

Active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0 (carry+5+6=12)

Interchanging inputs of equal weight does not affect the operation, thus C0, A1, B1, can be arbitrarily assigned to pins 7, 5 or 3.

5-3


SN54/74LS283

FUNCTIONAL TRUTH TABLE

C (n–1) An Bn ∑n Cn

L L L L LL L H H LL H L H LL H H L HH L L H LH L H L HH H L L HH H H H H

C1 – C3 are generated internallyC0 is an external inputC4 is an output generated internally




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA


S b l P

Limits






Vp g

All Inputs







I I HIGH C

C0 20 µAVCC = MAX VIN = 2 7 V

IIH Input HIGH CurrentAny A or B 40 µA

VCC = MAX, VIN = 2.7 V

IIH Input HIGH CurrentC0 0.1 mA

VCC = MAX VIN = 7 0 VAny A or B 0.2 mA


IIL Input LOW CurrentC0 –0.4 mA

VCC = MAX VIN = 0 4 VIIL Input LOW CurrentAny A or B –0.8 mA



ICC

Power Supply CurrentTotal, Output HIGH 34 mA VCC = MAXCCTotal, Output LOW 39

CC


5-4


SN54/74LS283


S b l P

Limits


tPLHtPHL

Propagation Delay, C0 Inputto Any Σ Output

1615

2424 ns

C 15 F

tPLHtPHL

Propagation Delay, Any A or B Inputto Σ Outputs

1515

2424 ns

CL = 15 pF

tPLHtPHL

Propagation Delay, C0 Inputto C4 Output

1111

1722 ns

L pFigures 1 & 2

tPLHtPHL

Propagation Delay, Any A or B Inputto C4 Output

1112

1717 ns

Figure 1 Figure 2

VIN

VOUT

1.3 V

1.3 V

1.3 V

1.3 V

VIN

VOUT

tPHL tPLH tPLH tPHL

AC WAVEFORMS



Experiment-1

Aim: To study and implement logic gates by using transistors as well as

ICs.

Apparatus:

Circuit Diagram:

Sr. No. COMPONENT SPECIFICATION Qty

1. Transistor BC 547 3

2. Resistor Box - 1

3. AND GATE IC 7408 1

4. OR GATE IC 7432 1

5. NAND GATE IC 7400 1

6. NOT GATE IC 7404 1

7. NOR GATE IC 7402 1

8. Bread board - 1



Theory:

Logic gates are electronic circuits which perform logical functions on one or more inputs to produce

one output. There are seven logic gates. When all the input combinations of a logic gate are written in

a series and their corresponding outputs written along them, then this input/ output combination is

called Truth Table. OR, AND and NOT are basic gates. NAND, NOR are known as universal gates.

Various gates and their working is explained here.

AND GATE:

The AND gate performs a logical multiplication commonly known as AND function. The output is

high when both the inputs are high. The output is low level when any one of the inputs is low.

OR GATE:

The OR gate performs a logical addition commonly known as OR function. The output is high when

any one of the inputs is high. The output is low level when both the inputs are low.

NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The output is low when

the input is high.

o

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and any

one of the input is low .The output is low level when both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The output

is low when one or both inputs are high.

X-OR GATE: The output is high when any one of the inputs is high. The output is low when both the inputs are low

and both the inputs are high.

Procedure:

Connect circuit diagram as indicated in figure.

Apply different input and measure output voltage level.

Connect the trainer kit to ac power supply.

Connect the inputs of any one logic gate to the logic sources and its output to the logic

indicator.

Apply various input combinations and observe output for each one.

Verify the truth table for each input/ output combination.

Repeat the process for all other logic gates.

Switch off the ac power supply.



Observation Table:

GATE Symbol Observation Truth table

AND

OR

NAND

NOR

Ex- OR



Ex- NOR

Conclusion:

Sign of Faculty: ________________



Experiment-2

Aim: Implement Boolean function F=xy+x’y’+y’z using AOI logic as

well as Universal GATES

Apparatus:

Theory:

A binary variable can take the value of 0 or 1. A Boolean function is an expression formed with binary

variables, the two binary operators OR and AND, and unary operator NOT, parentheses, and an equal

sign. For a given value of the variables, the function can be either 0 or 1. Boolean function represented

as an algebraic expression may be transformed from an algebraic expression into a logic diagram

composed of AND, OR, and NOT gates. . Every Boolean function can be realized by a And-Or-Not

gates i.e. using AOI logic

Logic Diagram:

(a) Using AOI GATE

(b) Using Universal GATE


1. AND GATE IC 7408 1

2. OR GATE IC 7432 1


4. NOT GATE IC 7404 1


6. Bread board - 1



Procedure:

Connect the trainer kit to ac power supply.

Verify the gates and make connections as per circuit diagram-A.

Apply various input combinations and observe output for each one.

Verify the truth table for each input/ output combination.

Repeat the process for circuit diagram-B.

Switch off the ac power supply.

Truth Table:

Input Output

X Y Z F

Conclusion:

Sign of Faculty: ________________



Experiment-3

Aim: To construct a full subtractor using Demultiplexer IC 74182

Apparatus:

Theory:

The IC 74X154 accepts four active high binary address inputs and provides 16 active low outputs. It

has two enable inputs : E0’ and E1’. These inputs must be low to enable the outputs. Below figure

shows pin description of IC 74X154.

The IC 74X154 can be used as 1 to 16 Demultiplexer by using one of the enable inputs as the

multiplexer data input. When the other enable input is low, the addressed output will follow the state

of applied data. The below table shows the function table of IC 74X154.

Logic Diagram:


1. 4 input NAND GATE IC 7420 1

2. Demultiplexer IC 74X154 1



Procedure:

Connect +5V and ground of all the ICs as per their pin configuration.

Only the first eight pin of the demux will be used.

Input is provided through E and A0 , A1 , A2 , A3 are taken as selection lines.

A3 should be grounded because there are only 3 inputs.

Pass the high outputs of Borrow and Difference through 4 bit NAND gate IC 7420.

Take various values of A1 , A2 and A3 and note down the output.

Truth Table:

Sr No. A3 A2 A1 A0 Borrow Difference

1.

2.

3.

4.

5.

6.

7.

8.

Conclusion:

Sign of Faculty: ________________



Experiment-4

Aim: To construct a 4 bit X-OR GATE by using 8*1 multiplexer.

Apparatus:

Theory:

Multiplexing means transmitting a large number of information units over a smaller number of

channels or lines. A digital multiplexer is a combinational circuit that selects binary information from

one of many input lines and directs it to a single output line. Normally there are 2n input lines and n

selection lines whose bit combinations determine which input is selected.

To implement 4 bit Ex-OR gate, here we are using inputs A, B and C as selection lines and

different logics of input D as the input to the 74151 multiplexer.

Procedure:

Connect Pin-16 of the 74151 multiplexer IC to +5V and Pin-8 to ground.

Feed the logic 0 (0V) or 1(5V) in different combinations at the inputs A, B and C connected as the

DATA SELECT according to truth table.

Connect input D to the DATA INPUT pins D0, D3, D5 and D6.

Connect input D’ to the DATA INPUT pins D1, D2, D4 and D7.

Connect input D’ to the DATA INPUT pins D1, D2, D4 and D7.

Observe and note down the output readings for Y for different combinations of inputs and verify the

truth table for input/output combination

Repeat the process for all logic functions/gates.

Logic Diagram:


1. 4 input NAND GATE IC 7420 1

2. Multiplexer IC 74151 1



Truth Table:

PAIRS A B C D Y= AΦBΦCΦD

1

2

3

4

5

6

7

8

Conclusion:

Sign of Faculty: ________________



Experiment-5

Aim: To construct and verify logic diagram of BCD adder using IC

74283.

Apparatus:

Theory:

The BCD adder is a digital circuit that performs the addition of two BCD numbers. To implement

4-bit BCD adder, we have to cascade two 4-bit binary adder. The two BCD numbers, together with

the input carry, are first added in the top 4-bit binary adder to produce a binary sum.

In BCD adder, when the output carry is equal to zero (i.e. when sum<=9 and Cout=0) it

is directly transferred to IC-2 and nothing is added to the binary sum. When it is equal to one (i.e.

sum>9 or Cout = 1) the sum outputs S3’, S2’, S1’ and carry output are connected through two

AND gates to OR gate add binary 0110 to the binary sum and the inputs are given to bottom 4-bit

binary adder.

Logic Diagram:

Sr.

No.

COMPONENT SPECIFICATION Qty

1. Carry Look Ahead Generator IC 74283 2





Procedure:

Connect +5V and ground of the ICs as per their Pin configuration.

Apply two BCD inputs at input A and B of top 4-bit binary adder IC.

When we provide input through B3, B2, B1, B0, A3, A2, A1, A0, The sum output of two

numbers is obtained from S3 S2 S1 S0 of IC-1.

Connect S3’-S2’ and S3’-S1’ with AND gates and connect their outputs with OR gate.

Then ground two terminals and connect the output of OR-gate to another two terminals of

input B of bottom 4-bit adder IC.

Take various values of A and B and note down the outputs.

Truth Table:

Sr.

No.

A3 A2 A1 A0 B3 B2 B1 B0 Cin S3 S2 S1 S0

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.



15.

16.

Conclusion:

Sign of Faculty: ________________



Experiment-6

Aim: To implement decimal to binary converter by using priority

encoder 74148 and represent decimal no. into seven segment display.

Apparatus:

Sr no component Specification Qty.

1 8×3 encoder IC 74148 1

2 NAND gates IC 7400 1

3 Bread board - 1

4 Seven segment display Common anode 1

5 Seven segment driver IC IC 7447 1

Theory:

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller

number of outputs. The output of a priority encoder is the binary representation of the original number

starting from zero of the most significant input bit. They are often used to control interrupt requests by

acting on the highest priority request.

If two or more inputs are given at the same time, the input having the highest priority will

take precedence. An example of a single bit 4 to 2 encoder is shown, where highest-priority inputs are

to the left and "x" indicates an irrelevant value - i.e. any input value there yields the same output since

it is superseded by higher-priority input. The output V indicates if the input is valid.

I3 I2 I1 I0 O1 O0 V

0 0 0 0 x x 0

0 0 0 1 0 0 1

0 0 1 x 0 1 1

0 1 x x 1 0 1

1 x X x 1 1 1

Procedure:

Connect input to encoder IC to and also connect +5 V and ground.

Connect input to the data input pins as required.

Connect output of encoder to seven segment driver IC

http://en.wikipedia.org/wiki/Electronic_circuit

http://en.wikipedia.org/wiki/Algorithm

http://en.wikipedia.org/wiki/Binary_code

http://en.wikipedia.org/wiki/Interrupt_request

http://en.wiktionary.org/wiki/precedence

http://en.wikipedia.org/wiki/Encoder



Connect seven segment driver IC to seven segment display

Connect input according to logic

Observe and note down the output readings for different combinations of inputs and verify

the truth table

Logic Diagram:

Conclusion:

Sign of Faculty: ________________



Experiment-7

Aim: To Design mod-4 Counter using J-K Flip-Flop.

Apparatus:

Sr No. Component Specification Qty.

1. J-K Flip-Flop IC 74112 1

2. Seven Segment Driver IC 7447 1

3. Voltage Regulator IC 7805 1

4. Bread Board - 1

5. Seven Segment Common Anode 1

6. Function Generator - 1

7. DSO - 1

Theory:

A mod-4 counter is a digital circuit that counts the numbers 0 to 3. We can see this numbers by using

the seven segment. For that purpose we are using J-K Flip-flop IC number 74112. We are using two J-

K Flip-flops for mod-4 counter. We will give clock to the first F/F by using Frequency Generator and

the o/p of first F/F will be the clock for second F/F that is why it is called Asynchronous counter. Both

o/p will be given to the seven segment driver IC 7447. That input will act as the binary number and

7447 will convert binary to decimal. Then we will give that o/p to seven segment and will see the

numbers 0 to 3 are displayed after some delay.

Logic Diagram:



Procedure:

Connect +5V and ground of all the ICs as per their pin configuration.

By using frequency generator give the clock pulse at pin no. 1 of 74112 and short i/p J & K

and give it logic 1 (Vcc=+5V).

Output will be on pin no. 5 and that will be given to clock pulse of 1Hz frequency to second J-

K f/f on pin no. 13.

And by using DSO observes the wave forms of Qa and Qb.

o Fig. Input and Output wave forms Qa and Qb

Output of 74112 will be i/p for 7447 and Qb will be given to pin no.1 of 7447

Connect pin no. 9 to 15 as per seven segment connections from a to f.

Because the frequency of pulse is 1Hz then time delay will be of 1 second.

There is two variables Qa and Qb so the code will be 2-bit binary code and 7447 will convert

that into decimal 0,1,2,3.

Conclusion:

Sign of Faculty: ________________



Experiment-8

Aim: To study shift register using IC 7495 in all its modes i.e.

SIPO/SISO, PISO/PIPO.

Apparatus:


1 Shift Register IC 7495 1


3 Bread board - 1



Theory:

In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output

of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit

that shifts by one position the "bit array" stored in it, shifting in the data present at its input

and shifting out the last bit in the array, at each transition of the clock input.

More generally, a shift register may be multidimensional, such that its "data in" and stage outputs are

themselves bit arrays: this is implemented simply by running several shift registers of the same bit-

length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often configured as

'serial-in, parallel-out' (SIPO) or as 'parallel-in, serial-out' (PISO). There are also types that have both

serial and parallel input and types with serial and parallel output. There are also 'bidirectional' shift

registers which allow shifting in both directions: L→R or R→L. The serial input and last output of a

shift register can also be connected to create a 'circular shift register'.

One of the most common uses of a shift register is to convert between serial and parallel interfaces.

This is useful as many circuits work on groups of bits in parallel, but serial interfaces are simpler to

construct. Shift registers can be used as simple delay circuits. Several bidirectional shift registers could

also be connected in parallel for a hardware implementation of a stack.

SIPO registers are commonly attached to the output of microprocessors when more General Purpose

Input/Output pins are required than are available. This allows several binary devices to be controlled

using only two or three pins, but slower than parallel I/O - the devices in question are attached to the

parallel outputs of the shift register, then the desired state of all those devices can be sent out of the

microprocessor using a single serial connection. Similarly, PISO configurations are commonly used to

add more binary inputs to a microprocessor than are available - each binary input (i.e. a button or more

http://en.wikipedia.org/wiki/Digital_circuit

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

http://en.wikipedia.org/wiki/Clock_signal

http://en.wikipedia.org/wiki/Bit_array

http://en.wikipedia.org/wiki/Parallel_communication

http://en.wikipedia.org/wiki/Serial_communication

http://en.wikipedia.org/wiki/Stack_(data_structure)

http://en.wikipedia.org/wiki/General_Purpose_Input/Output

http://en.wikipedia.org/wiki/General_Purpose_Input/Output



complicated circuitry) is attached to a parallel input of the shift register, then the data is sent back via

serial to the microprocessor using several fewer lines than originally required.

Shift registers can also be used as pulse extenders. Compared to monostable multivibrators, the timing

has no dependency on component values, however it requires external clock and the timing accuracy is

limited by a granularity of this clock. Example: Ronja Twister, where five 74164 shift registers create

the core of the timing logic.

In early computers, shift registers were used to handle data processing: two numbers to be added were

stored in two shift registers and clocked out into an arithmetic and logic unit (ALU) with the result

being fed back to the input of one of the shift registers (the accumulator) which was one bit longer

since binary addition can only result in an answer that is the same size or one bit longer.

Many computer languages include instructions to 'shift right' and 'shift left' the data in a register,

effectively dividing by two or multiplying by two for each place shifted.

Very large serial-in serial-out shift registers (thousands of bits in size) were used in a similar manner

to the earlier delay line memory in some devices built in the early 1970s. Such memories were

sometimes called circulating memory. For example, the Datapoint 3300 terminal stored its display of

25 rows of 72 columns of upper-case characters using fifty-four 200-bit shift registers, arranged in six

tracks of nine packs each, providing storage for 1800 six-bit characters. The shift register design

meant that scrolling the terminal display could be accomplished by simply pausing the display output

to skip one line of characters

Procedure:

Serial In Parallel Out (SIPO) :-

Connections are made as per circuit diagram.

Apply the data at serial i/p

Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.

Apply the next data at serial i/p.

Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the

new data applied will appear at QA.

Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift register.

Serial In Serial Out (SISO):-


Load the shift register with 4 bits of data one by one serially.

At the end of 4th clock pulse the first data ‘d0’ appears at QD.

Apply another clock pulse; the second data ‘d1’ appears at QD.

Apply another clock pulse; the third data appears at QD.

Application of next clock pulse will enable the 4th data ‘d3’ to appear at QD. Thus the

data applied serially at the input comes out serially at QD

http://en.wikipedia.org/wiki/Ronja_Twister

http://en.wikipedia.org/wiki/Arithmetic_logic_unit

http://en.wikipedia.org/wiki/Delay_line_memory

http://en.wikipedia.org/wiki/Datapoint_3300

http://en.wikipedia.org/wiki/Characters_per_line



Logic Diagram:



PISO:



Parallel In Serial Out (PISO) :-


Apply the desired 4 bit data at A, B, C and D.

Keeping the mode control M=1 apply one clock pulse. The data applied at A, B, C and

D will appear at QA, QB, QC and QD respectively.

Now mode control M=0. Apply clock pulses one by one and observe the

Data coming out serially at QD

Parallel In Parallel Out (PIPO):-


Apply the 4 bit data at A, B, C and D.

Apply one clock pulse at Clock 2 (Note: Mode control M=1).

The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.

Conclusion:

Sign of Faculty: ________________



Experiment-9

Aim: To verify the Function table of 4 bit ALU - IC 74181.

Apparatus:


1 4 bit ALU IC 74181 1


3 Bread board - 1



Theory:

In digital electronics, an arithmetic logic unit (ALU) is a digital circuit that performs

arithmetic and logical operations on integer binary numbers. It is a fundamental building block of

the central processing unit found in many digital computers. Powerful and complex ALUs are often

used in modern, high performance CPUs and graphics processing units (GPUs), and in some cases a

single CPU or GPU may contain two or more ALUs. Mathematician John von Neumann proposed the

ALU concept in 1945in a report on the foundations for a new computer called the EDVAC.

The inputs to the ALU are the data to be operated on (called operands) and a code from the control

unit indicating which operation to perform. Its output is the result of the computation. One thing

designers must keep in mind is whether the ALU will operate on big-endian or little-endian numbers.

In many designs, the ALU also takes or generates inputs or outputs a set of condition codes from or to

a status register. These codes are used to indicate cases such as carry-in or carry-out, overflow, divide-

by-zero, etc.

A floating-point unit also performs arithmetic operations between two values, but they do so for

numbers in floating-point representation, which is much more complicated than thetwo's

complement representation used in a typical ALU. In order to do these calculations, a FPU has several

complex circuits built-in, including some internal ALUs.

http://en.wikipedia.org/wiki/Digital_electronics

http://en.wikipedia.org/wiki/Digital_circuit

http://en.wikipedia.org/wiki/Arithmetic

http://en.wikipedia.org/wiki/Logical

http://en.wikipedia.org/wiki/Binary_number

http://en.wikipedia.org/wiki/Central_processing_unit

http://en.wikipedia.org/wiki/Graphics_processing_unit

http://en.wikipedia.org/wiki/John_von_Neumann

http://en.wikipedia.org/wiki/EDVAC

http://en.wikipedia.org/wiki/Operand

http://en.wikipedia.org/wiki/Control_unit

http://en.wikipedia.org/wiki/Control_unit

http://en.wikipedia.org/wiki/Endianness

http://en.wikipedia.org/wiki/Status_register

http://en.wikipedia.org/wiki/Carry_(arithmetic)

http://en.wikipedia.org/wiki/Arithmetic_overflow

http://en.wikipedia.org/wiki/Division_by_zero

http://en.wikipedia.org/wiki/Division_by_zero

http://en.wikipedia.org/wiki/Floating-point_unit

http://en.wikipedia.org/wiki/Floating_point

http://en.wikipedia.org/wiki/Two%27s_complement





In modern practice, engineers typically refer to the ALU as the circuit that performs integer arithmetic

operations (like two's complement and BCD). Circuits that calculate more complex formats

like floating point, complex numbers, etc. usually receive a more specific name such as floating-point

unit (FPU).

Procedure:

Connections are made as shown in the Circuit diagram.

Change the values of the inputs and verify at least 5 functions given in the function

table.


http://en.wikipedia.org/wiki/Binary-coded_decimal

http://en.wikipedia.org/wiki/Floating_point

http://en.wikipedia.org/wiki/Complex_numbers





Conclusion:

Sign of Faculty: ________________



Experiment-10

Aim: To study and find out the logic gate parameters of any ICs

Apparatus:


1 NAND GATE IC 7400 2

2 Function generator - -

3 DSO - -

4 Variable power supply - -

5 NOT GATE IC 7404 5

Theory:

Noise Margin: The transistor-transistor logic (TTL) is the most widely used logic family. The TTL electrical

specifications are usually of interest to the designer of a digital system. A brief discussion of these

characteristics is given below. Input/output characteristics logic gate specification typically include the

following maximum and minimum voltage levels: V = Minimum gate input voltage which will

reliably be recognized as logic 1 (high). V IH = Maximum gate input voltage which will reliably be

recognized as logic 0 (low). VIL = Minimum voltage at the gate output when it is a logic 1 (high). VOL

VOH = Maximum voltage at the gate output when it is a logic 0 (low).

The manufacturer of the gate guarantees that when the input signal Vi is less than VIL, the output Vo

will be greater than VOH under the worst-case conditions. He also guarantees that when Vi exceeds

VIH, the output will be less than VOL under the worstcase conditions.

The voltages VIL VIH, VOL and VOH are specified for input and output current levels not to exceed IIL,

IIH, IOL and IOH respectively. The low-level noise margin NML is defined as:

NML = VIL -VOL

The high-level noise margin NMH is defined as:

NMH = VOH –VIH



Fan out: In practice, the output of one gate is often connected to the input of one or more gates. The fan-out

describes the maximum number of load gates of similar design as the drive gate, that can be connected

to the output of a logic, that is, the driver gate.

Propagation delay time: These times are measured between two reference levels on the input and output voltage waveforms as

shown in figure 6.1. A turn-on delay time (tPHL) is measured as the output changing from a high

voltage level to a low voltage level. The turn-off delay time (tPLH) is measured as the output changing

from low level to a high level. The average propagation delay time is defined as:

𝑡𝑝 = (𝑡𝑝𝐻L + 𝑡𝑝LH)/2



Procedure:

Finding NMl and NMh

For measuring these voltages, following must be done:

Connect the input of a gate to the +5 supply voltage (available on the board), and the

other input to a variable power supply.

Connect the input, supplied by the variable source and the output of the gate, to the

two channels of an oscilloscope as shown in Figure 2.

Change the variable input voltage value to find Voltage Levels of Figure 1. This is

explained in the following paragraphs.

When the voltage of the power supply is at zero, the output of the NAND is in the High state. This output

voltage is VOH (min). Now slowly increase the voltage of the power supply. With a small change in the input

the output voltage will drop slightly. If we further increase the voltage of the supply, a wide band will be

observed on the oscilloscope instead of the narrow line. This wide band is related to the prohibited limit. If

we continue increasing the voltage, the output voltage will jump to its LOW state. In this state the value of the

power supply voltage (input voltage) is VIH (min). Next we set the voltage of power source to +5v, the output

goes to its low state, which is at VOL (max) value. (For measuring this voltage, you should expand the range of

the oscilloscope) Now lowering the voltage of the power supply will cause the output voltage to rise. If we

continue decreasing the input voltage, same wide band will be observed on the oscilloscope. If we continue

decreasing the voltage, a sharp increase will be observed on the output, making it go to its High value. In this

state the input voltage will be equal to VIL (max).

Finding Delay time:



Conclusion:

Sign of Faculty: ________________



Experiment-11

Aim: PROJECT

Title:



Sign of Faculty: ________________

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