Embedded, De-embedded in High speed serial data system

Embedded, De-embedded in High speed serial data system

• Serial Data link analysis and Icon apply 3 gen. HSS

Presented by :David Yang- Technical support manager

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Agenda

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1. Market info

2. SDNA ( Serial Data Network Analyzer) - TDR and ICON

3. Model Application in SDLA feature by feature

4. SDLA features and benefits

Fundamentals of Link Analysis

4/19/2016 SERIAL DATA LINK ANALYSIS 3

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• De-embed measured circuit as needed, to remove the effects of the test fixture, cables and/or the channel to characterize the Transmitter

• Embed the simulated Channel: observe the waveform at the receiver pins

• Emulate the Equalization inside the Rx: observe the waveform at the comparator

Comp.

Result of Channel EffectsTransmitter Performance

Channel Characteristics (S-parameters)

After Equalization

Signal Integrity Issues

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• Loss include dielectric loss and skin effect loss in high speed digital system also impact the signal integrity it will cause the DJ component like ISI

• Control of characteristic impedance is becoming more important as digital system designers seek faster speeds. Mismatches and variations of impedance cause reflections that add to system noise and jitter, especially with fast signals. This can lead to data and logic errors and severe, hard-to-identify reliability problems.

• High speed digital system have high bandwidth will cause high frequency couple -crosstalk

eSerial: DATA is generally transmitted across the interconnect

without any clock in parallel

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Transition points often involve combinations of solder joints, circuit board vias, and connectors: these all can have substantial effect on the total link performance.

Agenda

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1. Market info

2. SDNA( Serial Data Network Analyzer) - TDR and ICON



TDR Fundamentals –Impedance Change

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• An impedance change in the transmission line will cause a change in the amplitude of the propagating step

StepSource

CharacteristicImpedance Z1 = Z0

ImpedanceChange Point

CharacteristicImpedance Z2 > Z0

ImpedanceChange Point

TDR Overview - Typical System

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Incident Step

50

Step Generator

Reflections

Sampler

eSerial: Interconnect itself Characterized using Time Domain Reflectometry (TDR)

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Sampling Scope display of TDR waveform

TDR on an Equivalent Time scope is used to measure the quality of the serial data interconncet: A step is generated and returning reflections are sampled (it’s like radar for serial data cables and boards)

eSerial: Differential TDR is used on differential interconnects.

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Sampling Scope display of two TDR waveforms

Two TDR sampling channels allow the differential impedance between the DATA+ and DATA- eSerial paths to be measured.

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eSerial: TDR is commonly used in design and manufacturing test of eSerial Interconnects

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Time

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Sampling Scope display of TDR waveforms

TDR can test passive eSerial Interconnect to characterize where poor quality will exist when Gbit DATA is sent through it.

Mask test

TDR is a key tool to find where bad interconnect sections may cause poor DATA quality.

TDR Overview

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TDR Waveforms - Open, Short and 50 Termination

AmplitudeOpen (Z =)

(Z = 50)

Short (Z = 0)

Time

Reflected

+ 1

0

- 1 t0 t1

Incident

TDR Overview - Lumped Discontinuities

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System Performance Limited by Interconnect between ICs

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Output Driver

Input Receiver

Package ModelPackage Model

Circuit Board Transmission Line

ICBond WirePackage Lead

Fiberglass Circuit Board

Circuit Board Trace

GOAL: Predict performance by simulating the interface between ICs

Ideal Transmission Line

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• Amount of current is a function of the voltage and the characteristic impedance.

• While the step is propagating, z0 and rsource form a voltage divider.

• Termination determines what happens at the end of the transmission line and what energy, if any, is reflected.

RSOURCE

Z0 = L

I

c

IC Package Example

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Physical Structure

Equivalent SPICE Model

TDR Trace

Bondwire IC

Package

Circuit BoardPin

L1 L2

C

Z0, td

R

subtrate

Circuit Board

TraceBond wire

Coax probe

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TDR Overview - Reflection Coefficient and Impedance

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Rho () = Reflected AmplitudeIncident Amplitude

=Z T - Z 0

Z T+ Z 0

Where ZT represents the trace impedanceZ0is a known impedance

(the characteristic impedance of the TDR system)

is measured by the oscilloscope

Z 0= Z 1 +

1 -

TDR Overview - Measuring Impedance

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Rho () = Reflected StepIncident Step

1 Division5 Divisions

=

= 0.2

RLoad =1 + 1 - Z0

=1 + .2

1 - .250

= 75

200ps/div

div

Cursor 1 at50ReferenceLine

Cursor 2 atReflectionfrom LoadResistor

TDR Resolution

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• No TDR Measurement is Ideal◦ Risetime limited on TDR Measurement Device◦ Interconnect Limited by Parasitics

• TDR Reflection will last as least as long as the Incident Edge

• Insufficient TDR Resolution◦ Rounds out Edges from Discontinuities◦ Causes Two Closely Spaced Discontinuities to be Smoothed

Together◦ May Lead to Mis-Interpretation of TDR Reflection◦ May Lead to Inaccurate Impedance Readings

TDR Resolution Limitations

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• TDR resolution is related to system risetime◦ Reflections last as long as the incident step and display as long as the system risetime

Z1, tDZ0 Z0

Displayed Time

t01 t12

tr(system) 2tD

80E10

80E04

TDR Resolution

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• Resolution FactorsTDR Edge◦ Rise Time◦ Settling Time◦ Foot and Preshoot

• Resolution FactorsInterconnect◦ Cable quality◦ Connector quality◦ Launch quality

Settling Time

Foot

Rise Time

Preshoot

TDR Resolution

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• Rule of Thumb:◦ Two Discontinuities will be Indistinguishable if Separated by less than

Half the System Rise Time

• System Rise Time is Characterized by Fall Time of Reflected Edge from Ideal Short at Test Point

• System Rise Time Approximated by:

T T T TR system R stepgen R sampler R connect( ) ( ) ( ) ( ) 2 2 2inter

TDR Resolution

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80E04 TDR Reflected Rise Time is <35 ps

at Front of Sampling Head

Resolution = 35 ps /2 = 17.5 ps

◦ Air: 5.25 mm

◦ Fiberglass/epoxy circuit boards: ~3 mm

◦ Alumina microcircuits: ~2.5 mm

• 80E08 TDR reflected Rise time is<20ps

• 80E10 TDR reflected Rise time is<12ps

Waveform compare result

80E10

80E04

TDR Accuracy Factors

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• Test System◦ Launch Parasitics◦ Cable Losses◦ Multiple Reflections◦ Interface Transmission Loss

TDR Accuracy - Test System

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• Launch Parasitics◦ Effects are like those of Aberrations in Step and Sampler◦ May not be repeatable

• Cable Losses◦ Apparent Z Increase over Time◦ From Interconnect or DUT◦ Caused mostly by Skin Effect◦ Times Involved can be Very Long

Cable Losses

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TDT response of 1 meter RG-58

100%0.8%/div

5 ns/div


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• Multiple Reflections◦ Can Appear Anywhere in a Waveform◦ Can Look Like Anomaly or Z-shift◦ Are Predictable◦ Might be Controllable

• Interface Transmission Loss

Launch Parasitics

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• The goal is to launch a fast rise time signal and maintain fidelity

• Considerations:◦ Small ground loop◦ Minimum crosstalk◦ Reliable physical connection to the DUT◦ Distance from the ground plane

Launch Parasitics

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Examples of Launch parasitic

Short ground loop Long ground loop

With 80E04 module , 26.5G cable and semi-rigid

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• Interface Transmission Loss◦ Only a Portion of Energy in Step Striking Interface is Transmitted◦ Only a Portion of Reflection Passing Back Through an Interface is

Returned to Source◦ Reduction is Significant when Impedances at Interface are

Substantially Different (e.g. 50 and 90 )

Interface Transmission Loss

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Effect of Multiple Impedance Discontinuities

Z0 = 50 Z1 = 90

(Open)

= 0.918 in a 50 system is 1170 !

1.286

1.286

0.918

1

0.286

Multiple Reflection Issues

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SMA probe

Multiple reflections from stub after probe

Interface Transmission Loss

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• Effects are Linear

• Can be Deconvolved (Iconnect)

• Impedance Readings can be Corrected

• Can Calibrate Once and Subsequent Measurements Corrected

TDR Alternatives

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• Simulation◦ Tools such as Electro provide simulation of impedances for Z-

symmetric geometries◦ Real world issues with variations in geometry, dielectric constant, loss

tangent, etc. must be included◦ Quick and easy for initial design◦ Once built, use TDR to verify and debug impedances

TDR Alternatives

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• Vector Network Analyzer◦ Frequency domain measurement tool◦ Separates and measures incident and reflected energy to device under

test◦ S-parameter domain◦ Correlation to TDR waveforms

)__(11 waveformreflectedTDRt

ffts

IConnect® Software

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SPICE / IBIS Simulation (HSpice, PSpice,

BSpice)

Field Solver Analysis

Accurate validated models

TDR TDS8000

What is IConnect®?

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• IConnect TDR and VNA software for gigabit

• digital interconnects:

◦ Quick signal integrity SPICE modeling and analysis

◦ Easy and accurate S-parameter and eye diagram

measurements

▪ Electrical compliance testing

◦ More accurate impedance measurements

◦ Efficient fault isolation and failure analysis

• MeasureXtractor™

◦ Automatically convert TDR/T or S-parameter data into

exact frequency dependent models

◦ Easily ensure SPICE / IBIS simulation accuracy Efficient, easy-to-use and cost-effective! Works with TDS/CSA8300 TDR scope

Board Trace IConnect® Z-line

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Impedance Accuracy: IConnect Z-line

Multiple reflections in TDR waveform

Scope reads here about 44 Ohm instead of 50 Ohm

Board Trace IConnect® Z-line

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Impedance Accuracy: IConnect Z-line

Accurate impedanceprofile in IConnect®

Impedance, Inductance and Capacitance Readouts

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Impedance Accuracy : IConnect Z-line

Cursors placed

Z, td readL, C read

Package Trace Failure Analysis

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Raw TDR: confusing multiple reflections

Impedance profile in IConnect®:Exact failure location,improved resolution

Z-line Applications and Benefits

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• What does Z-line do?◦ Corrects for multiple reflections inside the DUT, which produce

impedance inaccuracies

• Benefits:◦ Avoid accuracy and disputes with vendors/customers through

improved accuracy and repeatability for PCB impedance measurements▪ Both in manufacturing and in PCB technology development

◦ Locate package, board and connector failures faster through improved resolution

◦ Get quick access to direct Z, td, L and C readouts from the corrected impedance profile


Input Die Capacitance Measurement

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• Measure an empty fixture

• Measure fixture with DUT inside

• IConnect computes Cself based

on the difference

• The same process applies to

package or socket capacitance

Package and Die Capacitance

Cself Applications and Benefits

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• What does Cself/mutual, Lself/mutual computation do?◦ Computes the appropriate values using JEDEC-established industry

standard (JEDEC publication JEP-123) for short interconnects

• Benefits◦ Efficient and quick measurement of input die and package capacitance

▪ A standard method in the semiconductor industry▪ Measurements of the Cdie in powered-up condition possible

Appnote: “Measurement of Input … Die Capacitance … Using TDR”

◦ Method is also efficiently applied to…▪ Small-size package, connector and socket modeling▪ Measuring inductance of a via on the board

Package and Die Capacitance

Eye Diagram In IConnect

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• TDT easily gives the eye diagram degradation◦ Deterministic jitter only◦ Eye degradation due to system losses, ISI, reflections

TDT and IConnect Eye Diagram

Eye Mask and Jitter Measurements

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Correlation

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2^10-1 IConnect eye from TDT measurement

2^10-1 pattern generator measurement


Data courtesy FCI Electronics

IConnect Eye Applications and Benefits

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• What does IConnect eye diagram do it do?

◦ Generates an eye for passive interconnect link – includes crosstalk!

◦ Place standard mask, perform peak-to-peak jitter and eye opening measurements

• Benefits:

◦ Efficient compliance testing for cable assemblies: (SATA, PCI Xpress, Infiniband, Gigabit Ethernet) - save time and money!

▪ No pattern generator (PG) required (at 10 Gbit/sec PG can cost >>$100k vs. <$20k for IConnect!)

▪ Save time: an eye is generated 100x faster than with PG!

▪ Leverage your TDR oscilloscope investment and save test space

◦ Quick isolation of system level problem – rapidly determine whether system performance is poor due to transmitter or to interconnect link

◦ Quick evaluation of maximum performance for a legacy backplane


IConnect® S-parameters

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The easiest way to perform S-parameter measurements for digital interconnects

• Differential, mixed mode, single ended

• Compliance testing for PCI-Xpress, Serial ATA,

Infiniband, Gigabit Ethernet and other standards

• Easily de-embed fixture effects

• Basic calibration capability

Frequency Dependent S-parameters

Correlation with Network Analyzer

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Frequency Dependent S-parameters

MeasureXtractor™

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The fastest path from VNA or TDR measurements to simulations◦ Exact SPICE / IBIS models◦ Automatic model generation◦ Measurement based◦ Frequency dependent◦ PASSIVITY, STABILITY, CAUSALITY ensured

Measurement-Based Modeling

Loss Extraction Results (Transmission)

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Extracted skin effect and dielectric loss parameters

Simulated and measured transmission


Loss Extraction Results (Reflection, Coupled)

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Both self and mutual parameters are extracted


Z-line Modeling in IConnect TDR Software

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* Name: Automatically Generated

.subckt Single port1 port2 gnd_

****** Partition #1

c1 port1 gnd_ 456f

l1 port1 1 1.05n

****** Partition #2

t1 1 gnd_ 2 gnd_ Z0=50.8 TD=125p

…………..

****** Partition #4

t3 3 gnd_ port2 gnd_ Z0=48.2 TD=190p

.ends


Agenda

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1. Market info




Why use Serial Link Analysis ?


• Serial Link Analysis “conditions” or “transforms” the acquired waveform in order to…◦ Remove the effects of the measurement system (fixtures, cables, etc)

to gain back margin in designs ◦ Applies equalization to emulate a receiver to open a closed eye before

analysis ◦ Allow simulation of a signal at a desired test point when direct signal

access is not available ◦ Support compliance testing for next generation standards by following

compliance specifications that require de-embedding, channel embedding and equalization

Understanding SDLA Visualizer Configuring and Running SDLA

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Select Input ModeSpecifies operating mode of SDLA

Configure Measurement Circuit (De-Embed)The Measurement Circuit is used to define the TX output impedance and the physical test and measurement system used to acquire the signal

Configure Simulation Circuit (Embed)The Simulation Circuit is used to define the TX output impedance, embed a simulated channel and to

specify a receiver loadConfigure RX Block (Equalization)

Rx Equalization can be specified as an IBIS-AMI model, OR CTLE and/or DFE/FFE.

Measurement Circuit

Simulation Circuit

Receiver Equalizer

Input ModeSelect Test PointsPoints of visibility within the link

eSerial: DATA is generally transmitted across the interconnect

without any clock in parallel

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Transition points often involve combinations of solder joints, circuit board vias, and connectors: these all can have substantial effect on the total link performance.

Impedance Change-simulation result

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• An impedance change in the transmission line will cause a change in the waveform of the incident waveform that will make your system fail

52ohm 54ohm 150ohm

DDR Reflection RemovalEstimate Transmission Line Delay / Resistance

SALES UNIVERSITY 2012 -TEKTRONIX CONFIDENTIAL PS401 ADVANCED LINK ANALYSIS 62

• Oftentimes probing at the RX Input is not feasible

• Probing is done away from the receiver causing reflections in the acquired signal as shown below

• .

DDR Reflection RemovalRemoving Reflections from DDR signal

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• Use cursor measurement to get delay for round trip reflection.

• Then divide by 2

Td 66ps /Td = 330ps

G= (V2 – V1 ) / V1

G= (1.25 – 0.75 ) / 0.75

R = 200

Emerging Requirements

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• As data rates increase, new requirements are necessary for link analysis tools ◦ Removing effects of test equipment in the context of the users DUT◦ Measuring at the pins of the transmitter or receiver while removing

reflections caused by impedance mismatch◦ Allowing modeling of the DUT in absence of S-Parameters ◦ Accurate modeling of silicon specific equalization algorithms◦ Plots and visual tools to validate the model

• Contact your Tektronix Account Manager for more details on how Tektronix can address these needs…

Reflection RemovalExample of Modeling in a DDR system …

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• Reflections caused by impedance discontinuities at the Rx seen at the probe point make measurements difficult

• Rx model can be compensated for by using either S-Parameter models or estimating the resistance using cursors to get the ratio of reflected to incident voltage…

G= (V2 – V1 ) / V1G= (1.25 – 0.75 ) / 0.75R = 200

Then tune the value of R to get best results. A value of 220 ohms was used.

R = Z0 ( 1 + G ) / (1 - G)Compute Resistance


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• Next the transmission line from the probe point to the Rx needs to be modeled, using S-Parameters or a lossless transmission line model

• For a lossless transmission line- Use cursor measurement to get delay for round trip reflection.

◦ Then divide by 2.Td 66ps /Td = 330ps


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• Using SDLA, the reflections due to the Rx load can be compensated for by

◦ Model the channel from the probe point to the Rx with lossless delay line

◦ Rx package model

◦ Model the Rx load

• Reflections can be removed by the use of simplified set of block models for low speed DDR when S-Parameters are not available

Reflection RemovalDe-Embed Results…

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• After using SDLA reflections are removed from the signal ◦ White is original acquired signal with the reflection.◦ Purple is the de-embedded result showing reflection removal.

Channel Effects

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Sources of Loss– Fixtures– Backplane– Connectors– Vias– Cables

Noise– Data Dependent Noise (DDN)

Jitter– Data Dependent Jitter (DDJ)

Probability of failure– BER Bathtub– BER Eye

Compensate with Equalization

Unequalized

Equalized

eSerial Interconnect: Loss The faster the data rate and the longer the interconnect, then the more loss in the signal

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Reference Maxim Note HFDN-27.0 (Rev. 0, 09/03)

Tx +

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Rcvpath +

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Clean, open, logical 1 & 0 at launch from transmitter

Smeared edges at end of long interconnect.

Logical 1 & 0 can be hard to distinguish at end of long interconnects; (this is often called a “closed eye”)

Click here to go to a detailed backup slide showing pre-emphasis methods used to help overcome interconnect loss and ISI effects.

Fast, sharp, edges at transmitter launch

eSerial Interconnect: Precision Low noise, higher resolution, best fidelity often needed by designer:

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6.25Gb/s at Tx launch into backplane 6.25Gb/s at 17in (43cm) of backplane 6.25Gb/s after 34in (86cm) of backplane

Small differences in levels being measured

Impact of Bandwidth Limitations

• Bandwidth limitations create inter-symbol interference which eventually limit the ability to distinguish one bit from another

Measured eye diagrams from a 40” PCI-Compliance ISI Trace, PRBS-7 Pattern

1.25 Gbps 2.5 Gbps 5.0 Gbps

Noise/jitter closes-down the available headroom in the eye opening

What Happens to Data?• Baseline wander follows consecutive bits in the bit pattern

• Certain bit patterns cause the worst opening

◦ These will have high bit error rates

• Using a 40” PCI-Compliance ISI channel at 5Gbps, PRBS data is significantly distorted

Channel Loss Causes Bit ErrorsPattern Dependent• Here we have found 2,291 bit errors that all happened at this most-distorted bit in the PRBS pattern

Measurement of Pattern Sensitivity

(to PRBS-7 Pattern)

• In these types of channels, we can study bit error locations in the received pattern…

Loss Impact on Jitter Margin

ISI adds to Deterministic JitterRJ remains close to the sameThis closes-down the eye……and makes less margin

At 5Gbps, 53% of eye is lost to jitter

40” ISI Compliance Channel5 Gbps, PRBS-7 pattern

Measurement of Jitter Peak(BER Bathtub)

We want to avoid this…

4GHz 8GHz 10GHz 12GHz 14GHz

Insertion Loss of Channel• Its easy to measure channel insertion loss (S21) with PRBS data…

Measurement of AveragedSingle-Valued Waveform

32-samples per bit

Time-Domain Response with/without channel

FourierTransform

Channel Insertion Loss(S21) – ratio of blue to red

Frequency-Domain Responsewith/without channel

(Singularity because NRZ data has frequency nulls at

octaves of half-bit rate) 2GHz 4GHz 6GHz 8GHz 10GHz 12GHz 14GHz

Ratio

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0GHz

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4GHz 8GHz 10GHz 12GHz 14GHz

Insertion Loss of Channel (continued)•Same can be done with a single step response…

Measurement of AveragedSingle-Valued Waveform32-samples per bit

Time-Domain Response with/without channel

Both PRBSand Step

data yields same loss

2GHz 4GHz 6GHz 8GHz 10GHz 12GHz 14GHz

FourierTransform

Channel Insertion Loss(S21) – ratio of blue to red

Frequency-Domain Responsewith/without channel

Ratio

0GHz

0

-20dB

1.2.

3.4.

2GHz 4GHz 6GHz 8GHz 10GHz 12GHz 14GHz0GHz

0

-20dB

Insertion Loss Measurement Comparison•A common but expensive way to measure insertion loss is with a Vector Network Analyzer (VNA)

Time-Domain(BERTScope,

Sampling Oscilloscope)

(For all these PCIe experiments, a 7.5GHz BW filter was used for the time-domaincaptures, removing this filter increases S21 measurement range to >20GHz)

Measurement of S21On VNA

2GHz 4GHz 6GHz 8GHz 10GHz 12GHz 14GHz

0

-20dB

1.

2.

0GHz

How Could You Correct For This?Linear Signal Processing

Channel

H(f)

T(f) R(f)

T(f) * H(f) = R(f)

Adding another filter, E(f) (equalizer) to the chain, we have

T(f) * H(f) * E(f) = R(f)

So, if E(f) = 1/H(f), then R(f) = T(f) – the ideal condition

Channel

H(f)

T(f) R(f)Eq

E(f)

Channel

H(f)

T(f) R(f)Eq

E(f)

Channel

H(f)

T(f) R(f)Eq

E2(f)

Eq

E1(f)

Where E(f) = E1(f) * E2(f)Or even,

Eq

1.

2.

3. 4.

5.

H(f)

E(f)

De-EmbeddingA Practical PCI Express 3.0 Example


Base Specification Measurements are defined at the pins of the transmitter

Signal access at the pins is often not assessable

De-embedding is required to see what the signal look liked at the pins of the TX, without the added effects of the channel

S-parameters are acquired on the replica channel

Signal at TX Pins Measured Signalat TP1

Apply Sparameters Signal with ChannelEffects Removed

Configuring the Measurement CircuitConfigure De-Embed Block


High Impedance Probe ModeModel PCB trace to the left and the right of the probe in B1-B8Model DUT RX Input Impedance (default 50 ohms) in the Load Block

Within the Probe Block, load the probe S-Parameters and Scope input impedance (default 50 ohms)

SMA ProbeModel PCB trace in B1-B8Model SMA probe (ideal default) and Scope input impedance (default 50 ohms) in Load Block

No ProbeModel PCB trace in B1-B8Model Scope Input Impedance in Load Block

Configuration Options for De-Embed and Embed Blocks


Two S2P files

S4P file

Lossless T Line

RLC Models Two S1P files

Mixed mode to single ended

Probe/Scope SparsOr Two FIR filesOr Two Transfer function files

Equalization: The solution #1:High Frequency “Boost”

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The problem is just what you’d think it would be:To compensate for this channel response …

…you need to boost the

channel so much.

The noise amplification is huge,

and it hurts the improvement

you get (Signal to noise)

De-Embedding ResultsA Practical PCI Express 3.0 Example


Results can be quickly verified after de-embedding

− Signal at TX pins – white

− Signal at TP1 – blue

− Signal after de-embedding from TP1 - Red

The waveforms at the TX pins, at the scope input, and after de-embedding can all be viewed simultaneously

− Allows easy verification/correlation- rise time, pre/under-shoot, ripples

De-Embedding ResultsA Practical PCI Express 3.0 Example


PCI Express 3.0 Base Specification requires measurements at the Tx pins

SDLA and DPOJET enable viewing and measuring the signal at multiple test points simultaneously to validate de-embedding results

− Acquired Signal (Left)

− De-embedded Signal (Center)

− Signal at TX Pins (Right)

De-embedding Considerations


De-embedding amplifies high frequency noise, thus bandwidth limiting is often required

◦ The correct bandwidth is dependent on channel, signal content, board material

Successful de-embedding starts with good quality board design and S-Parameter data

◦ Matched impedance, low loss structures

◦ No gain, significant resonances, or large dips

Quality of de-embedding

◦ Eye height and jitter

◦ Signal to

Noise Ratio

5 GHz 10 GHz

5GHz Filter 10GHz Filter -> Noise amplification

De-embedded rule

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Cut frequency of de-embedded to reduce noise

De-Embedding ConsiderationsBandwidth Control


Bandwidth limiting alone is often not sufficient for de-embedding

The example below shows how a combination of bandwidth limiting and filter roll-off control are used to eliminate a mask violation due to pre-shoot

First, the step and impulse response are show with no bandwidth limiting

The effects of the ripples after the response can been seen in the eye diagram

De-Embedding ConsiderationsBandwidth and Filter Roll-off Control


While other solutions simply allow a bandwidth setting, SDLA enables the control of the filter roll-off

Next, we keep the bandwidth set at 12.5Ghz, but set the stop band frequency to 20GHz, and stop band gain to -20dB. The “Auto” case uses [20GHz, 25GHz, -80dB].

De-Embedding ConsiderationsBandwidth Control


We now see the step response has smaller preshoot/overshoot. This is because the BW limit filter has slower roll off.

The eye diagram no longer shows mask violations

De-Embedding ConsiderationsFinal Comparison with and without Fine Tuning


• Tuning bandwidth to avoid mask violation.

Low bandwidth with no violation.

High bandwidth with violation.

Understanding SDLA VisualizerConfiguring and Running SDLA


Select Input Mode

Specifies operating mode of SDLA

Configure Measurement Circuit (De-Embed)

The Measurement Circuit is used to define the TX output impedance and the physical test and measurement system used to acquire the signal

Configure Simulation Circuit (Embed)

The Simulation Circuit is used to define the TX output impedance, embed a simulated channel and to specify a receiver load

Configure RX Block (Equalization)


Select Test Points

Points of visibility within the link

Select Input Mode








Select Test Points


Receiver Equalizer

Input Mode

Measurement CircuitSimulation Circuit

Configuring the Measurement CircuitConfigure DUT Output Impedance


• TX Block

◦ Configure the DUT TX output impedance (default 50 ohms)

▪ 2 s1p S-Parameter Models or 1 s2p S-Parameter Model

• The output impedance for both the measurement and simulation circuits are configured

◦ The measurement circuit should be the output impedance of the actual DUT

◦ The simulation can be the actual or another impedance profile for doing “what if” scenarios.

Measurement Circuit

Simulation Circuit

Transmitter Equalization De/Pre-emphasis: add or remove emulation

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De-emphasized signal

-0.8

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V

What is Transmitter Equalization or Pre-emphasis, De-emphasis ? Answer: Boosting the signal “edge” at the Tx. In simplest form just boost the 1st

bit after transition – aka Transitional Bit.

Tx Equalization helps open the eye at Rx side

We can:– Add it in emulation– Remove it in emulation– Play scenarios for best

opening at Rx side– Measure it

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Measured Eye out of Tx

Effects of active Pre-emphasis & the need to characterize the pre-emphasis bit

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Reference Maxim Note HFDN-27.0 (Rev. 0, 09/03)



Select Input Mode








Select Test Points


Select Input Mode








Select Test Points


Receiver Equalizer

Input Mode


Configuring the Simulation CircuitConfigure Embed Block


• The simulation circuit setup is identical regardless of the physical probe configuration◦ Model channel characteristics, cables, etc. in B1-B8◦ Model the Rx Input Impedance (default 50 ohms) in the Load Block

SDLA OverviewEmbed the Channel


Most next generation serial standards are “closed eye” requiring embedding of a compliance channel

Probing at the Rx pins is often not possible requiring emulation of the channel before and after the probe point to accurately characterize the Rx input

SDLA allows the user the insert the channel based on its S-parameters

Comp.

Emulated result at the comparator

Embed the channel …… observe the closure.

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Transmitter Performance

ReceiverPerformance

The problem is the channel … Channel exhibits large frequency dependent loss

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Graph from IEEE 802.3ap effort

Loss/dispersion of the channel closes the eye

Receivers now incorporate methods to compensate for loss (equalization)

EmbeddingPCI Express 3.0 Compliance Example


Signal Acquiredfrom ComplianceBoard

Embed the Add-In CardCompliance Channel

Closed Eye due tothe Channel

Apply the Base Specification CTLE + Dfe for Long Channel

Open Eye for Measurements

Signal is acquired directly off the PCI Express Compliance Base or Load Board

Compliance channel is “embedded” in the acquired signal

S-Parameters for the compliance channel are available from the PCI-SIG

Channel Embedding Verification


When post processing the acquired waveform it is desired in many cases to verify the results

The effects of embedding can be quickly verified using plots and waveforms

◦ The plot below shows that based on the PCIe 3.0 Add-In Card Compliance Channel, 10dB attenuation is expected on high frequency bits (4Ghz for PCIeGen 3)

Channel EmbeddingVerification


Based on the Insertion Loss Plot, we expect a 10dB loss at the fundamental frequency of 4Ghz. ◦ This equates to approx. 68% reduction in the high frequency content of the signal (lin = 10^(db/20), so 10^(-10/20) =

.316)

This can be easily verified on the scope waveform by doing a quick check using cursor measurements

Channel EmbeddingVerification


Next measure the vertical amplitude after the channel (approx. 140mV)

SDLA has automatically applied the channel filter to Math 4



Select Input Mode








Select Test Points


Select Input Mode








Select Test Points


Receiver Equalizer

Input Mode


Receiver Equalization

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Viewing at the Rx does show the closure, but doesn’t give a clear answer to the question what will the signal look like inside the Rx where the decision 0 or 1 is made by the comparator (aka the “slicer”).

SDLA tools allow the user to insert different Equalizers, then observe at the ‘virtual’ Rx.

Popular Equalizers: FFE, DFE, CTLE*

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Comp.

Combined result at end of channel

Transmitter performance

Channel Characteristics (S-parameters)

Emulated result at the comparator

Enable Rx Equalization … … observe opening of eye

*CTLE not currently supported in JNB

Configuring the Simulation CircuitConfigure Receiver Equalizer


IBIS-AMIEnables processing of vendor specific equalization models

Requires an IBIS-AMI file from the silicon vendorMost IBIS-AMI models are under IP control so we will not distribute the models with SDLA

Please be advised, there may be differences unknown to us in model to model that may require updating our software

CTLE and/or DFE/FFEGeneral Purpose equalization with PCIe 3.0 specific support for equalization optimizationClock recovery is required for FFE/DFE, new support is added to automatically configure the bit rate, but requires a starting point close to the actual data rate

Equalization: CTLE frequency response

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CTLE response example

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CTLE – Continuous Time Linear Equalization

Linear HF filter/boost

Advantages: Low power & Simple implementation

… but it amplifies noise

zero – pole - pole

Understanding Test PointsTp10 Equalizer Test Points


• SDLA Visualizer has a new test point Tp10, allows visibility between CTLE and DFE/FFE◦ Enables measurement/visual inspection of effect of DFE/FFE after

CTLE◦ Enables real-time update when using CTLE only

Source

Tp10 Tp4

Tp3

CTLE Example

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• Equalizer model

◦ Pole, Zero, and Frequencies entered into SDLA tool

Far End Eye After CTLE

Receiver EqualizationPCIe 3.0 Example

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All “closed” eye standards have reference equalizers to be used for compliance testingThese are defined in the specification, but do not put any requirement on silicon implementationSilicon is assumed to be as good or better than the reference equalizer

PCI Express 3.0 reference equalizer is CTLE and 1 Tap DFECTLE – one Zero and Two PolesDFE – 1 Tap (-30/30mV tap value)

CTLE + DFE values are optimized to produce the best eye area7dB Adc settings are shown in the example below

Verifying Effects of RX Equalizer

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Low frequency bits are attenuated based on the optimal CTLE setting

Example below shows plot of -8dB Adc◦ Low frequency bits should be attenuated by ~60%

DFE will result in an increase of eye opening based on the tap value setting

Validate EqualizerAnalyze Raw Waveform

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On the scope, use cursors to measure the low frequency content of the signal on the acquired waveform (Math 1)

In this example the low frequency content of the waveform is approx. 615mV

Validate EqualizerAnalyze Waveform After CTLE

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Based on the CTLE that was applied, we expect a 60% attenuation in the low frequency content after the CTLE

This can quickly be verified, note the low frequency amplitude is approx. 240mV

High Frequency Boost ImplementationFeed Forward Equalizer (FFE)

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D out

T is a UI; let K be 1 (UI-spaced).

Equalization: Decision Feedback Equalization (DFE)

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D out

T is a UI; let K be 1 (UI-spaced).Pic from Matlab signal processing lib. documentation

•Non-linear due to feedback after comparator (yd)•Comparator is the non-linear device•Advantage: FFE amplifies noise DFE does not add noise •Disadvantage: More complex, can potentially propogate errors

Decision Feedback EqualizationEffectively further open the eye

Correct baseline wander of received data stream by subtracting-off a portion of recent history

40” PCI Compliance ISI Board, 5Gbps PRBS-7 Data

4-bit Average Improved Margin

Decision Level

“Delay and Invert”

Received Data

Add Red + Blue

1.

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DFE Waveform View

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Boost logic ‘0’

Latch ‘0’

Boost logic ‘1’

(for the next bit!)

Latch ‘0’

Latch ‘1’

Boost logic ‘0’

Latch ‘0’

Boost logic ‘1’

Validate EqualizerAnalyze DFE

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PCIe uses a 1 tap DFE, meaning that the previous bit will determine if change of the current bit. The DFE will open the eye by twice the tap value

The table below outlines the change based on the 20mV Tap

Previous Bit Current Bit Change

0 1 20mV

1 0 -20mV

0 0 No Change

1 1 No Change

Validate Equalizer: Analyze DFE

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Both waveform and eye diagram views of the signal after DFE are available

The example shows validating the effects of DFE on a scope waveform

◦ DFE will open the eye by approx 2 times the tap value ◦ High frequency signal before DFE is 126mV and after 166mV,

which is 2 times the tap value of 20mV

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IBIS-AMI with Real-Time Oscilloscopes Introduction

Equalization in Real-Time Oscilloscopes

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• In the past, post processing software on oscilloscopes have implemented reference equalization models and clock recovery based on the requirements of serial standards including SAS and PCI Express 3.0

• These methods are required for compliance testing, but fall short for characterization and debug where it is desired to look at true circuit behavior

What is IBIS-AMI

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• Provides a standard modeling approach for digital models including RX/TX equalization and clock recovery◦ Allows for interoperability between different vendors◦ Provides faster simulations compared to SPICE◦ Encapsulates vendor specific IP

• IBIS-AMI models support two input parameters◦ Impulse Response

▪ Impulse response is fed into the IBIS-AMI model, equalization is applied and an impulse response is returned

◦ Time Domain Waveform▪ Waveform is fed into the IBIS-AMI model, equalization is applied and an

waveform is returned

IBIS-AMI in the Time Domain

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Why use IBIS-AMI models

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• Reference equalizers represent an ideal mathematical model that can implement DFE as defined in the specification

◦ Don’t take into account exact clock recovery function, automatic gain control

• IBIS-AMI models are designed using the architecture of the actual receiver

◦ Impairments to mimic jitter, voltage variation, temperature variation, and bandwidth limitations

Reference Equalizer10 Tap DFECR: Type II PLL JTF 7.2Mhz

IBIS-AMI Model

442mV68ps

311mV56ps


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Select Input Mode








Select Test Points


Select Input Mode








Select Test Points


Receiver Equalizer

Input Mode


Understanding Test PointsTest Point Configuration


• SDLA Test Points use the Scope Math System

• This methodology allows us to always have visibility of the raw waveform and allows simultaneous visibility of multiple test points

• Before Test Points are “Visible” and before the model can be applied Test Points must be enabled in the SDLA Test Point Manager

◦ Clicking on the radio button of any Test Point will open the Test Point Manager

Understanding Test PointsTest Point Manager Overview


Control to Turn on Test Point

Test Point to Turn On

Test Point Label (Shows up on Graticule and DPOJET)

Save Test Points for Later Use

Bandwidth Limit Control

Filter Delay Control, default is Remove Delay

NOTE: After making changes the SDLA Model must be applied by clicking the Apply Button on the Main SDLA Screen.

Test Point Visibility


• After Applying the SDLA Model, Magnitude, Phase, Impulse and Step Response Plots are visible for each test point.

Measuring Test Points


• DPOJET can be automatically configured from SDLA or SDLA can perform a recalculation after processing of previously configured setup

Agenda

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1. Market info


3. SDLA feature by feature


SDLA from TektronixDPO/DSA70000B and DSA8300

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Tektronix SDLA Solution:

Flexible: supports both RT and Sampling SDLA tools; Select the oscilloscope you need, Tekanalysis tools are there for you

Proven: Tek’s SDLA tools have been used by the industry since fall of 2007 (80SJNB Advanced introduction)

Gives clear insightSDLA provides multiple simultaneous eye diagrams for each steps of the path (Tx, channel emulation, Rx equalization)SDLA provides clarifying time and frequency domain plots allowing the user to verify the process if desired.*Equalization supports a very flexible software clock recovery* and can open almost any closed eyeEqualization has 3 modes of adaptation that can learn from a known pattern, an unknown pattern* or traffic* or can be pre-configured.

*Not available in Sampling.

SDLA for DPO/DSA70000B Features and Benefits

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Features BenefitsOpt. SLE: Serial Link Essentials* Channel Effects Emulation (add/remove)

* Transmitter Pre/De emphasis (add/remove)

* Test Fixture De-embed

* Time/frequency domain plots for debug

* Seamless waveform interface to DPOJET

* Multiple simultaneous eye diagrams for each step of the link

Complete, flexible, insightful, precise tool set to analyze the link

Insight into reasons for eye closure and transmission failure

Enables what if analysis on the real signal, and provides immediate results and measurements on the scope

Emulate what is happening on the link even if you don’t have the whole link available –debugging remote systems

Remove the impact of test fixture on the measurements for more precision.

Opt. SLA: Serial Link Advanced (Includes all SLE features and benefits)* DFE/FFE Equalization with 3 modes of adaptation: learn from a training sequence, or from unknown sequence, or from traffic

Emulation of the waveform at the receiver; Include the effects of a Rx equalization – using a flexible “golden” known model and correlated to other implementations of this “golden” model.

80SJNB Advanced* “Complete Link” – channel embedding, equalization (FFE/DFE)

Separation of Jitter & Noise into deterministic & random components at the comparator

Eye contour and BER eye calculations at the comparator

Same as Above Plus

Jitter, Noise and BER analysis of high-speed serial data rates from <1 Gb/s to 60 Gb/s provides insight into precise causes of eye closure

Separation of both Jitter and Noise provides highly accurate extrapolation of BER and eye contour

Unmatched measurement system fidelity with ultra-low Jitter floor for accurate and repeatable measurement results

Date post:	16-Jan-2023
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Embedded, De-embedded in High speed serial data system

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