QUALITY AND RELIABILITY ENGINEERING INTERNATIONAL. VOL. 8, 177-187 (1992)

FLOATING GATE MEMORIES RELIABILITY G. CRISENZA, C. CLEMENTI, G. GHIDINI AND M. TOSI

SGS-Thomson Microelectronics, Central R & D Technology. viu C. Olivetti 2, 20041 Agrate Briatrzct ( M I ) , Italy

SUMMARY Besides conventional IC failure mechanisms, the floating gate (FG) device reliability is affected by data retention, characteristic of non-volatile memories, and endurance, typical of electrically erasable arrays.

The subjects of this work are EPROM and flash EEPROM, the leading and most promising devices among the FG non-volatile memories.

The degradation mechanisms observed in programming and erasing steps are investigated. EPROM data retention is associated with intrinsic and defect related charge loss with both electronic and ionic processes involved. Experimental results are presented.

The reliability problems associated with repeated write/erase cycles are introduced, and their effects on EEPROM endurance discussed.

Finally, a fishbone diagram for data retention is proposed. The complexity of technology and the cell scaling down with increasing chip size impose lower failure rate goals and reliability becomes integrated within the manufacturing process.

KEY WORDS Reliability Non-volatile memories Data retention Endurance

INTRODUCTION

FG memories have shown better reliability than SRAM and DRAM, since they are less sensitive to low voltage oxide breakdown and soft errors. 1,2

FG memory arrays are designed and tested for high voltage operations. Few program cycles during production test guarantee good oxide integrity. Fur- thermore, many of the oxides are grown relatively thick to be compatible with high voltage operation. On the other hand, volatile memories and logical devices use thinner gate oxides, which cannot sustain high voltage screening.

From the intrinsic point of view, FG data reten- tion should be infinite, for the 3.2 eV oxide barrier height prevents electrons from escaping, even at high temperature^.^

In the case of volatile memories, the number of carriers generated by an a-particle loosing energy across the thin FG is very small in comparison with those produced in the substrate. Moreover, only few electrons will escape over the oxide barrier.2 Therefore, the charge stored in a floating gate is much safer than the one stored in a diffused circuit node.

Hence, the intrinsic charge loss does not strongly affect the failure rate and the data retention basically depends on defect density. The quality of dielectrics is the key issue in FG memory reliability: retention and endurance are characteristics of the same dielec- trics. Retention is affected by conduction at low electric fields, while endurance is related to high field conduction. A defective dielectric will cause both endurance and retention failure. High density

FG memory reliability is limited by the defect den- sity typical of a given technology.

Once the failure mechanism has been classified, the failure rate due to random defects can be pre- dicted by accelerated production screening.

As a drawback, non-volatile memories show higher cost and throughput time for the reliability tests.

EPROMs are at the moment the most diffused FG non-volatile memories, while flash EEPROMs are expected to have an important rise in the next five years.4

DEVICE STRUCTURE

The stacked gate cell (SGC), which is the most commonly used in EPROM and flash products, is presented in detail. EPROM and flash EEPROM SGC are n-channel MOS transistors with an additional FG. They are both programmed by chan- nel hot electron injection, but the erase mechanism is different: photoelectric effect for EPROMs and Fowler-Nordheim tunnelling through a thin gate oxide for flash.

The standard T-shaped layout (Figure l(a)) and the SGC architecture (Figures l(b) and l(c)) will be briefly described. Figure l (a) shows the smallest unit repeated in the array, defined in the x direction by the metal pitch (contact size and metal overlap on contact, metal to metal spacing) and in the y direction by the sum of source line width, source line to word line spacing, gate length, gate to contact distance and contact size. Figures l(b) and l(c)

074&8017/92/030177-11$10.50 0 1992 by John Wiley & Sons, Ltd.

Received February 1992

178 G . CRISENZA ET AL.

contact

I I

source I a)

interpoly dielectric

control gate I floating gate

C )

floating gate 1 gate oxide -1 I

source J ,.; - 7 p-substrate

drain L b)

control gate

source substrate drain

d) Figure 1. Layout of a T-shaped SGC (a); vertical cross section along (b) and perpendicular (c) to the channel; equivalent capacitive

circuit (d)

show the vertical cross-sections along and perpen- dicular to the channel. The FG and the surrounding dielectrics (thermal oxides and/or ONO) are clearly shown. The As source/drain junctions are self- aligned to the gate and symmetric in the EPROM cell, whereas a P diffusion is added to the source in the flash cell to allow high voltage while erasing. Usually a higher B dose than in transistors is implanted in the channel to prevent punch through and to increase programming efficiency by enhanc- ing carrier multiplication.

Both flash and EPROM cells are typically pro- grammed by applying positive voltage pulses to con- trol gate and drain. While the EPROM cell is erased by UV light irradiation, flash cell is erased by a high positive voltage applied to the source. For the high electric fields across the thin gate oxide, electrons can tunnel from the FG to the source. During the erase operation the drain is kept floating to prevent large channel currents.

An SGC can be simply described by an equivalent capacitive circuit (Figure l(d)) for which the FG potential V, can be easily calculated as a function of the bias conditions at the other nodes.

Defining the total FG capacitance CT as C, = Cpp + CD + Cs + CB, where Cj is the capacitance to FG to the j-electrode and Cpp is the interpoly capacitance, it can be shown by trivial considerations that

where cxj = Cj/CT is the coupling ratio, Q the charge stored in the FG, VT and VTo the programmed and virgin threshold voltages. Once the coupling ratios are known, the SGC electrical characteristics are those of a conventional MOS transistor, whose gate voltage is given by equation (1).

In addition, the electric field across the interpoly dielectrics EPP, can be easily calculated as

(3)

Xpp being the equivalent thickness of the interpoly dielectric.

EG, the electric field across the gate oxide, depending on the faced j-electrode, at first order becomes

where XG is the gate oxide thickness.

(4)

FLOATING GATE MEMORIES RELIABILITY 179

RETENTION

A memory cell is in the logic condition ‘1’ or ‘0’ depending on the quantity of charge stored in the FG. Retention measures the integrity of stored data as a function of time, evaluating the period elapsed between the data storage and the first repeatable fault in reading. The charge loss may result from intrinsic or defect related mechanism. Moreover stress during the programming of the array may influence data

Program disturbs

DC erase, programming disturbs and DC pro- gramming are here described. These are the three main stressing conditions that can occur while pro- gramming the array. Program disturbs affecting memory cells sharing a common gate (wordline) or a common drain (bitline) (see Figure 2) influence both yield, for failures in programming verification, and reliability for faults during prolonged reading cycles. An important consideration in the design is the accurate choice of reading and programming voltage to minimize these effects.

DC erase is a gate stress on programmed cells (see Cell A in Figure 2), causing charge loss. Once cell A is programmed, the programming of the remaining bits of the same wordline produces a high voltage on the A cell. From equations ( l ) , (2) and (3), the electric field across the interpoly oxide is

where VcG is equal to Vpp, the high voltage applied in programming.

Since this electric field may be large enough to cause tunnelling, the resulting charge loss produces a decrease of the (margin) threshold voltage of the cell with possible data loss. In Figure 3 the potential diagram of the cell is shown. In a similar way,

hND o v

12 v

b & b BL BL BL o v 7 v o v

Figure 2. Schematic of a memory array displaying stress con- ditions resulting in program disturb

Substrate -r Floating Gate

0

Control Gate

Figure 3. Potential diagram for gate stress on programmed cell

prolonged reading cycles can be very harmful and the quality of the interpoly dielectric can be tested with this kind of stress.

Program disturb (see cell D in Figure 2) is a drain stess on programmed cells. The programming of bits in the same bitline may cause charge loss. From equations (l), (2) and (4), the electric field across the gate oxide on the drain is

VD being the drain high voltage in programming. In a flash EPROM this electric field may allow

the electron tunnelling from the FG to the drain, while in the last EPROM generation holes generated in silicon may be collected in the FG. The related potential diagram is shown in Figure 4. This stress tests the quality of both gate oxide (tunnel oxide in flash EEPROMs) and FG edge sealing oxide.

DC programming is a gate stress on not pro- grammed or erased cells (see cell C in Figure 2), yielding a charge gain. The related potential diagram is shown in Figure 5 . High voltage on the word line produces high electric field on the gate oxide. The cell threshold voltage, especially for flash EEP- ROM, may increase for the electron tunnelling from

Floating Gate \ 00 0

0

Substrate I

I

Figure 4. Potential diagram for drain stress on programmed cell

180 G . CRlSENZA ET AL.

0.8

0 6 -

Figure 5 . Potential diagram for gate stress on erased cell

substrate to FG. A similar event may occur during prolonged reading cycles. Hot electrons injected from the substrate may be accidentally collected by the FG. A proper cell design can eliminate this last effect.

In conclusion, the major concerns related with these failures are the pattern sensitivity, imposing proper production screening, and the margin reduction of the stored logical levels, affecting the overall reliability.

Intrinsic charge loss As already discussed, charge transfer due to

intrinsic mechanism is negligible: retention time for a defect free cell is expected to be in excess of thousands of year^.^.^ The intrinsic leakage current has been modelled by Fowler-Nordheim tunnelling and thermionic emi~sion.~ The potential diagram of a programmed cell without external bias is shown in Figure 6.

The leakage current density due to electron tun- nelling through the oxide potential barrier is by Fowler-Nordheim emission: lo

J = AE2exp( -:) (7)

A and B depend on the barrier height and the electron effective mass. The effective electric field

Figure 6. Potential diagram for a programmed cell

through all the dielectrics in a programmed cell is so low that the resulting leakage current does not produce significant charge loss after tens of years.

At high temperatures the thermionic emission may cause additional charge loss. The electron num- ber n in the FG is a function of time t and tempera- ture T. According to the thermionic emission model, n(t) is given by

where n(0) is the number of electrons stored in the FG after programming, u the electron-phonon collision frequency, k the Boltzmann’s constant and aB the barrier height.3

In a typical 250°C bake, a value of QB larger than 1 eV yields months of data retention, corresponding to a huge number of years at operating conditions.

Anyway, as Figure 7 suggests, an intrinsic charge loss, typically corresponding to a fixed, small frac- tion of the stored charge, can be observed on almost all cells. Charge loss rate decreases with the baking time, independently on cell layout. Electrons pre- viously trapped in the interpoly and gate oxide dur- ing UV erasing9 may represent a component of the lost charge.

A different mechanism has been reported for the intrinsic charge loss of cells with ON0 (oxide- nitride-oxide) as interpoly dielectric. 11,13

The intrinsic retention characteristics can be mod- elled by three main mechanisms occurring in three different phases. The initial fast charge loss may be related to carrier movement in the nitride or to a nitride polarization effect, increasing with nitride

0.2

0 0 2 0 0 4 0 0 600 800 1000 1200

250 C BAKE TIME ( H O U R S )

Figure 7. EPROM cell (ONO) threshold shift vs. 250°C baking time

181 FLOATING GATE MEMORIES RELIABILITY

thickness. The second phase is associated with the electrons moving within the nitride from the bottom oxidelnitride interface to the nitride/top oxide interface, according to a trap to trap hopping trans- port law (linear dependence on electric field). These electrons may come from the programming or leak- ing through the bottom oxide. The third phase is a non-saturating long-term charge loss due to elec- trons leaking through the top oxide. The first step is strongly temperature related, while for the other two phases an activation energy of 0.35 eV has been found for temperatures below 300°C. At higher tem- peratures, the charge loss is limited only by the electron surmounting the nitridehop oxide barrier, through a Poole-Frenkel mechanism with a barrier height of 1.9 eV.42

On the other hand, the intrinsic charge loss may be related to a ionic process.14.16 A field assisted thermally activated release of mobile ions from the interlevel dielectric may be superimposed to the intrinsic charge loss. This problem can be faced in two different ways: the cell pas~ivation'~ or the contamination gettering. l4 With the cell scaling down, the charge stored in the FG is reduced (equation (2)), obtaining the same AVT. The cell is then more sensible to ion contamination. Charge loss as a function of the control gate/floating gate overlapping area is shown in Figure 8. Cells with the same interpoly and gate oxide thicknesses, but with different borophosphosilicate glasses (BPSG) as interlevel dielectric have been used to stress the role of P in improving data retention. Figure 8 shows only a qualitative trend, since the capacitance experimentally scales as the square of the scaling factor, while theoretically it decreases linearly.

Defect related charge loss

The retention time of the worst cell rules the retention time of a FG memory array. This basic consideration suggests that the number of the cells and the distribution of cell retention time statistically influence the FG memory retention. Moreover, the

larger the memory array, the higher the probability of finding a cell containing a defect. Defects can be classified as structural, affecting the infant mortality, or statistical, associated with the wearout. The first kind of defects may be disclosed by an effective bum-in screening, while the retention failure rate is essentially due to the second type of defects. The defect related charge loss is the result of latent failures, whose degradation is enhanced by the tem- perature treatments.

According to the nature of the charge carrier, we can distinguish between electronic and ionic pro- cesses. Electronic processes are related to the escape of electrons from the FG through oxide defects. This failure mechanism typically affects single bits randomly located in a memory array. Ionic pro- cesses, affecting the charge loss not of the whole array, but only of localized spots, are connected with contaminating species, which may be present in the process, or come from outside through a hole in the final passivation.

Electronic processes. From the life test results it turns out that the single bit charge loss is probably the most important failure mode in EPROM reliability. The reading current distribution of a 4Mb EPROM cell immediately after programming and after lo00 hours at 250°C is shown in Figures 9 and 10. The array has been programmed in such a way as to easily detect any increase in the cell current, to monitor the charge loss. While the whole histo- gram has a very small shift, a single bit moves away from the distribution and fails. The defect may be located in the gate oxide or in the interpoly dielec- tric: the distinction is possible by performing gate stress on a programmed or erased cell. According to the potential diagrams previously presented in Figures 3 and 5, charge gain of erased cell is connec- ted with a gate oxide failure, while charge loss of programmed cell is related with an interpoly dielec- tric failure.

The leakage current follows a linear dependence on the electric field for gate oxide failures in

T - 425 OC t' = 10 min

AVT(0) = 5 V

v- ~

0 1 2 3 4 5 control gate - floating gate overlap area ( pm 2,

Figure 8. Charge loss vs. floating gate area with intermediate dielectric phosphorus content as parameter

1000000

100000 t=O

.- 2 10000

"0 1000

.n

5 100

5 10 z

1

n .

10 20 30 40 so 00 70 no ~ o i o o i i o i ~ o i ~ o ~ ~ o i 6 o t e o ~ ~ o i e o i s o ~ a "_ I

Cell current (uA)

Figure 9. Cell reading current distribution after programming in a 4 Mbit EPROM

182 G . CRISENZA ET A L .

10000000 c 1000000

100000 t- 1000 hours

10000

a3 c 1000 n 0 100 .c

2 10

5 1 z 0.1

10 20 30 40 50 80 70 80 90100110120130140150180170180190200

Cell current (uA) Figure 10. Cell reading current distribution after lo00 hours

250°C bake in a 4 Mbit EPROM

EPROMs, while the dependence is exponential for both tunnel oxide18 and interpoly oxide9 failures. The charge loss for both interpoly and gate oxide (Figure 11) has an activation energy of 0.6 eV, while a 0.25 eV value or less has been found for tunnel oxide. On the other hand, the O N 0 interpoly dielec- tric has an activation energy of 0.8 eV (Figure 12).

Hopping conduction, with positive temperature coefficient and linear dependence on electric field, has been proposed as a transport mechanism through gate oxide defects.8 Tunnelling current dur- ing erasing shows the same linear dependence on electric field, suggesting the onset of tunnelling through a lower or thinner potential barrier in defec- tive tunnel oxides.18 On the contrary, considering both thermal acceleration and exponential I-V dependence, the conduction through defects in interpoly dielectrics, O N 0 included, is modelled by a Poole-Frenkel mechani~rn.~ The zero time testing

Ea.0.6 eV

O.O1 v 0.001 ' I

1.5 1.6 1.7 1.8 1.9 2 2.1 2.2

1000IT (VK) Figure 11. Temperature dependence of failure time for failed bits

with gate oxide defects

...- . 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2

1000/T (1/K) Figure 12. Temperature dependence of failure time for failed bits

with interpoly O.N.O. defects

is not suitable to detect a hole in O N 0 bottom oxide and only the temperature causes a charge motion from the FG to the nitride, whose conduction is known to be modelled by the Poole-Frenkel mech- a n i ~ m . ~ ~ , ~ ~ Charge loss related to ON0 defects is usually ascribed to the poor quality of the bottom

Because of this high defectivity, the sca- ling down of the O N 0 layer could be obtained by using the NO layer only." Furthermore, the thicker the nitride and the thinner the O N 0 top oxide, the larger the threshold ~ h i f t . ~ ~ , ~ ~ In conclusion, the defect related charge loss is not a fixed amount, but depends on the size, the nature and the position of the defect itself.

Ionic processes. A defect, i.e. a pinhole, in the final passivation or in the intermediate dielectric may allow mobile ions, namely alkali metals, to diffuse into the array and compensate the negative charge stored in the FG. Another possible source of contaminating species is the process itself; with the scaling down this contamination level will become more and more important for the reliability issues. A typical feature of ionic contamination can be observed by performing the following cycle: a high temperature bake on programmed cells, an U.V. erasing and a final bake. According to this model,9 it can be found a charge loss after the first bake, driven by the electric field associated with the stored negative charge, and a charge gain after the second bake, driven by the ion concentration gradi- ent. In a localized region around the pinhole the bits quickly fail. Fick's law, modelling the diffusion from a localized source, can be used to evaluate the time to failure.26 It was found that the radius of the circular zone grows with the square root of the time and the charge loss mechanism is thermally

183 FLOATING GATE MEMORIES RELIABILITY

Oerase

activated, with activation energies ranging between 1.2 eV8 and 1.8 eV.26

ENDURANCE

Endurance is a basic reliability issue for the electri- cally erasable FG memories. Successive program and erase (P/E) cycles progressively damage the thin oxide under the floating gate. Current flow causes both trapping and interface states: the amount of damage depends on the injected charge density. Because of this trapped charge, the thres- hold shift between erased and programmed cell decreases as shown in Figure 13. The maximum number of cycles the cell can withstand, before no longer succeeding in storing charge in the FG, has been defined as endurance. Endurance in FG EEP- ROM is strictly related with the tunnel oxide, obtainable via a thin gate or a thick oxide on a textured p~ly-Si.* '-~~ Negative charge trapping in the tunnel oxide causes the intrinsic wearout mechanism affecting endurance. Low field breakdown of both gate and tunnel oxide is the defect related mechanism affecting endurance. An additional wearout mechanism related to enhanced hole trapping in the thin o ~ i d e ~ , ~ ~ , ~ ~ is present in flash EEPROM because of flash erase operating condition.

Intrinsic endurance

During P/E cycles a relevant electronic charge flows through the tunnel oxide. Some charge may be trapped and shield tunnelling and thus program- ming. This trapping can be evaluated by measuring the increase in the programming voltage required to program the cell as a consequence of cycling. Trap- up is proportional to the square of the oxide thick- ness and therefore influences more the textured

polyoxide than the thin oxide. Endurance limited by trap-up exhibits a negative temperature acceleration with an activation energy of about -0.1 eV, prob- ably due to thermal detrapping during P/E cycles.

Defect related endurance

Tunnel oxide breakdown is a completely random process, more frequently observed on thin than on thick tunnel oxide. Oxide breakdown is gradual and irreversible as in a typical capacitor. The small amount of available electrostatic energy in the float- ing gate capacitance explains this behaviour. The conduction characteristics show an exponential dependence on electric field, as the Si-Si02 barrier becomes either lower or thinner. Endurance limited by tunnel oxide breakdown is only slightly acceler- ated by temperature with an activation energy of 0.15 eV. Gate oxide breakdown can also take place on the decoding circuit, because of the high voltage required for programming and erasing. Typical effect on the device is row or column failure.

Endurance in FG EEPROMs with textured poly is limited by trap-up, an intrinsic mechanism. In FG EEPROMs with thin oxide the endurance is defect limited, and thus strongly influenced by the increase of memory size. As a consequence, the SGC flash EEPROM cell architecture enhances the thin oxide EEPROM endurance, yielding both high memory density and a large number of P/E cycles. This improvement can be attributed mainly to two causes. First, the tunnelling area is smaller than on previous EEPROM mask-defined thin oxide, being flash erase confined in the FG-source overlap region. Therefore oxide defect density is less important. Secondly, the quality of tunnel oxides grown on lightly doped instead of heavy doped sili- con is intrinsically better. In addition, flash erase allows the use of longer, lower voltage erase pulses, with lower oxide stresses.

h

184 G . CRISENZA ET AL.

Figure 13 shows the endurance of a small array of flash EEPROM: more than one hundred thou- sand P/E cycles have been accomplished. The slope of the erase curve indicates a window widening after one hundred cycles, probably due to hole injection above the source, which enhances electron tunnel- ling. A further increase of the erase curve can be attributed to electron trap-up, as already observed in EEPROM wth thin gate oxide.

In flash EEPROM P/E cycles influence the DC program disturb and data retention (charge loss). This behaviour is associated with a lowering of the tunnelling barrier, because of hole injection and trapping in the tunnel oxide. This injection, during flash erase, is correlated with the gate aided junction breakdown at the source resulting in hot hole gener- ation in the source-substrate depletion region.

SCREENING AND LIFE TESTS

Accelerated life test on FG memories is widely used as a reliability characterization methodology. It is based on the fact that the data retention failure mechanisms are enhanced by temperature and elec- tric field. Failure mechanisms are analysed and the related acceleration factors determined. The failure rates are then estimated by the accelerated life tests and correlated with the nominal operating con- ditions. Failure analysis techniques are necessary to identify the specific failure mechanism. In Table I the activation energies for the typical data loss fail- ure mechanisms are reported.

The burn-in conditions can be set and the expected device operating life calculated via the acceleration factors. As reported in Reference 34 the acceleration factor ATEF for the combined tem- perature and electric field stresses is given by

Table I

Failure mode Activation Authors and energy References ( e v )

Oxide breakdown

Oxides defects

Intrinsic charge loss

Intrinsic charge loss (ONO)

Ionic Contamination

Cycling induced charge loss

0.3 0.36

0.6 0.6

1.4 1.24

0.35 0.37

1-2 1.8

1.1

Baglee28 D ~ m a n g u e ~ ~

ShinerX Mielke'

ShinerX Nozawa'

WU" PanJ2

ShineP HefleyZh

Verma'

where Ea is the activation energy, To and T1 the operating and the stressing temperatures, respect- ively, Vo and V1 the operating and the stressing voltages, EEF an acceleration rate ~ o n s t a n t ~ ~ , ~ ~ and X,, the oxide thickness in A.

This traditional approach needs testing and scre- ening at the end of the process. The product is eventually scrapped only at this point: this implies that this methodology is very expensive and time consuming.

BUILDING IN RELIABILITY

A new method, building in reliability, proposed by Crook,37 Baglee6 and Schaff ,38 will be implemented in order to reach the failure rate needed for future FG memories. This approach basically deals with the understanding 'why the failure' instead of pre- dicting the 'time to failure'. It means to ensure the reliability more by controlling the input variables to the process in the manufacturing environment than by measuring the failure rate on the final product. Effectiveness and cost considerations support this a priori approach. First, as technology complexity grows up and dimensions scale down, failure analysis becomes less and less practical. Secondly, a huge number of units has to be monitored to meet the reliability goals, forecasted around 10 F I T s . ~ ~ Because of the lengthening of testing time associated with the increasing density, the demonstration of adequate device reliability will become too expen- sive and even unfeasible. All the manufacturing aspects assume a relevant role and must be kept under control, such as the cleanlinesss of the quartz- ware,6 the analysis of the oxidation ambient39 or the control of the particles associated with the specific process and equipment .40 Appropriate in-line moni- tors have to be used to control the process vari- ations. Obviously many process variables may be correlated to each reliability failure mechanism, and each variable may be a function of other input vari- ables, resulting thus in a fishbone diagram for each failure mechanism. A tentative fishbone diagram for the data retention in EPROM is presented in Figure 14. As discussed above, intrinsic and defect related charge loss affects data retention. Likewise, the input variables of this diagram can be classified as intrinsic and extrinsic.38

Intrinsic input variables are those selected to influence intrinsic reliability. Any variation from the formerly characterized target values has to be reduced to zero. Improving reliability means the continuous tightening of the dispersion of the intrin- sic input variables. Oxide thicknesses, floating gate doping as well as the stacked gate profile are con- ceived to get intrinsic data retention.

FLOATING GATE MEMORIES RELIABILIn 185

Figure 14. Fishbone diagram showing input variables which affect FG memory data retention

Extrinsic input variables, are those which can have an extraneous, even random, detrimental effect on data retention. Identifying and eliminating these effects is the main issue to reduce defect related data retention. This can be obtained by modifying, updating and replacing defect generating process steps or equipments. In process charging41 or oxi- dation ambient39 can be examples of extrinsic input variables.

Actually because of the FG technology com- plexity, many other input variables could influence data retention. In other words, the proposed approach suggests to control and reduce the process dispersions: as well known, an improvement both in quality and yield often corresponds with a reduction of reliability failures.

CONCLUSIONS

F.G. memory failure mechanisms have been reviewed, focusing on EPROM data retention and flash EEPROM endurance. The intrinsic retention does not contribute to the failure rate both consider- ing electronic and ionic processes, which indeed could be more critical as dimensions scale down. FG memory data retention is definitively determined by defect density. The quality of dielectrics is the key

issue in FG memory reliability: retention and endur- ance are characteristic of the same dielectric.

Hole trap-up degradation as well as destructive oxide breakdown during prograderase cycling are reported as limiting the flash EEPROM SGC endur- ance. A new methodology, building-in reliability, will be implemented in order to meet the require- ments for future FG memories: the key point is to improve reliability by classifying and controlling the input parameters of the manufacturing process.

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Authors’ Biographies:

Giuseppe Crisenza was born in Italy in 1950. He received the Doctor degree in physics from the University of Milan, Milan, Italy in 1977. His doctoral work was a study of the optical and electronic characteristics of the avalanche photodiodes. In 1978 he joined the Central R&D Depart- ment of SGS-Thomson Microelectronics, Agrate Brianza, Italy. Since 1978 he was engaged in NMOS non-volatile memory process development, working on process archi- tecture, high voltage devices, memory cell character- ization and new cell concepts. From 1985 up to now he led the CMOS EPROM process development for 1 Mbit, 4 Mbit and 16 Mbit generations. He is interested in the device design and fabrication process in submicrometer VLSI and non-volatile memory devices. He is currently developing ultra high density EPROM and flash EEP- ROM such as 64 Mbit and beyond.

FLOATING GATE MEMORIES RELIABILITY 187

Cesare Clementi was born in 1962. He received the degree in solid state physics from the University of Milan, Milan, Italy in 1988. The subject of his work of thesis was the optical absorption of neutron irradiated quartz and silica. In 1990 he joined SGS-Thomson Microelectronics and since then he has been working in Central R&D Process Development group. He is currently involved in 16 Mbit EPROM process integration, with particular interest in interpoly dielectrics.

Gabriella Ghidini was born in Piacenza, Italy, in 1955. She received the degree in solid state physics in Parma, Italy in 1979. The subject of her thesis work was the characterization of the heterojunction Cd,-,Zn,S/GaAs. In 1983 she received the Ph.D. degree in Physics from the City University of New York for a study of the critical conditions for the growth of Si02 on Si. In the same year she joined SGS-Thomson Microelectronics and she was

working in the Central R&D Physics group. In 1987 she joined the Central R&D Process Development group and she is currently involved in 16 Mbit EPROM process development and she is responsible for thin dielectric processes.

Marina Tosi was born in Verona, Italy in 1955. She received the degree in Physics from the University of Padova, Padova, Italy in 1978. The subject of her thesis work was the material characterization by X-ray fluor- escence and Rutherford scattering for geological appli- cations. In 1979 she joined SGS-Thomson Microelectron- ics in Central R&D Process development group. Since 1979 she has been engaged in NMOS transistor with par- ticular interest in hot carriers aging. From 1985 she was involved in CMOS EPROM process development, (currently in 16 Mbit EPROM) and she is responsible for interpoly dielectrics and reliability.