Low-Transition Test Pattern Generation for BIST-Based Applications

Low-Transition Test Pattern Generation forBIST-Based Applications

Mehrdad Nourani, Senior Member, IEEE, Mohammad Tehranipoor, Member, IEEE, and

Nisar Ahmed, Student Member, IEEE

Abstract—A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to

reduce the average and peak power of a circuit during test by reducing the transitions among patterns. Transitions are reduced in two

dimensions: 1) between consecutive patterns (fed to a combinational only circuit) and 2) between consecutive bits (sent to a scan

chain in a sequential circuit). LT-LFSR is independent of circuit under test and flexible to be used in both BIST and scan-based BIST

architectures. The proposed architecture increases the correlation among the patterns generated by LT-LFSR with negligible impact

on test length. The experimental results for the ISCAS’85 and ’89 benchmarks confirm up to 77 percent and 49 percent reduction in

average and peak power, respectively.

Index Terms—Built-In Self-Test, LFSR technique, low-power pattern generation, switching activity, reliability.

Ç

1 INTRODUCTION

POWER dissipation is a challenging problem for today’ssystem-on-chips (SoCs) design and test. In general, the

power dissipation of a system in test mode is more than innormal mode [1]. Four reasons are blamed for powerincrease during test [26]:

1. high-switching activity due to nature of test patterns,2. parallel activation of internal cores during test,3. power consumed by extra design-for-test (DFT)

circuitry, and4. low correlation among test vectors.

This extra power consumption (average or peak) cancreate problems such as instantaneous power surge thatcause circuit damage, formation of hot spots, difficulty inperformance verification, and reduction of the productyield and lifetime. Solutions that are commonly applied toalleviate the excessive power problem during test includereducing frequency and test partitioning/scheduling toavoid hot spots. The former disrupts at-speed test philoso-phy and the latter may significantly increase the time.

Built-In Self-Test (BIST) is a DFT methodology that aimsat detecting faulty components in a system by incorporatingthe test logic on chip. BIST is well known for its numerousadvantages such as at-speed testing and reduced need forexpensive external automatic test equipment (ATE). InBIST, a linear feedback shift register (LFSR) generates

pseudorandom test patterns for primary inputs (for a

combinational circuit) or scan chain inputs (for a sequential

circuit). On the observation side, a multiple input signature

register (MISR) compacts test responses received from

primary outputs or scan chain outputs. Unfortunately,

BIST-based structures are very vulnerable to high-power

consumption during test. Test vectors, applied to a circuit

under test at nominal operating frequency, often cause

more average and/or peak power dissipation than in

normal mode. The main reason is that the random nature

of patterns generated by an LFSR significantly reduces the

correlation not only among the patterns but also among

adjacent bits within each pattern.

1.1 Prior Work

Several techniques have been reported to cope with high-

power consumption in BIST-based architectures. These

techniques can be classified into three broad categories as

follows:

. System-Level Partitioning and/or Scheduling. Thetechnique proposed in [1] consists of a distributedBIST control scheme that simplifies BIST architecturefor complex ICs, especially during higher levels oftest activity. This approach can schedule the execu-tion of every BIST element to keep the powerdissipation under a specified limit. A partitioningmethod using hypergraph is employed in [10] tolower power in BIST designs. References [11] and[12] are two optimization techniques (using mixed-ILP and ILP, respectively) that insert idle timewindows in the test schedule to make sure thatpower and other thermal constraints are satisfied.

. Correlation-Driven Enhancement of LFSR. A BISTstrategy called dual-speed LFSR is proposed in [2] toreduce the circuit’s overall switching activities. Thistechnique uses two different-speed LFSRs to controlthose inputs that have elevated transition densities.

IEEE TRANSACTIONS ON COMPUTERS, VOL. 57, NO. 3, MARCH 2008 303

. M. Nourani is with the Department of Electrical Engineering, Universityof Texas at Dallas, 2601 North Floyd Road, PO Box 830688, EC 33,Richardson, TX 75083-0688. E-mail: [email protected].

. M. Tehranipoor and N. Ahmed are with the Department of Electrical andComputer Engineering, University of Connecticut, 371 Fairfield Way,U-2157, Storrs, CT 06269-2157.E-mail: {tehrani, nisar}@engr.uconn.edu.

Manuscript received 26 Oct. 2005; revised 5 June 2006; accepted 7 July 2006;published online 9 Aug. 2007.Recommended for acceptance by D. Pradhan.For information on obtaining reprints of this article, please send e-mail to:[email protected], and reference IEEECS Log Number TC-0375-1005.Digital Object Identifier no. 10.1109/TC.2007.70794.

0018-9340/08/$25.00 � 2008 IEEE Published by the IEEE Computer Society

Authorized licensed use limited to: IEEE Xplore. Downloaded on October 26, 2008 at 12:19 from IEEE Xplore. Restrictions apply.

The low-power test pattern generator presented in[3] is based on cellular automata and reduces the testpower in combinational circuits. Another low-powertest pattern generator based on a modified LFSR isproposed in [4]. This scheme reduces the power inCUT in general and clock tree in particular. A low-power BIST for data path architecture, built aroundmultiplier-accumulator pairs, proposed in [5], iscircuit dependent. This dependency implies thatnondetecting subsequences must be determined foreach circuit test sequence. A low-power BIST basedon state correlation analysis is proposed in [6].

Modifying the LFSR by adding weights to tunethe pseudorandom vectors for various probabilitiesdecreases energy consumption and increases faultcoverage [7], [8]. A low-power random patterngeneration technique to reduce signal activities inthe scan chain is proposed in [9]. In this technique,an LFSR generates equally probable random pat-terns. The technique generates random but highlycorrelated neighboring bits in the scan chain,reducing the number of transitions and, thus, theaverage power.

. Power-Driven Control of LFSR. The authors of [13]proposed a method to select an LFSR’s seed toreduce the lowest energy consumption using asimulated-annealing algorithm. Test vector inhibit-ing techniques [14], [15], [16] filter out somenondetecting subsequences of a pseudorandom testset generated by an LFSR. These architectures applythe minimum number of test vectors required toattain the desired fault coverage and thereforereduce power.

Many low-power strategies have been proposedfor full-scan [21], [22] and BIST/scan-based BISTarchitectures [17], [18], [19], [20]. The architectureproposed in [17] modifies the scan-path structuresuch that the CUT’s inputs remain unchangedduring a shift operation. A test pattern generatorfor scan-based BIST was proposed in [18] whichreduces the number of transitions that occur at scaninputs during scan-shift operation. The authors of[19] proposed a pseudorandom BIST scheme toreduce the switching activity in the scan chains. Theactivity and correlation in CUT are controlled bylimiting the scan shifts to a portion of the scan chainstructure using scan chain disable control.

1.2 Contribution and Paper Organization

This paper presents a new test pattern generator for low-power BIST (LT-LFSR), which can be employed by bothcombinational and sequential (scan-based) architectures.The proposed technique increases the correlation in twodimensions: 1) the vertical dimension between consecu-tive test patterns (Hamming Distance) and 2) thehorizontal dimension between adjacent bits of a patternsent to a scan chain. Reducing the switching activity inturn results in reducing the power consumption, bothpeak and average. The conventional LFSR structure willbe modified such that it automatically inserts intermedi-ate patterns between its original pairs. The intermediate

patterns are carefully chosen using two techniques (thatis, bipartite and random injection) and impose minimaltime increase to achieve a desired fault coverage. Thefavorable features of LT-LFSR in terms of performance,coverage, and average/peak power consumption areverified using the ISCAS’85 and ISCAS’89 benchmarks.

The rest of this paper is organized as follows: Section 2describes our motivation of designing a new randompattern generator. Section 3 describes the randomness oftest patterns generated by our proposed techniques.Section 4 describes implementation of the two proposedtechniques (RI and Bipartite) for low-power test patterngeneration and combines them to design our LT-LFSR.Section 5 discusses some practical aspects of LT-LFSR. Theexperimental results are discussed in Section 6. Finally, theconcluding remarks are in Section 7.

2 BACKGROUND AND MOTIVATION

2.1 Behavior and Applications of LFSR

Random pattern generators such as LFSR usuallygenerate very low correlated patterns. Assume that T i ¼fti1; ti2; . . . ; ting and T iþ1 ¼ ftiþ1

1 ; tiþ12 ; . . . ; tiþ1

n g are two con-secutive patterns. The number of bits in the test patterns ðnÞis equal to either the number of PIs or the length of the scanchain in the CUT. If T i is used for combinational circuits,then it is applied to PIs. If T i is a pattern generated to beused in sequential circuits, it is applied to the scan-in pin(SI) of a scan chain in the circuit.

2.2 Test per Clock versus Test per Scan

. Test per Clock. Assume that T i and T iþ1 are twoconsecutive patterns, and the number of bit changes(transitions) between two consecutive patternsðPn

j¼1 jtij � tiþ1j jÞ is high. If low-correlated patterns

are applied to PIs of combinational circuits (seeFig. 1a), they generate a high number of transitionsat the PIs, which in turn results in huge number ofswitching activities in CUT. The transitions betweentwo consecutive test patterns are shown in Fig. 1c.

. Test per Scan. Assume that bit j of patterns isshifted into the scan chain and the number oftransitions among the adjacent bits going into thescan chain SCjð

Pm�1i¼1 jtij � tiþ1

j jÞ is high. Fig. 1bshows a test-per-scan architecture that uses arandom pattern generator, that is, LFSR. It also usesMISR as the signature analyzer at the output of thescan chains to receive the responses. If low-corre-lated patterns are used for testing sequential circuits,they will result in a large number of transitions inscan chains and combinational block during shiftingthe patterns into the scan chains. The transitionsbetween two adjacent bits when shifted into a scan-in chain are shown using arrows in Fig. 1c.

2.3 Motivation and Focus

Almost all of the proposed techniques of random patterngenerators reduce the transitions either within the patternsor between the patterns [4], [23], [9]. In this paper, our goalis to design a new random pattern generator that reduces

304 IEEE TRANSACTIONS ON COMPUTERS, VOL. 57, NO. 3, MARCH 2008


the total number of transitions among the adjacent bits ineach random pattern (horizontal dimension) and transitionsbetween two consecutive random patterns (vertical dimen-sion) as well (see Fig. 1c). In other words, the new low-transition random pattern generator increases the correla-tion between and within patterns and can therefore be usedfor any combinational or sequential circuits.

We propose a random pattern generator that combinestwo methods of test pattern generation called RandomInjection (RI) and Bipartite LFSR. Briefly, the RI methodinserts a new intermediate pattern between two consecutivetest patterns by positioning a random-bit ðRÞ in thecorresponding bit of the intermediate pattern when thereis a transition between corresponding bits of pattern pairs.The Bipartite LFSR generates an intermediate pattern usingone half of each of the two consecutive random patterns.The main advantage of our proposed technique is that it canbe used for both combinational and sequential circuits andthe randomness quality of patterns does not deteriorate.

There are two additional favorable features in our low-power LFSR.

1. Both the peak and average power consumptions arereduced. The peak power reduction to alleviate thethermal and signal integrity problems during test isoften the main goal. However, reducing the averagepower will improve reliability. Moreover, in somecases, reducing the average test power is quitebeneficial. For example, some portable devices needto be self-tested periodically during their lifetimecycle [26].

2. The second feature of our LT-LFSR is its negligibleeffect on the fault coverage convergence. By injectingintermediate patterns into our technique, the correla-tion among patterns will change. However, inSection 5, we will show that the effect on performancefor achieving a target fault coverage is negligible. Notethat, even though intermediate patterns are generatedbetween consecutive patterns, the test length (numberof patterns required to achieve a target fault coverage)compared to a conventional random pattern genera-tor is quite close. This is achieved by preserving the

randomness of the inserted patterns. We will showour evidence using both the ISCAS’85 (combinational)and ISCAS’89 (sequential) benchmarks in Section 6.

3 RANDOM-BIT INJECTION METHODOLOGIES

3.1 Definition of Randomness Metric

Many researchers used entropy as a measure of randomnessmetric [32], [33]:

H ¼ �Xri¼1

pi � log2pi; ð1Þ

where pi is the probability that the signal is in state i and rdenotes total number of states. This metric can quantify howthe quality of pseudorandom values deteriorates if there is abiased change in bit selection or sequencing. More specifi-cally, for an n-bit perfect random generator, we have r ¼ 2n

and pi ¼ 1=2n and, thus, the entropy will be Hmax ¼ n,reflecting the maximum randomness. For a nonidealrandom generator, we get 0 � H � n. To make it easierfor computation in an n-bit LFSR, if p0j ðp1jÞ denotes theprobability of having 0 (1) in bit bj, then we approximate itsentropy by adding the entropy of individual bits:

H � �Xnj¼1

ðp0j � log2p0j þ p1j � log2p1jÞ: ð2Þ

3.2 Randomness in Conventional LFSR

LFSR units are expected to generate pseudorandompatterns that behave quite close to ideal random numbersðH � nÞ. To show this better, we analyzed the first 10,000patterns generated by a 20-bit LFSR with polynomialfðxÞ ¼ x20 þ xþ 1. The results are shown in Figs. 2, 3, and4 for conventional LFSR.

Fig. 2 shows that, if the number of patterns chosen(N ¼ 10; 000 here) is large, each bit bj ð1 � j � 20Þ wouldalmost equally get 0s and 1s. In practice, depending on thepolynomial used in the LFSR, the randomness is not perfect.That is why, in Fig. 2, for example, for LFSR, we get around4,930 zeros (that is, p0j � 0:493 and H � 19:72) instead ofexactly 5,000 ðHmax ¼ 20Þ. Figs. 3 and 4 picture distribution

NOURANI ET AL.: LOW-TRANSITION TEST PATTERN GENERATION FOR BIST-BASED APPLICATIONS 305

Fig. 1. Using LFSR in BIST architectures: (a) test per clock (for combinational circuits), (b) test per scan (for sequential circuits), and (c) bit transitions

in two dimensions.


of bit transitions vertically (between two consecutive

patterns fed to a combinational circuit) and horizontally

(among adjacent bits chosen from one bit position and fed

to a sequential circuit), respectively. The normal curvebehavior in Fig. 3 is expected due to close-to-perfectrandomness of bits generated in an LFSR. Note carefullythat, in Fig. 4, it is expected that the curves for bipartite andRI-LFSR will be identical as the total number of transitionsamong adjacent bits chosen from one bit position and sentinto a scan chain serially remains the same due to

Pnj¼1 jtij �

ti1j j þPn

j¼1 jti1j � tiþ1j j ¼

Pnj¼1 jtij � tiþ1

j j relation (see Fig. 1).It is also expected that the number of transitions for LFSRbecome almost twice that of the other two methods. This isbecause, for the case of LFSR, it generates 10,000 patterns.However, for bipartite-LFSR and RI-LFSR, only 5,000 ofthose patterns are used, in which another 5,000 patterns areadded to lower the transitions. This way we will be able tocompare three methods for the same number of totalpatterns (that is, 10,000).

3.3 Randomness in Bipartite LFSR

The implementation of an LFSR can be changed to improvesome design features, such as power, during test. However,such a modification may change the order of patterns orinsert new patterns that affect the overall randomness. Forexample, suppose that T i and T iþ1 are two consecutive


Fig. 2. Distribution of 0s for three random pattern generation strategies.

Fig. 3. Distribution of number of transitions between consecutive patterns for three random pattern generation strategies.

Fig. 4. Distribution of number of transitions for three random pattern

generation strategies.


patterns generated by an n-bit LFSR. The maximum

number of transitions will be n when T i and T iþ1 are

complements of each other. One strategy, used in [23] to

reduce number of transitions to maximum of n=2, is to

insert a pattern T i1, half of which is identical to T i and T iþ1.

This Bipartite (half-fixed) strategy is shown symbolically in

Fig. 5.The Bipartite strategy guarantees the transition change to

be limited to n=2 between two consecutive patterns.

However, it deteriorates the randomness to H ¼ n=2.

Intuitively, the worst-case scenario ðH ¼ 0Þ belongs to a

case in which all transitions happen in the same half that we

fix. In this case, Ti1 and T i will be identical and adding T i1

has no significance for fault detection. It only prolongs the

test. To see the randomness drop more clearly, we repeated

the same experiment for a modified 20-bit LFSR and the

results are shown in Figs. 2, 3, and 4.

3.4 Randomness in RI-LFSR

To preserve the randomness of patterns, instead of Bipartite

strategy, we randomly inject a value in bit positions, where

tij 6¼ tiþ1j . Briefly,

ti1j ¼tij if tij ¼ tiþ1

j

R if tij 6¼ tiþ1j :

(ð3Þ

Fig. 6 shows this symbolically. The shaded cells show

those bit positions where tij 6¼ tiþ1j . We insert a random bit

(shown asR inT i1) if the corresponding bits inT i andT iþ1 are

different. Note that, since such bits are uniformly distributed

and we also replace them with another random value, the

overall randomness remains unchanged, that is, Hmax ¼ n.

Unfortunately, the maximum bit transition can no longer be

guaranteed, although the expected number of transitions

(mean value in the normal distribution) will be n=2.To verify the high randomness of this strategy, we

repeated the same experiment for a modified 20-bit LFSR

and the results are shown in Figs. 2, 3, and 4.In Section 4, we will show how to design and mix these

two strategies (Bipartite and RI) to have an LFSR in which

the maximum number of transitions is guaranteed to be

n=4, while the randomness of patterns is largely preserved.

4 LOW-TRANSITION LINEAR FEEDBACK SHIFT

REGISTER ARCHITECTURE

4.1 Implementing the RI Technique

The RI technique (Section 3.4) inserts a new test pattern T i1

between these two test patterns such that the sum of the PI’s

activities between T i and T it ðNi;i1transÞ and T i1 and

T iþ1 ðNi1;iþ1trans Þ is equal to the activities between T i and

T iþ1 ðNi;iþ1transÞ or, briefly,

Ni;i1trans þN

i1;iþ1trans ¼ N

i;iþ1trans; ð4Þ

Xnj¼1

jtij � ti1j j þXnj¼1

jti1j � tiþ1j j ¼

Xnj¼1

jtij � tiþ1j j: ð5Þ

Therefore, by inserting T i1, Ni;iþ1trans is partitioned into two

parts, Ni;i1trans and Ni1;iþ1

trans , which reduce the patterns’ switch-

ing activity. When two same-position bits in T i and T iþ1 are

equal, the same bit is placed in the same position in T i1.

When there is a transition between two corresponding bits

in T i and T iþ1, the RI method injects random-bit ðRÞ.Fig. 7 shows a small example of generating an

intermediate pattern using the RI technique. The shaded

bits in T i and T iþ1 show that the number of transitions

between T i and T iþ1 is Ni;iþ1trans ¼ 10 before inserting T i1.

For example, after generating T i1 using the RI method, as

shown in Figs. 6 and 4 or 4 and 6 (depending on R ¼ 0

or 1), transitions exist between T i and T i1 and Ti1 and

T iþ1, respectively. There are a maximum of six transitions

for the RI technique regardless of R ¼ 0 or R ¼ 1. In

general, for n-bit vectors if m ðm � nÞ transitions exist

between T i and T iþ1:

Worst Case : Ni;i1trans ¼ 0; Ni1;iþ1

trans ¼ m ðor vice versaÞ;Best Case : Ni;i1

trans ¼ Ni1;iþ1trans ¼ m=2:

�ð6Þ


Fig. 5. Pattern insertion based on Bipartite strategy.

Fig. 6. Pattern insertion based on RI strategy.


Fig. 8 shows the RI unit that generates intermediatepatterns. R is a random bit which can come from one of theoutputs of a random pattern generator (for example, LFSR)itself.

4.2 Implementing Bipartite LFSR Technique

This technique inserts an intermediate test pattern ðT i1Þbetween two consecutive random patterns (T i and T iþ1)such that the transitions between T i and T i1 and T i1 andT iþ1 are reduced. In this technique, each half of T i1 is filledwith half of T i and T iþ1:

T i1 ¼ ti1; � � � ; tin2; tiþ1n

2þ1; � � � ; tiþ1

n

n o: ð7Þ

In this method, an LFSR is divided into two halves byapplying two complementary (nonoverlapping) enablesignals. In other words, when one half is working, theother half is in idle mode. An LFSR including flip-flops withenable is shown in Fig. 9a. Fig. 9b shows the architecture ofthe Bipartite LFSR to generate intermediate pattern T i1. en1

and en2 are two nonoverlapping enable signals. Whenen1en2 ¼ 10, the first half of LFSR is working, whereas, withen1en2 ¼ 01, the second half works. The shaded flip-flop isadded to the Bipartite LFSR architecture to store then=2th bit of LFSR when en1en2 ¼ 10 and send its valueinto the ðn=2þ 1Þth flip-flop when the second half becomesactive ðen1en2 ¼ 01Þ. Note carefully that the new (shaded)flip-flop does not change the characteristic function ofLFSR. The LFSR’s operation is effectively split into twohalves, and the shaded flip-flop is an interface betweenthese two.

This method is similar to the proposed LPATPG in [23]and Modified Clock Scheme LFSR [4]. Although the basicidea of Bipartite LFSR is not new, the LT-LFSR architectureis much more efficient in terms of randomness of patternsand power. In [23], the authors used two n-bit randompattern generators and n ð2� 1Þ multiplexers, but we onlyadd one flip-flop to an n-bit LFSR. Therefore, the area

overhead of Bipartite LFSR is much lower than LPATPG. In[4], an n-bit LFSR is divided into two n=2-bit LFSRs, whichtogether reduce the CUT and clock tree power consump-tion. The drawback of this technique is that it reduces therandomness property of the LFSR due to dividing it intotwo smaller LFSR and it also requires generating anddistributing two nonoverlapping clocks (with half fre-quency), which in turn increases the area overhead.

Our Bipartite LFSR keeps the randomness property ofthe n-bit LFSR intact and it also reduces the overall powerconsumption of Bipartite LFSR compared to LFSR because,in each period of the clock, half of the LFSR is in idle mode.Fig. 9c shows a small example of inserting an intermediatepattern T i1 between two consecutive patterns T i and T iþ1

using a 16-bit Bipartite LFSR. This reduces the bit transi-tions among patterns from Ni;iþ1

trans ¼ 10 to Ni;i1trans ¼ 7 and

Ni1;iþ1trans ¼ 3.

4.3 Implementing Low-Transition Linear FeedbackShift Register Architecture

We combine our two proposed techniques of patterngeneration (RI and Bipartite LFSR) for low-power BIST.The new LT-LFSR generates three intermediate patterns(T i1, T i2, and T i3) between T i and T iþ1. We embed these twotechniques into a bit-sliced LFSR architecture to create LT-LFSR, which provides more power reduction compared tohaving only one of the R-Injection and Bipartite LFSRtechniques in an LFSR. This may seem to prolong testsession by a factor of 4. However, due to the high


Fig. 7. An example for RI.

Fig. 8. An RI circuit. Fig. 9. The Bipartite LFSR technique.


randomness of the inserted patterns, many of the inter-

mediate patterns can do as well as patterns generated by an

LFSR in terms of fault detection. In fact, in Section 6, we

show that the overall number of LT-LFSR patterns to hit a

fault coverage target is quite close to the number of

conventional LFSR patterns.Fig. 10 shows LT-LFSR with RI and Bipartite LFSR

included. The LFSR used in LT-LFSR is an external-XOR

LFSR. As shown, an injector circuit taps the present state (T i

pattern) and the next state (T iþ1 pattern) of LFSR. Signals

en1 and en2 select half of the LFSR to generate random

patterns, as shown in Fig. 9. MUXs select either the injection

bit or the exact bit in LFSR. One very small (46 gates, see

Section 6) finite-state machine (FSM) controls the pattern

generation process as follows:

1. Step 1. en1en2 ¼ 10, sel1sel2 ¼ 11. The first half ofLFSR is active and the second half is in idle mode.Selecting sel1sel2 ¼ 11, both halves of LFSR are sentto the outputs (O1 to On). In this case, T i isgenerated.

2. Step 2. en1en2 ¼ 00, sel1sel2 ¼ 10. Both halves ofLFSR are in idle mode. The first half of LFSR is sentto the outputs (O1 to On=2), but the RI injector circuitoutputs are sent to the outputs (On

2þ1 to On). T i1 isgenerated.

3. Step 3. en1en2 ¼ 01, sel1sel2 ¼ 11. The second half ofLFSR works and the first half of LFSR is in idlemode. Both halves are transferred to the outputs (O1

to On) and T i2 is generated.4. Step 4. en1en2 ¼ 00, sel1sel2 ¼ 01. Both halves of

LFSR are in idle mode. From the first half, theinjector outputs are sent to the outputs of LT-LFSR(O1 to On=2) and the second half sends the exact bitsin LFSR to the outputs (On

2þ1 to On) to generate T i3.5. Step 5. The process continues by going through Step 1

to generate T iþ1.

Fig. 11 shows patterns generated using an 8-bit LP-LFSR

with polynomial x8 þ xþ 1 and seed ¼ 01001011. As shown,

between two consecutive patterns T i and T iþ1, three

intermediate patterns are generated as Ni;iþ1trans ¼ 7, but

Ni;i1trans, Ni1;i2

trans, Ni2;i3trans, and Ni3;iþ1

trans are 1, 2, 2, and 2,

respectively. This reduction of transitions eventually re-

duces the average and peak power during test.

LT-LFSR reduces the transitions between consecutivepatterns that can be used for test-per-clock architecture. Thegenerated patterns can also be used for test-per-scanarchitecture to feed scan chains with a lower number oftransitions. We will discuss this more in Section 5.

5 PRACTICAL ASPECTS

5.1 Time-Fault Coverage Relationship in LT-LFSR

Suppose a conventional LFSR generates N patterns for amaximum fault coverage ðFC�Þ for a CUT. Since LT-LFSRadds three intermediate patterns between LFSR patterns, itgenerates a total of 4N � 3 patterns. Although the worst-case scenario seems to quadruple the overall test time, thisnever happens in practical cases when the goal is to hit atarget fault coverage. Fig. 12 is an intuitive illustration ofthis fact. The FC curve for the majority of circuits risesexponentially (for example, point FC1 after N/10 patternsin LFSR) and then continues toward FC� logarithmically. InLT-LFSR, after 4N/10 patterns, we will be at FC1 (worstcase) or higher since all of those N/10 LFSR patterns areincluded. After that, an absolute worst-case (pessimistic)scenario is a case to hit FC� at 4N. In all of the examples wetried so far, this never happened because the random natureof patterns is preserved in LT-LFSR and almost all of theoriginal LFSR patterns are generated much earlier than the4N point. For example, for the s13207 ISCAS’85 benchmark,the required number of patterns to hitFC� ¼ 97:7% are 77,696and 78,832 for LFSR and LT-LFSR, respectively. This is only a1.5 percent increase for a large (about 8,500 gates) circuit.Empirically, FC� (or a higher point) is often hit in 0.9 N to 1.3N range using LT-LFSR patterns, as shown in Fig. 12. Ourexperimental results shown in Section 6 also confirm this


Fig. 10. LT-LFSR structure.

Fig. 11. An example of LT-LFSR using an 8-bit LFSR.


statistical analysis. Using a lesser number of patterns (forexample, 0.9 N to hitFC�) for some examples is not a surpriseas the intermediate patterns inserted by LT-LFSR were goodenough to catch some of the hard-to-detect faults. The rate ofgrowth of fault coverage for LFSR and LT-LFSR patterns wereperformed for one of the ISCAS’89 benchmarks in Section 6.

5.2 Performance Drawback

The additional components in LT-LFSR impose extra delay,which in turn causes slight performance degradationcompared to its LFSR counterpart. Our implementationusing Synopsys Design Compiler and 0.18 �m libraryindicates that, in the worst-case scenario, using an LT-LFSRcircuit, a maximum of 0.1 ns is added to the critical pathdelay of the unit. For example, for a circuit originallyrunning at 100 MHz, the delay added by LT-LFSR makesthe circuit run at 99.1 MHz, which is a negligible reduction.

5.3 BIST Applications

Figs. 13a and 13b show the application of LT-LFSR in test-per-clock (BIST) and test-per-scan (Scan-BIST) architectures,respectively. LT-LFSR can replace LFSR in all applicationsto generate and feed pseudorandom test patterns into thecircuit or scan chains. Specifically, the patterns appliedthrough a scan chain reduce the scan-in power because of alesser number of transitions generated inside the patterns.Note that we have not used phase shifter in this techniqueand that is mainly because the phase shifter may change thepatterns at its output and that may not result in high testpower reduction.

Fig. 14 shows the LT-LFSR patterns generated using an8-bit LT-LFSR, as discussed earlier in Fig. 11. Here, there arem ¼ 8 scan chains with a length of l ¼ 5. A maximum of one

transition exists in each scan chain (SC1 through SC8). Thisshows that LT-LFSR is quite capable of reducing transitionsin each test pattern applying to scan chain.

5.4 Power Consumption of Low-Transition LinearFeedback Shift Register

The power consumption of LT-LFSR itself is also reduceddue to using the Bipartite LFSR technique. Only half of theLT-LFSR components are clocked in each cycle. Fig. 15indicates this behavior. At each of the four steps of patterngeneration process, either half of the flip-flops or half of theRI units becomes active by en1en2 and sel1sel2, respectively.In an LFSR, all flip-flops are clocked at the same time ineach clock cycle and, thus, its power consumption is muchhigher than LT-LFSR. See Section 6 for more statistics.

5.5 Circuit-Independent Structure

Several methods were proposed for low-power BIST usingtest vector inhibiting [14], [15], [16] to filter out somenondetecting subsequences of a pseudorandom test setgenerated by an LFSR. These methods result in more powerreduction, but have high area overhead. More importantly,they are customized for the CUT (test pattern-dependent) andneed to start with a specific seed. Therefore, a preprocessingstep is required to obtain the nondetecting subsequencesand seed. Although LT-LFSR is totally independent of CUTand no preprocessing is needed to obtain a seed. LT-LFSRhas a flexible structure that can replace a conventional LFSRin any circuit.

5.6 Randomness in LT-LFSR

Figs. 16, 17, and 18 show the high randomness of 10,000 LT-LFSR patterns generated under polynomial x20 þ xþ 1. Asseen in Fig. 16, the number of 0s and 1s is almost equal,which indicates very good randomness for each bit. Fig. 17shows that a curve has been shifted to the left compared toLFSR’s curve in Fig. 3. This is expected as, by inserting three


Fig. 12. Time-coverage relationship in LT-LFSR.

Fig. 13. Using LT-LFSR in BIST architectures: (a) test-per-clock and

(b) test-per-scan.

Fig. 14. Test patterns generated using an 8-bit LT-LFSR used for test-

per-scan architecture.


patterns (see Fig. 11), the maximum number of transitionswill drop to n=4 (five in our case). Finally, Fig. 18 shows thatnumber of transitions in each bit position if that positionfeeds a scan chain. Again, this is almost four times betterthan conventional LFSR (Fig. 4).

6 EXPERIMENTAL RESULTS

6.1 Simulations Setup and Implementation

In our experimentation, we used polynomial xn þ xþ 1 for

both LFSR and LT-LFSR of different lengths. The results are

shown for both combinational and sequential ISCAS (’85

and ’89) benchmarks. We have selected the four largest

ISCAS’85 and four largest ISCAS’89 benchmarks in our

experiments. All circuits are synthesized using Synopsys’

Design Compiler [24]. The same tool is used for scan chain

insertion for ISCAS’89 benchmarks. Twenty scan chains

were inserted into these ISCAS’89 benchmarks. The circuits

are optimized using the Artisan TSMC library based on

0.18 �m technology. Fault coverage is obtained using the

TetraMax tool [24] from Synopsys. Power consumption has

been measured at the gate level using PrimePower [24],

assuming a power supply voltage of 1.8 V. PrimePower

reports the entire power consumed in the circuit-under-test

and that includes scan-in, power consumed in combina-

tional blocks, and scan-out power. The simulation is

performed with back-annotation using a standard delay

format (SDF) file containing the delay information of each

gate in the netlist. This process is performed for all two test

data sets, that is, LFSR and LT-LFSR.Below, we summarize the steps used in obtaining the

fault coverage and the required number of test patterns for

LFSR and LT-LFSR:

1. First, the test patterns are generated using an LFSRwritten in C++.

2. The required number of test patterns (Np of LFSR) totarget a certain fault coverage ðFC�Þ is obtainedusing a Fault Simulator in TetraMax [24].

3. Low-power test patterns are generated usingLT-LFSR with the same seed as used for LFSR inStep 1, again written in C++.

4. Repeat Step 2 to achieve the same FC� for LT-LFSRpatterns. Note that TetraMax has an option that asksthe user to enter the desired fault coverage. Here, weare trying to compare the required number ofpatterns for both LFSR and LT-LFSR that achievethe same fault coverage. Therefore, the same faultcoverage obtained from Step 2 is used as the targetfault coverage in this step. The required number oflow-power patterns (Np of LT-LFSR) to meet thesame FC� is obtained.


Fig. 15. The clock scheme of LT-LFSR.

Fig. 16. Distribution of 0s of random pattern generated using LT-LFSR.

Fig. 17. Distribution of number of transitions between consecutive

patterns generated using LT-LFSR.

Fig. 18. Distribution of the number of transitions in each pattern

generated using LT-LFSR.


Table 1 shows the specifications of the ISCAS bench-marks and the number of test patterns ðNpÞ required to hit atarget fault coverage ðFC�Þ for LFSR and LT-LFSR. Thistable also compares our results with techniques proposed in[23] and [4] for the number of patterns and fault coverage.Referrence [23] and [4] report results only on combinationaland sequential benchmarks, respectively. Reference [4]seems to limit Np and, thus, achieves a lower fault coverage.

In general, the performance of both LFSR and LT-LFSR(Np to hit FC�) is seed and polynomial independent.According to this table, to hit the target FC�, LT-LFSR usesat mostþ=�10 percent more/less patterns than that of LFSRfor the majority of the benchmarks. As seen in a few cases (forexample, c1908 and c5315), Np slightly (13.3 percent and1.6 percent, respectively) drops, showing that some of theintermediate patterns did a good job in fault detection. Weused 50 different seeds for 10 different polynomials in ourexperiments and the results were almost the same as whatwas shown in the table. This confirms that the perfor-mance is seed and polynomial independent.

The comparison between LT-LFSR and other techniquessuch as those proposed in [14], [15], [16] is not feasible sincethose are conceptually different. These techniques try tofilter the nondetecting vectors that result in reduction in theaverage test power and may also reduce the peak power.However, if the pattern that causes the peak power is adetecting pattern, then it will not be masked and the peak

power will not be reduced. A preprocessing step is alsorequired to find the nondetecting patterns. The techniqueproposed in [17] reduces the power during test bysuppressing the output switch during shifting. The techni-ques proposed here and in [14], [15], [16] are different fromthat in [17] since these techniques work on test patterns.Compared to all of these techniques, our proposedtechnique reduces the switching activity among patternsand this has given us a significant reduction in both peakand average power.

6.2 The Rate of Growth of LT-LFSR Fault Coverage

Fig. 19 shows the rate of the growth of fault coverage for thes38584 benchmark. The figure shows that the new LT-LFSRincreases the fault coverage almost the same way as anLFSR does. The empirical results shown in Table 1 and inthis figure verify the argument in Section 5 that the requirednumber of LT-LFSR patterns to provide a target faultcoverage ðFC�Þ does not quadruple. In fact, due topreserving randomness in LT-LFSR, the number of patterns(and, therefore, the required time) to hit FC� remains quiteclose to the number of LFSR patterns.

6.3 Average and Peak Power Reduction

Table 2 shows the average and peak power of LFSR and LT-LFSR for ISCAS benchmarks. As expected, LT-LFSRsignificantly reduces the average and peak power. Table 3shows the average and peak power reduction of LT-LFSRcompared to LFSR, that is, �Pavg ¼ PavgðLFSRÞ�PavgðLT�LFSRÞ

PavgðLFSRÞ .As shown, LT-LFSR reduces up to 77 percent and 49 percent


TABLE 1Applying LFSR and LT-LFSR to ISCAS Benchmarks

Fig. 19. The rate of growth of fault coverage for the s38584 benchmark.

TABLE 2Average and Peak Power for ISCAS Benchmarks


of the average and peak power, respectively. Compared to[23] and [4], our technique, in most cases, provides a largerreduction of the average and peak power.

6.4 Instantaneous Power

Instantaneous power (that is, power surge between two

consecutive patterns) can put a lot of stress on circuits (forexample, formation of hot spots) and, thus, is a matter ofconcern. Our LT-LFSR significantly lowers the chance ofinstantaneous power violations. Fig. 20 shows the instanta-neous power waveform for the first 500 patterns appliedusing LFSR and LT-LFSR for c880 benchmark. The para-

meter Pthr represents the instantaneous power limit set bythe user. For this particular benchmark, Pthr ¼ 9:0�W . Thetest patterns generated by LT-LFSR cross this limit muchless frequently than LFSR patterns. In this particularbenchmark in the same simulation period, LT-LFSRpatterns violate the power limit ðPthrÞ only 21 times,whereas LFSR patterns violate Pthr 106 times. The more

violations there are of such a limit, the more chances thereare of damaging the circuit.

6.5 Power Consumption of LFSR and LT-LFSR

We also explored the power consumption of LFSR andLT-LFSR themselves used in the benchmarks. Table 4compares the power consumption of the RI of LT-LFSR,including its FSM and LFSR. Depending on the size, the

power consumption of LT-LFSR is 14-22 percent less thanthe same size of LFSR.

6.6 Area Overhead

As mentioned before, FSM can be a part of an on-chip BISTcontroller to control the test pattern generation process. Thesize of FSM is fixed, that is, 46 equivalent NAND gates.Table 5 shows the area increase for ISCAS benchmarkswhen they use LT-LFSR instead of LFSR. As seen in thetable, using LT-LFSR, the overall test area overheadincreases up to 13 percent. Compared to a conventionalLFSR, test overhead is almost negligible, especially for largecircuits such as s38417 and s38584.

7 CONCLUSION

This paper presents a new low-power LFSR to reduce theaverage and peak power of combinational and sequentialcircuits during the test mode. The switching activity in theCUT and scan chains and, eventually, their powerconsumption are reduced by increasing the correlationbetween patterns and also within each pattern. Theexperimental results indicate up to 77 percent and49 percent reduction in the average and peak power,respectively, with test overhead less than 13 percent. This is


TABLE 3Average and Peak Power Reduction

Fig. 20. Instantaneous power in LFSR and LT-LFSR.

TABLE 4Comparing the Power Consumption of LT-LFSR and LFSR

TABLE 5Test Overhead (Equivalent NAND Gate)


achieved with almost no increase in test length to hit a

target fault coverage. LT-LFSR significantly reduces the

instantaneous power violation compared to the LFSR and,

thus, avoids putting stress on the circuit during test.

ACKNOWLEDGMENTS

A preliminary version of this paper was published in the

Proceedings of the 14th IEEE Asian Test Symposium (ATS ’05).

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Mehrdad Nourani received the BSc and MScdegrees in electrical engineering from the Uni-versity of Tehran, Iran, in 1986 and the PhDdegree in computer engineering from CaseWestern Reserve University, Cleveland, Ohio,in 1993. In 1994, he was a postdoctoral fellow inthe Department of Computer Engineering atCase Western Reserve University. He served inthe Department of Electrical and ComputerEngineering at the University of Tehran from

1995 to 1998 and the Department of Electrical Engineering andComputer Science at Case Western Reserve University from 1998 to1999. Since August 1999, he has been on the faculty of the University ofTexas at Dallas, where he is currently an associate professor ofelectrical engineering and a member of the Center for Integrated Circuitsand Systems (CICS). His current research interests include design fortestability, system-on-chip testing, signal integrity modeling and test,application specific processor architectures, packet processing devices,high-level synthesis, and low-power design methodologies. He haspublished more than 120 papers in journals and refereed conferenceproceedings. He is a senior member of the IEEE and a member of theIEEE Computer Society and ACM SIGDA. He received the TexasTelecommunications Consortium Award in 1999, the Clark FoundationResearch Initiation Grant in 2001, the US National Science FoundationCareer Award in 2002, and the Cisco Systems Inc. URP Award in 2004.He received a best paper award at the 2004 International Conference onComputer Design.



Mohammad Tehranipoor received the BScdegree from the Amirkabir University of Tech-nology (Tehran Polytechnic University), Iran, theMSc degree from the University of Tehran, andthe PhD degree from the University of Texas atDallas, in 1997, 2000, and 2004, respectively, allin electrical engineering. He is currently anassistant professor of electrical and computerengineering at the University of Connecticut. Hewas a faculty member in the Computer Science

and Electrical Engineering Department at the University of MarylandBaltimore County (UMBC) from 2004 to 2006. His current researchinterests include computer-aided design and test for CMOS VLSIdesigns and emerging nanoscale devices, design-for-testability, at-speed test, secure design, and IC trust. He has published more than70 journal articles and refereed conference papers in the area of VLSIdesign and test. He has published two books, Nanometer TechnologyDesigns—High-Quality Delay Tests and Emerging Nanotechnolo-gies—Test, Defect Tolerance and Reliability, in addition to two bookchapters. He was a recipient of a best paper award at the 2005 VLSITest Symposium (VTS), a best paper candidate at the DesignAutomation Conference (DAC) in 2006, a recipient of a best panelaward at VTS ’06, and a recipient of top 10 paper recognition at the 2005International Test Conference (ITC). He has served on the programcommittees of several workshops and conferences in addition to servingas session chair for many technical events. He has served as a guesteditor of the Journal of Electronic Testing: Theory and Applications(JETTA) on “test and defect tolerance for nanoscale devices” and IEEEDesign and Test of Computers on “IR-drop and power supply noiseeffects on very deep-submicron designs.” He has also served as theprogram chair of the 2007 IEEE Defect-Based Testing (DBT) Workshop.He will also be serving as co-program chair of the 2008 InternationalDefect and Fault Tolerance in VLSI Systems (DFT). He serves as anassociate editor of JETTA. He is a member of the IEEE, the IEEEComputer Society, the ACM, and ACM SIGDA.

Nisar Ahmed received the BE degree inelectronics and communication engineering fromOsmania University, India, and the MS degree inelectrical engineering from the University ofTexas at Dallas. He is currently working towardthe PhD degree in electrical and computerengineering at the University of Connecticut.His current research interests include computer-aided design and test, at-speed low-cost test,and IR-drop effects on delay test. He is a student

member of the IEEE and the IEEE Computer Society.

. For more information on this or any other computing topic,please visit our Digital Library at www.computer.org/publications/dlib.



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Low-Transition Test Pattern Generation for BIST-Based Applications

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