Problems NOTE: For all problems the device and circuit parameters and values are given in the appropriate figures. Pl.l Two emitter-coupled pairs are shown in Figure Pl.l. (a) For the resistive load circuit of Figure Pl.la, determine the bias state of the circuit for V 1 = 0. (b) Repeat (a) for the circuit with an active load as in Figure Pl.lb. Note that VA =50 V for the pnp units. (c) Determine the small-signal performance of the circuit of (a) about the quiescent bias point. (d) Estimate the small-signal gain of the active- load circuit. (e) Verify your results with appropriate Spice runs. (f) Estimate the harmonic distortion of the circuit of Figure Pl.la with an input sinusoidal amplitude of 50 mV. (g) Check your distortion estimate with a Spice run. (h) Use Spice to determine the distortion for the circuit of Figure Pl.lb with a 1.5 mV sinusoidal input. (i) Use Spice to investigate the distortion generation of the active-load circuit if the parameter VA = 100 V is added for the npn transistors. For the input, use an offset voltage of 5 m V and a sinusoidal amplitude of 1.5 mV. P1.2 An emitter-coupled pair is shown in Figure P1.2. (a) For V 1 = v2 = 0, determine the quiescent bias state of the circuit. (b) If the signal input is V 1 and the output voltage is V0 as shown, what are the input and output resistances and the small- signal voltage gain of the circuit? (c) Verify your estimates of (a) and (b) with Spice. (d) Plot the (large-signal) voltage-transfer characteristic of the circuit. Check the value of gain estimated in (b) both from the above plot and from a .TF output of Spice. (e) Estimate the harmonic distortion of 549
Transcript
Problems
NOTE: For all problems the device and circuit parameters and values are given in the appropriate figures.
Pl.l Two emitter-coupled pairs are shown in Figure Pl.l. (a) For the resistive load circuit of Figure Pl.la, determine the bias state of the circuit for V1 = 0. (b) Repeat (a) for the circuit with an active load as in Figure Pl.lb. Note that VA =50 V for the pnp units. (c) Determine the small-signal performance of the circuit of (a) about the quiescent bias point. (d) Estimate the small-signal gain of the activeload circuit. (e) Verify your results with appropriate Spice runs. (f) Estimate the harmonic distortion of the circuit of Figure Pl.la with an input sinusoidal amplitude of 50 mV. (g) Check your distortion estimate with a Spice run. (h) Use Spice to determine the distortion for the circuit of Figure Pl.lb with a 1.5 mV sinusoidal input. (i) Use Spice to investigate the distortion generation of the active-load circuit if the parameter VA = 100 V is added for the npn transistors. For the input, use an offset voltage of 5 m V and a sinusoidal amplitude of 1.5 mV.
P1.2 An emitter-coupled pair is shown in Figure P1.2. (a) For V1 = v2 = 0, determine the quiescent bias state of the circuit. (b) If the signal input is V1 and the output voltage is V0 as shown, what are the input and output resistances and the small- signal voltage gain of the circuit? (c) Verify your estimates of (a) and (b) with Spice. (d) Plot the (large-signal) voltage-transfer characteristic of the circuit. Check the value of gain estimated in (b) both from the above plot and from a .TF output of Spice. (e) Estimate the harmonic distortion of
549
550
llpll
Is= 1o·••A
~·= 100
v,
Figure Pl.l
Is= 1o·••A Po= 100
Figure P1.2
-9V
(a)
3Kil
v,
ANALOG INTEGRATED CIRCUITS
-9V
(b)
pap
lo=10"15 A
Pp=30 VA=50V
-SV
k'=30J1AIV", VT=O.SV, ~=12
Figure P1.3
PROBLEMS 551
the circuit with a sinusoidal input amplitude of 60 mV. Verify your estimate with Spice. (f) Repeat Parts (a) through (e) with V2 = 0.03 v.
Pl.3 A MOS source-coupled pair is shown in Figure P1.3. (a) Determine the voltage transfer characteristic of the stage. (b) Estimate the small-signal voltage gain and the level of HD3 for an input amplitude of 1 V. (c) Verify the results of (b) with Spice.
P2.1 The voltage transfer function for an output stage is shown in Figure P2.1. For a bias input of 2 V and a sinusoidal input voltage of 4 V, estimate the value of THD in the output voltage waveform.
P2.2 A MOS stage is shown in Figure P2.2. (a) Use Spice to establish the de transfer characteristic of the stage. (b) Choose a load resistor to approximate the actual stage loading and achieve an idealized, basic stage. (c) Choose a quiescent input bias voltage and an input sinusoidal amplitude to achieve 'just clipping' of the peaks of the output voltage. Estimate the values of HD2 and HD3. Verify with Spice. (d) For the input conditions of(c) using the de transfer characteristic of (a), use a three-point distortion analysis to estimate HD2, and a five-point distortion analysis to estimate HD2 and HD3. Verify your estimates with Spice.
P3.1 A bipolar stage is shown in Figure P3.1. (a) Develop for the stage an idealized, basic configuration. (b) For Rs = 0.5 n, estimate HD2 and HD3 for a sinusoidal input amplitude of 15 mV. The input bias voltage must be chosen to achieve the specified bias state of the stage, Ic = 1 rnA. Verify with Spice. (c) For Rs = 0.5 0, what is the practical maximum of input amplitude to achieve a reasonable output voltage waveform. (d) For Rs = 1.5 KO, estimate HD2 and HD3 with an input amplitude to achieve the same fundamental output voltage as in (b). Compare results. Note that the input bias voltage must be also adjusted to maintain the same quiescent collector current. (e) For Rs = 100 KO, and with lKF = 8 rnA and h = 0.04 rnA, determine the THD for the stage if the input amplitude is adjusted to achieve 'just clipping'. The quiescent bias state of the circuit should remain that of Part (b).
P3.2 A common-emitter stage including a signal-source resistance is shown in Figure P3.2. (a) For Rs = 100 KO and with V. = VBB + V.Acosw1t, determine HD2 and HD3 if the quiescent bias state is Ic = 0.5 rnA and the fundamental output voltage amplitude is 4 V. Use Spice as appropriate. (b) For Rs = 10 KO, re-establish the
552 ANALOG INTEGRATED CIRCUITS
PROBlEMS 553
same quiescent bias state and determine the necessary input drive to achieve the same fundamental output voltage amplitude. Compare the values of HD2 and HD3 for the transistor parameters of Figure P3.2 and for the case where beta is constant at the value of BF.
P4.1 A common-emitter stage with series feedback and with a finite source resistance is shown in Figure P4.1. (a) For Rs = 0 and with Vss chosen to produce Ic = 0.5 rnA, estimate the value of R. needed to eliminate HD3. Verify with Spice for the case where the input signal amplitude is 20 m V. (b) What value of Rs with R. = 0 provides the same estimated cancellation at the same quiescent bias state? Compare Spice results with those of (a).
P4.2 A MOS stage is shown in Figure P4.2. (a) Use Spice to establish the de transfer characteristic of the stage. (b) Confirm that the values of Vaa = 1.7 V and V.A = 0.4 V are suitable values at the input. (c) For R1 = oo, estimate the value of HD2 for the drive of (b). Confirm your estimates with Spice. (d) For RJ = 200 KO, estimate THD for the same drive. Confirm with Spice. (e) For R1 = 200 KO and Rs = 0, what is HD2.
P4.3 A emitter-coupled pair with emitter resistances is shown in Figure P4.3. Determine HD3 for V1 = 0 + 50mV cosw1t.
P4.4 The de current transfer characteristic for a BJT stage is shown in Figure P4.4. For a de input which provides a collector current of 4 rnA and an input sinusoidal voltage of 2.0 V, use the method of differential error to estimate HD2 in the output waveform.
P5.1 An emitter-follower stage is shown in Figure P5.1. (a) Estimate the maximum value of VlA for a reasonable output voltage waveform. (b) For VlA = 9 V, use Spice to establish THD. Check results with differential error estimation. (c) Can feedback ideas and formulations be used to estimate the THD for the drive condition of (b)? (d) For the drive of (b), determine the average power delivered to the load, the average power supplied by the de voltage sources, and the power-conversion efficiency.
P5.2 A source-follower stage is shown in Figure P5.2. (a) Establish the value of Vas to produce Vo = 0 V. (b) For V,A = 2 V, estimate HD2 and HD3 using an analysis technique of your choice. Verify with Spice. What is the maximum value of V.A for adequate operation? (c) For v.A = 2 v, determine the average power delivered to the load, the average power supplied by the de voltage sources, and the power conversion efficiency.
554
Figure P4.3
.,.
Figure P4.4
· lOY
Figure P5.1
v,
Is • 10 · 1 ~ A
~ . - 100
v,
• IOV
I KO
ANALOG INTEGRATED CIRCUITS
· lOV
l c ( rnA) 4
f. v,
= 0
Figure P5.2
11 ( ~A )
·5V
Vy::o:,. 0.7V k' ~ 30~AN' f~ 12
R,. • IOKO
PROBLEMS 555
P5.3 A push-pull emitter-follower is shown in Figure P5.3. (a) Replace transistor Q3 with a voltage source, V,, the quiescent value of which produces a de current of 1 rnA in the transistors. Note that all the transistors of the same type have the same Is. Determine the necessary sinusoidal input amplitude to achieve 'just clipping' of the output voltage waveform. (b) Use the method fo differential error to estimate THD for V.A = 4.5 V. (c) Estimate the efficiency of power-supply conversion for the conditions of Part (b). (d) Replace V. with Q3 and V1 . Find the necessary value of the bias of the input voltage to produce currents of 1 rnA in the transistors. Determine the necessary sinusoidal drive to achieve the output amplitude of (b). Comment on the difficulties of this request. Establish the distortion in the output voltage waveform for your choice of drive.
P6.1 A transformer-coupled amplifier is shown in Figure P6.1. The transformer turns ratios are to be determined. Both transformers have a primary-side magnetizing inductance of 1 H and a core loss modeled by a shunt 10 Kn resistance at the primary. The coefficient of coupling for each unit is approximately one. (a) For no feedback, R1 = oo, design the circuit to achieve the desired de state. Specifically state the quiescent operating point of each transistor. (b) For R J = oo, determine the turns ratio of the transformers to achieve maximum power transfer. (c) For an approximate maximum unclipped output voltage, estimate TJ, the power conversion efficiency, and HD2 of the output voltage. (d) If the turns ratio of the output transformer is adjusted, can a better conversion efficiency be obtained? (e) Above what input frequency is proper high-pass operation produced? (f) Choose R J so that a loop gain of 20dB is obtained for the design conditions of (b). How are the values of TJ and HD2 changed if the fundamental of the output voltage is maintained.
P6.2 A push-pull transformer-coupled stage employing MOS devices is shown in Figure P6.2. Determine the input voltage level to provide maximum unclipped output voltage. What is the ac power output and the THD for this input?
P7.1 Design a bandpass stage having the configuration shown in Figure P7.1 to achieve a center frequency of 3 MHz with a -3dB bandwidth of 50 KHz. Determine the pole locations. Use Spice to find the frequency response for transformer couplings of k = 1.0 and k = 0.8.
P8.1 A bandpass amplifier based upon an active RC circuit is shown in Figure P8.1. Design the circuit to provide an approximate single-
556 ANALOG INTEGRATED CIRCUITS
IIJlll Is= 10·15 A
p.~200
JIIIP la=l0"15 A
p.~ 30
v,
,-----,..--- +SV
v. 3K!l
v,
'-----J.__ -SV
Figure P5.3 Figure P6.1
+IOV
Ollo~IK0 1 ,:
v, .18--+-,
'------1
Figure P6.2
Figure P7.1
MOS ~: k' ~ 30 111JV2, Vro = 0.4 V, r. ~ 0
Alaume I. :ia llrge for beth tnnafonncn
~'IT.v. ·y~-oooo
3000
Is~ 10·16 A
p.~ 100
v_.~sov
PROBLEMS
v,
Figure P8.1
v,
Ia= 1o·••A ~·= 100 v .. =S(JV
Figure P8.2
Vm=0.7V
k'=3011Af\"'
A=O
~=10
+lOV
+ 10V
• • R,.=10KO
n.:1(f t.,.,, kl
-10V
(a)
557
-10V
(b)
558 ANALOG INTEGRATED CIRCUITS
tuned bandpass response with a center frequency of 10 MHz with a Q of 30. Confirm your design values with Spice simulations.
P8.2 A bandpass amplifier is shown in Figure P8.2a. (a) Design the amplifier to produce a center frequency of 1 MHz with a -3dB bandwidth of 50 KHz. Provide maximum power transfer at the output. (b) What is the value of the center frequency voltage gain? (c) What is the rejection of a signal at 1.5 times the center frequency. (d) Redo Part (a) including a tuned circuit at the EC pair input as illustrated in Figure P8.2b.
P8.3 Design the MOS bandpass amplifer in Figure P8.3 to provide a center frequency of 10 MHz with an overall Q of 30. The turns ratios of the transformers are limited to 1/10 ~ n ~ 10 with a coefficient of coupling approximately 1. Confirm your design values of center frequency and bandwidth with Spice simulation.
P9.1 A RC oscillator is shown in Figure P9.1. (a) Find R, to achieve a van der Pol parameter E of 0.1. (b) Estimate the frequency of the buildup of oscillation. Estimate the frequency of steady-state operation. (c) Estimate and justify the amplitude of the output voltage for steady-state operation. (d) What is the amplitude of Vin in steadystate operation?
P9.2 An EC pair oscillator is shown in Figure P9.2a. (a) Design the oscillator to achieve a steady-state output with a frequency of 10 MHz. The maximum turns ratio for the transformer is 10. Estimate and confirm the value of the steady-state output voltage. (b) Use Spice simulation to investigate the effects of the BJT parameters VA = 100 v, RB = 100 n, and CJc = 1 pF. (c) Can oscillation be achieved if one winding of the transformer is reversed and feedback connection is made to the base of Q2 as shown in Figure P9.2b. If so, how do your results compare with those of Part (a). (d) Replace the BJTs of Figure P9.2a with MOS devices, having the size and parameter values of Figure P9.2c. Adjust the circuit parameters to achieve oscillations. Compare your results with those of Part (a).
PlO.l An oscillator configuration is shown in Figure P10.1. (a) Design the circuit to achieve an oscillation frequency of 100 MHz with a van der Pol parameter of 0.3. (b) Establish the effects on the performance of the circuit if the transistor parameters include VA = 100 V, R 8 = 100 n, CjeO = CjcO = 0.1 pF and Tp = 0.1 ns.
P10.2 A source-coupled oscillator is shown in Figure P10.2. (a) Design the oscillator to achieve a steady-state output with a frequency of
PROBlEMS
V10 = 0. 7 V
k' = 30~AN"
'-=0.01
~=10
03
1m ···a1 . . v, c,
Figure P8.3
Figure P9.1
-IOV
(b)
Figure P9.2
R.= 2R, = 10KO
C, =i-C, = 100pF
opArnp: "" • 10'
Turns ntio n: 1: 1
Is= tO·I6A
~.= 100
Figure P9.2 (a)
(c)
Turns ratio n: 1: 1
Is= w·" A
~·= 100
~=20
k' = 30 ~NV"
Vro=0.5V
v='-=O
559
560
+SV
·"'[p Vo
-SV
Figure PlO.l
Figure P 11.1
k' ~ 30 ~Af\1'2
vT~ o.7 v
Figure P11.2
lOOp!'
Is= to-15 A
~.~ 100
lOOp!'
ANALOG INTEGRATED CIRCUITS
S:ln:Vo 43000
'---.....-----'~ 1~ ~~~
-lOV
Figure P10.2
Is= to-tiS A
p.~ 100
Ra chosen for lA =Is= 100 liA whenV;,=O
-SV
Figure P11.3
Is= to-tiS A
P.~ 100
Rs
-SV
PROBLEMS 561
10 MHz. The Q of the tuned circuit including the load resistance cannot exceed 20. Justify your choice of the ratio of Ca. and Cb and of the values of Rat and Ra2· (b) Can Ra2 be reduced to zero? (c) Estimate and confirm the value of the steady-state output voltage. (d) Use Spice simulation to investigate the effects of M OS parameters ~ = 0.02, C9d.O = C9, 0 =50 fF.
Pll.l A voltage-controlled oscillator is shown in Figure Pll.l. Note the transistor current sources. (a) For Vin = 0, determine the frequency of oscillation and sketch the waveforms at the base and collector of Q2. (b) Determine the range of voltage control and the corresponding range of frequency of oscillation.
P11.2 A relaxation oscillator using NMOS inverters is shown in Figure P11.2. (a) Determine the steady-state operation of the circuit and the frequency of oscillation. Sketch all voltage waveforms. (b) If the resistors Rv in Figure P11.2 are replaced with enhancement-mode devices with W /L = 5, establish the operation of the circuit and the frequency of oscillation. Compare this performance with that of Part (a).
P11.3 A bipolar relaxation oscillator is shown in Figure Pl1.3. (a) Determine the steady-state operation of the circuit and the frequency of oscillation. Sketch all voltage waveforms. (b) Estimate the change in performance if devices Qa and Q4 are replaced with short circuits from base to emitter.
P12.1 An analog multiplier used as a frequency translator is shown in Figure P12.1 (a) Determine the amplitude of the difference-frequency component of the output voltage across the tuned circuit which is tuned to the difference frequency. Clearly state any assumptions that you make. (b) Estimate the ratios of the amplitudes of the differencefrequency component of the output voltage to the output components at the fundamental frequencies of the input signals.
Pl2.2 A single-device mixer is shown in Figure P12.2. (a) Design the tuned circuit to resonate at the difference frequency. (b) Determine the amplitude of the difference frequency output. (c) What is the ratio of the desired output amplitude of Part (b) and the fundamental output due to the local oscillator.
P13.1 An AM peak detector is shown in Figure P13.1. The input voltage has a carrier amplitude of 4 V with a modulation factor of 0.8. The carrier frequency is 0.5 MHz and the single-tone modulation frequency
562
k' ~ 30 ~AN'
VT=0.6V
f~zo 1-~v~o
Figure P12.1
Figure P13.1
Figure Pl5.1
~ 0.2mA
L--.JL- -10 v
L=3.8mH C= 667pF
25: I
ANALOG INTEGRATED CIRCUITS
v,
Voo
+lOV
Q=25
k' = 30~AIV' VT=0.6V
f=20
l.=v=O
v.= 100mVooa211{t,. 107}:
V]o= lVros2n{1.1 >< 107}
Figure P12.2
PROBLEMS 563
is 10 KHz. (a) Use the series 1 0 resistor as shown in the figure to connect the input and the diode and determine a suitable value for the filter capacitor CL. (b) Determine the harmonic distortion of the output voltage at the modulation frequency. (c) Replace the 1 0 series resistance with the tuned transformer circuit shown in the figure. The center frequency is 0.5 MHz with a Q of 20. Determine the THD of the modulation output. Compare the results with those of (b).
P14.1 In an IC phase-locked loop, the free-running frequency ofthe VCO is 10 MHz. The maximum deviation of the input frequency is 50 KHz about a carrier frequency equal to the free-running frequency of the VCO. For the phase detector of the PLL the output is 6 V /rad. (a) What value of Ko for the VCO is needed to achieve proper operation? (b) Sketch the closed-loop magnitude response of Vo/Wi if no lowpass amplifier is included and if a one-pole filter is used in the PLL with a -3dB frequency of 50 KHz.
P14.2 A phase-locked loop has the parameters, Kp = 3 V /rad, Ko = 15 KHz/V. For a filter with a one-pole lowpass response, establish the corner frequency of the filter and the gain constant A of the PLL to achieve a closed-loop, double-pole response with a closed-loop, -3dB bandwidth of 50 KHz. (Hint: A two-pole bandwidth shrinkage factor can be used.)
P15.1 A full-wave bridge rectifier is shown in Figure P15.1. Determine the average output voltage and the ripple. The input voltage is 117 V RMS at a frequency of 60 Hz.
P15.2 A simple series regulator is shown in Figure P15.2. (a) Determine the output voltage with RL of 1MO, lOKO, lKO, and 0.2KO. (b) What is the load regulation? (c) Change the input voltage to 18 V. What is the line regulation? (d) Modify the values of R 1 and R 2 to achieve an output voltage of 8 V? (e) Is the load regulation affected by the changes of Part (d).
P15.3 A buck converter is shown in Figure P15.3a. A suggested Spice model is shown in Figure P15.3b. The switching frequency is 100 KHz. (a) Choose L, C, and the duty cycle D to make Vo = 5 V and the peak- to-peak ripple, ~ V0 = 0.5 V. The averaged response should have Q = 1. (b) How is the transient response changed if R = 5000, R = 500?
564
Figure Pl5.2
Figure Pl5.3
v
ISVh n n
0~-: PULSE(O ISOOODTT)
T~-L f..;tch
ANALOG INTEGRATED CIRCUITS
(a)
(b)
Index
AGC, 434, 466 AM demodulation, 451,455,457 Amplifier power series, 31 Amplitude modulation, 435,449,451 Analog multipliers, 413,425, 431 Astable circuit, 369, 384, 390, 393,
400 Automatic gain control, 434, 466 Autotransformer, 179
