Reconfigurable Architecture of Adaptive Median Filter – An FPGA Based Approach for Impulse
Noise Suppression
Abstract--In this paper, low complexity reconfigurable hardware architecture for adaptive median filter is proposed and a comparative study of hardware based median and adaptive median filter is presented. An efficient development of median & adaptive median filter is presented for removal of impulse noise mainly salt & pepper noise from digital Images. Performance measurement of mean square error (MSE) and peak signal-to-noise ratio (PSNR) is done to compare these two filters. This paper proposes hardware implementation which is highly required for real time execution. Field Programmable Gate Arrays (FPGAs) are widely used for real time processing where the requirements of time, speed, area, power become strict. The algorithms of these two filters are discussed in detail which is followed by FPGA based solutions. Simulation is done using Xilinx ISE 14.5 software of XILINX platform where the implementations utilize on Genesys VERTEX V FPGA Board of XC5VLX50T device family. Keywords--Adaptive Median Filter, Median Filter, Real-time Filtering, Salt-and-pepper noise, Impulse Noise, Field programmable gate array (FPGA).
Our main goal is efficiently removing the fixed-valued impulse noise from the corrupted image which is presented in this paper. Recently, many image denoising methods have been proposed for impulse noise suppression [8]-[18]. Some of them employ the standard median filter [8] or its modifications [9], [10]. These approaches modify both noisy and noise-free pixels such that the resulting images are blurred. Filters are chosen according to their noise pattern in the field of image processing. In case of order statistics filters, non linear filters perform better than linear filters. A proposal was made for correlation between a number of non linear filters and vectors by using various distance measurement [19]-[21]. Analysis and comparisons of different filtering discussed in algorithms are already quite a few literatures and number of different improved algorithms are put forwarded [22][23]. Comparing with software implementation, hardware implementation can result better speed with the help of pipelining and parallelism technique. Reconfigurable nature of FPGAs consisting with pipeline and parallelism technique makes it efficient to reduce the complexity of algorithms and simplify the debugging and verification. In this paper, the algorithms of median and adaptive median filter are proposed in the means of hardware implementation for removal of impulse noise considering salt and pepper noise from grayscale images. The proposed algorithms are capable for 8-bit grayscale image processing and as image neighborhood, 3x3 and 5x5 moving window are chosen which are also expandable as the design needs. The hardware implementations are done on FPGAs [2] which associate with flexibility, high performance and low cost. These two designs can be implemented for real time imaging applications where ultimate importance is fast processing [24]. This paper consists of five sections containing a brief overview of median and adaptive median filter, the architecture of the adaptive median filter, implementation issues, Performances of these two hardware based filters, and conclusions respectively.
Manali Mukherjee Dept. of Information Technology
Govt. College of Engg. & Ceramic Technology West Bengal, India
Mausumi Maitra Dept. of Information Technology
Govt. College of Engg. & Ceramic Technology West Bengal, India
Kamarujjaman Dept. of Information Technology
Govt. College of Engg. & Ceramic Technology West Bengal, India
2. BRIEF OVERVIEW OF FILTERS
A. Median Filter One of the nonlinear filters is median filter. Median filtering has proved an effective way to satisfy the dual requirements of removing impulse noise while preserving rapid signal changes [25][26]. Comparing with linear filtering, non-linear filtering give better result in image processing [27]. A classic general purpose Median filter is based on a sorting approach over the entire window elements to find the median value. Median filters operate by replacing a given sample in a signal by the median of the signal values in a window around the sample. A block diagram of median filter is depicted in Figure 1.
Figure 1. Block diagram of median filter Suppose I is an input image and p is any point at I. For calculation of median value of p (€I) neighbor pixels are needed. Neighborhood pixels can find by designing a window W, considering p as origin. If the total number of elements (n) in W is odd then n=2m+1, where m is positive integer. The n values are I(p1), I(p2),....... , I(pn) of n points p1,p2,......, pn of I are sorted in ascending order, forming the order set { I1,I2,..... , In} such that I1 ≤ I2 ≤ ....... ≤ In. Median=Im+1 , (m+1)th value of {I1,I2,........ , In}.
B. Adaptive Median Filter Our proposed method is a combination of adaptive median filter with switching median filter. We use the adaptive median filter framework to enable the flexibility of the filter by change its window size accordingly based on the approximation of local noise density. Switching filter is required to filter only the noise pixels such that the process should increase its speed and local details of images should be preserved.
Figure 2. Block Diagram of Adaptive Median Filter
3. ARCHITECTURE DESIGN OF ADAPTIVE MEDIAN FILTER
The proposed architectures are designed in pipeline manner to minimize computational time. Parallel
processing has also been done for process acceleration. A 3x3 or 5x5 pixel image neighborhood can be selected for computation of the filter output. The design of the adaptive median filter consists of five different operational stages which are described in the following paragraphs. The hardware structure of adaptive median filter and the computation procedure are illustrated in Figure 3. In the following subsections the design and functional characteristics of previously mentioned stages are described in detail.
Figure 3. Hardware Design of Adaptive Median Filter
A. Stage I The pixel values of the input image are imported into this module serially for computation of moving window. In order to obtain the n x n window, a set of dual port Delay Blocks are used to generate the row of the window. For generation of this window, n number of delay blocks are required in which the first block takes zero latency and the other takes latency one. A 5x5 window creation module is depicted in Figure 4.
Figure 4. Window Creation Module
B. Stage II In this stage, computation of median value is done from image neighborhood for substitution of central pixel value. For 5x5 window, hardware implementation of
median computation module is depicted in Figure 5(a) and 5(b).
Figure 5 (a). Median Computation Module
In the Figure 5(a), the input data of median computation module is the output of the filtering window creation module. In Figure 5(b), from stage 2, we can get the maximum and minimum output value. From stage 4, we can get the median value.
Figure 5 (b). Internal structure of 9 input sorter
The median computation module consists of 4 stages of comparing blocks. Each stage comprises of tri input comparators (SB) in Figure 6, whose outputs are organized in descending order. The maximum value of each comparator is put together as a group and that is the same with the median value and the minimum value of each comparator. From stage 4 we can get the median output value.
Figure 6. Diagram of Tri Input Sorting Block (SB)
C. Stage III The aim of noise detection module is to detect the noise pixel with the help of threshold value. Each central pixel should be compared with predefined threshold values (T1 & T2) shown in Figure 7.
Figure 7. Noise Detection Module
The central pixel is considered to be noise free when its value between T1 & T2, Otherwise it is considered as noisy pixel.
D. Stage IV The adaptive computation module is the most important part of the design. The aim of this module is to implement the adaptive algorithm. The output of this module is median value of 3 x 3 neighbor window or 5 x 5 neighbor window or central pixel depending on the adaptive condition. This module consists six comparator blocks, three logic blocks and three multiplexers depicted in Figure 8.
Figure 8. Adaptive Computation Module
E. Stage V The last stage of the design is shown in Figure 9. In this stage, the output value for the performed operation is selected depending on the output of noise detection module.
Figure 9. Output Selection Module
4. IMPLEMENTATION DETAILS The proposed adaptive median filter structure is designed, compiled and simulated using Xilinx ISE (v. 14.5) software of XILINX Inc. For flexibility and advantageous characteristics of FPGA, the hardware implementation has been done into it. FPGAs are now a mainstream logic technology and provide a way of
obtaining high performance on digital system design [28] at an economical price. The FPGA used for the proposed design is the Genesys Virtex5 board of the XC5VLX50T device family. The XC5VLX50T -2ff1136 device provides 120x30 CLB array, 28,800 number of 6-input LUTs, 28,800 number of slice registers, 28,800 number used as logic, 7,200 number of occupied slices, 480 kb maximum distributed RAM , 240 Kb shift registers and 28,800 number of Flip-flops is suitable for different kind of memory functions and large number of complex logic functions. The typical maximum operating clock frequency of the proposed designs is estimated by the timing analyzer using system generator of Xilinx ISE software. The proposed designs are successfully simulated with Isim simulator of Xilinx (14.5) software. First window output has been generated after 25 clock cycles and whereas remaining are generated after 5 clock cycles each.
5. RESULTS AND DISCUSSIONS In Figure 10, Figure 11, and Figure 12, the results of the application of median filter and adaptive median filter are presented on 8bit grey scale “Pepper”, “Lena”, and “Baboon” images. More specifically, Figure 10(a), presents the original uncorrupted “pepper” image. Figure 10(b) shows the original image degraded by 5% impulse noise (salt & pepper noise). In Figure 10 (c) and (d), and Figure 10 (e) and (f), the resultant images of the application of median and adaptive median filter for a 3x3 and 5x5 pixel window are shown respectively. These situations are same for Figure 11 and Figure 12.
(a) (b)
(c) (d)
(e) (f)
Figure 10. (a) Original image “Peppers”. (b) Corrupted image by 5% impulse noise. (c) Result of median filter using 3X3 window. (d) AMF result using 3X3 window. (e) Result of median filter using 5X5 window. (f) AMF result using 5X5 window
(a) (b)
(c) (d)
(e) (f)
Figure 11. (a) Original image “Lena”. (b) Corrupted image by 5% impulse noise. (c) Result of median filter using 3X3 window. (d) AMF result using 3X3 window. (e) Result of median filter using 5X5 window. (f) AMF result using 5X5 window
(a) (b)
(c) (d)
(e) (f)
Figure 12. (a) Original image “Baboon”. (b) Corrupted image by 5% impulse noise. (c) Result of median filter using 3X3 window. (d) AMF result using 3X3 window. (e) Result of median filter using 5X5 window. (f) AMF result using 5X5 window
Table 1 Design summary of proposed Median & Adaptive Median Filter in terms
of their Chip Utilizations
Table 2 Comparative results between Architecture Based Median Filter and
Adaptive Median Filter in terms of MSE
Table 3 Comparative results between Architecture Based Median Filter and
Adaptive Median Filter in terms of PSNR
6. CONCLUSION
In this paper, we present hardware design of adaptive median filter and give the performance measurement details in terms of MSE and PSNR. Table 1 shows the resource utilization details of median and adaptive median filter as they are designed in hardware manner. Table 2 and Table 3 shows the better hardware performances of adaptive median filter for noise removal than the reference [27]. Moreover, these designs are easily scalable to handle larger size windows with some small modifications.
ACKNOWLEDGEMENT
We acknowledge University Grants Commission (UGC), Govt. of India, for providing necessary fund through the Major Research Project “Development of IP Core for Implementation of Image Processing Algorithms on FPGA Board”.
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Summary of Slice Utilization
Median Filter (5x5)
Adaptive Median Filter (5x5)
Number of Slices 1296 1352
Number of LUTs 2400 2504
Number of Flip Flops 192 192
Number of IOBs 16 16
Peppers image Lena image Baboon Image
Size 5x5 5x5 5x5
Noise 3% 5% 3% 5% 3% 5%
median 26.82 26.43 25.54 25.41 22.72 22.63
AMF 42.97 40.38 40.97 38.41 38.19 36.05
Peppers image Lena image Baboon Image
Size 5x5 5x5 5x5
Noise 3% 5% 3% 5% 3% 5%
median 135.07 147.6 181.44 186.77 347.5 354.72
AMF 3.28 5.95 5.19 9.36 9.85 16.15
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