Reliability-based design guidance of 3D ICs packaging using

thermal compression bonding and dummy Cu/Ni/SnAg

microbumps

Chang-Chun Lee, Po Ting Lin*

Department of Mechanical Engineering, R&D Center for Microsystem Reliability,

Center for Biomedical Technology, Chung Yuan Christian University

200 Chungpei Road, Chungli City, Taoyuan County, Taiwan 32023 *Corresponding author. Tel: +886-983033147. Email address: potinglin@cycu.edu.tw

Abstract

In the latest microelectronics industry, the emerging three-dimensional (3D) chip

stacking technique using through silicon via (TSV) enables higher integration density that

allows greater numbers of interconnections in order to fulfill the urgent requirements of

dimensional downscaling and electrical speed enhancement. A high-density pitch of

microbumps associated with the wafer-level underfill (WLUF) under a thermal compressions

process are utilized to prevent the thermo-mechanical failures of the microbumps due to

variations of thermal expansions of different materials in the 3D package. The use of dummy

microbumps has been proposed to find the acceptable thin-layer uniformity and the reliable

mechanical performances of the entire packaging structure. The warpage and strain behavior

of packaging structure has been simulated by finite element analysis (FEA) and compared

with experimental results. The responses were parametrically modeled using Kriging model

with respect to compressive force, the thickness of the top chip, and the location of the

dummy microbumps. The deterministic design guidance for warpage and strain has been

obtained from the Kriging model. Furthermore, the reliability of the design under uncertainty

has been investigated. A Reliability-Based Design Guidance has been proposed to provide a

safety boundary in terms of the allowable reliability index. The proposed method can be

utilized as the reliability standard for high-throughput production of 3D ICs packaging.

Keywords: 3D ICs; Wafer Level Underfill (WLUF); Dummy microbumps; Under bump

metallization (UBM); Reliability index; Kriging.

1. Introduction

The latest microelectronics industry has migrated from two-dimensional integrated

circuits (ICs) to three-dimensional (3D) ICs due to rapidly growing demands of finer and

denser interconnections for faster and more powerful performances of the electronic devices.

The 3D ICs packages assembled by through silicon via (TSV) and microbump

interconnections have drawn world attentions on the scaling and function integrations of a

planar chip while Moore’s law is difficult to meet the future requirements of a higher speed,

multi-functionality, and the hetero-integrations among chips. The emerging technique of 3D

chip stacking using TSV enables higher integration density that allows greater numbers of

interconnections in order to fulfill the urgent requirements of dimensional downscaling and

electrical speed enhancement. However, 3D ICs packages have many critical issues regarding

reliability such as heat dissipation [1], fracture failure of microbumps under temperature/or

power cycling tests, interfacial delamination of underfill, cracking behaviors of stacking

silicon chips [2], electromigration, stressmigration [3]. Several structural designs have been

developed in the literature for improving the thermo-mechanical reliability of high-density

3D interconnections. For fine-pitch microbumps fabricated by using flip-chip bonding

technology, different Cu pillar bump types were studied to resist the fractured occurrence of

bonding interface between dissimilar materials [4]. In addition, another failure mode

regarding the delamination mechanism of advanced chips with Cu/low-k back end of line

interconnections was further investigated while the multi-temperature cycling loads induced

from fabricated processes of stacked thin films were taken into account [5]. As the both the

pitch and diameter among TSVs continues scaling down, a finite element analysis (FEA) is a

power tool to predict the stress response of various reliability tests. The layout arrangement

of high density TSVs on the assembly and related thermal cycling experiments have been

performed by FEA with an effective material model [6].

It has been known that underfill that surrounds the microbumps not only protects the

microstructures but also reduces the possibility of fatigue failure. However, when the gap

between stacking chips becomes narrower (<=20 µm), the traditional filling approach that

relies on the capillary actions becomes invalid. The wafer level underfill (WLUF) technology

combined with a thermal-compression process has been proposed to overcome the foregoing

assembly issue [7]. Compared with the traditional flip chip (FC) packaging, the proposed

vehicle of 3D ICs packaging is assembled using a thermal compression process instead of

reflow process. In addition, the interconnections of microbumps are significantly smaller than

the bumps in FC technology. To ensure the proposed WLUF is capable of properly filling at

the narrow gaps between stacking chips, the vehicle has been examined without TSV

structures. Meanwhile, a serious warpage induced from WLUF procedures is unfavorable to

the subsequent assembly of chip stacking. For this reason, the layout arrangements by means

of additional dummy bumps with considerations of major designed factors are optimized in

accordance with the capability limitations of packaging technology. Moreover, a design

guideline for the mechanical reliability of the 3D ICs packaging with WLUF and

microbumps is suggested in this paper.

2. Process Simulation of 3D ICs Packaging

A high-density pitch of microbumps associated with the WLUF under a thermal

compression process are utilized to prevent the thermo-mechanical failures of the

microbumps due to variations of thermal expansions of different materials in the 3D package.

However, the packaging structure significantly warps due to the mismatch of coefficients of

thermal expansions (CTE) between the WULF and the bonded material components. The

displacement of the packaging structure along the normal direction is utilized to represent the

warpage behavior of the structure. The increment of warpage leads to strain concentration

and higher probability of crack failure of the packaging structure. To investigate the warpage

behavior that is unfavorable for the subsequent assembly of chip stacking, two key design

factors, including the compressive force and the arrangement of outmost dummy joint, were

studied. To establish the structural optimization of 3D ICs packages combined the WLUF

and the assistance of dummy microbumps, the virtual prototype simulations based on two-

dimensional (2D) nonlinear FEA with a consideration of plane strain assumption was

implemented in this investigation. Using a process-oriented simulation technique, the FEA

estimated the distributions of warpage and stress/strain in the integrated packaging structures.

The process simulation of the 3D ICs packaging was compared with the experimental results.

2.1. Simulation Setup

In order to investigate the induced warpage in the multi-material packaging structure

purely resulted from the effect of WULF, as shown in Fig. 1, the chip-on-chip stacking

structure without TSV is regarded as the testing vehicle to examine the impacts during the

compression process. Unlike the conventional underfill and the no-flow underfill for flip chip

assembly [8], the WLUF has the advantages of avoiding the nucleation of micro-voids in the

underfill material that are detrimental to the microbump reliability [9]. However, the cooling

processing sequential to the thermal compression bonding (from 250°C to ambient

temperature) potentially incurs the warpage of the entire packaging structure of the thin-

silicon stacking method. To this end, the reduction of stress concentrations at the microbump

interconnections around the edges of the packaging structure as well as the preservations of

thin-layer uniformity in the integrations of TSV and microbumps have become one the of

most crucial tasks in the 3D ICs packaging. This paper proposed to use the dummy

microbumps and find the optimal magnitude of thermal compressions force for acceptable

thin-layer uniformity and the reliable mechanical performances of the entire packaging

structure.

Fig. 1 shows the FEA model of the investigated 3D ICs packaging with the WLUP

and the design of microbumps. The cutting direction of the analyzed area is shown in

Fig. 1 (a). Due to the geometric symmetry of the packaging structure, the cross-sectional area

of only half of the whole framework was constructed in 2D FEA, as in Fig. 1 (a). There are

totally 67 microbumps in the half model. The top chip was mounted on the bottom chip with

the interconnections of microbumps with lead-free solder materials. The subfigure (b) shows

the detail of the interconnection structure. The top and substrate silicon chips, designed in the

sizes of 5.1-by-5.1 and 16-by-16 millimeter squares respectively, were bonded together for

the reliability evaluations of a thin-chip-on-chip test. The Sn2.5Ag lead-free solder/Ni/Cu

microbumps were fabricated using the electroplating method and the subsequent reflow

process. The microbumps were patterned in a uniformly distributed array with a pitch of

30 µm for the foundations of the thin-chip stacking structure. The layers chosen for the under

bump metallization (UBM) were the 5-µm-thick Cu and 3.5-µm-thick Ni. The electrical

characteristics of the bonded daisy-chain chip with the metallic wires on the substrate were

exhaustively examined during the bonding process to evaluate the reliability performances.

The filled gap among the above-mentioned microbump array was too narrow for the

traditional underfill. The thermal-compression approach was utilized during the WLUF in the

assembly procedure. The process-simulated technique traced the stress variations and the

corresponding warpage during the complete WLUF process. The subfigure (c) shows the

detailed finite element meshes of a single microbump. The material properties utilized in the

FEA are listed in Table 1. It should be noted that WLUF usually has the mechanical

properties of a high CTE and a low modulus at an elevated temperature but introduces into a

modulus of several giga-pascals at the ambient temperature [6, 7, 10, 11]. Therefore, a

process-oriented simulation with an element inactivated/re-activated technique using a linear-

elastic modulus and a high CTE for the material property of the WLUF was sufficient to

represent the effective thermo-mechanical influence on microbumps. The temperature-

dependent stress/strain behavior of the solder material is shown in Fig. 2. The kinematic

hardening rule is utilized to describe the stress/strain behavior of solder material in 2D FEA.

2.2. Experimental and Numerical Results

2.2.1 Boundary and loading conditions of process-oriented FEA

Due to the periodic patterns of the microbump arrays, a two-dimensional (2D)

nonlinear FEA was used to model only the cross-section of the packaging structure passing

through the center axes of one microbump array during in the simulation of the WLUF

process. A half model associated with zero x-directional nodal displacements along the z-axis

was considered due to the symmetry about the z-axis, shown in Fig. 1 (a). Moreover, zero z-

directional nodal displacements were assigned at the bottom edge of the silicon substrate

since the packaging structure was mounted on a rigid ground. The cross-section of the

Cu/Ni/SnAg microbump and the corresponding meshed model in FEA are shown in Fig. 1 (b)

and (c) respectively.

At the beginning of the underfilling process, a stress-free environment was first

defined at an elevated temperature of 250°C while the WLUF remained at the liquid state.

Furthermore, the WLUF elements were inactivated so that no stress was induced to the whole

packaging structure. An external bonding force was then applied on the surface of top chip to

push the chip-side microbumps through the WLUF in order to assemble with the substrate-

side microbumps. A curing process at the same temperature solidified the WLUF forming a

stress impact on the microbump array while the structural warpage was induced accordingly.

The WLUF elements in FEA were re-activated during the curing process. Next, the bonding

force was removed and the entire packaging structure was cooled from 250°C to the ambient

temperature of 25°C. More severe stress and warpage were resulted from the mismatch of

between each material during the cooling process.

The thermo-mechanical stress/strain behavior of microbumps in the proposed 3D ICs

packaging structure was studied. The warpage contour of a chip-on-chip stacking package for

the 50-µm top chip with a 2-kg bonding load is shown in Fig. 3 (a). Observed from the center

of the packaging structure, the maximum warpage (blue colored) occurred at the outermost

surface corner of the top chip. The serious induced warpage occurred because the top chip

was not supported underneath at the outer region of the package. Since the distribution of von

Mises strain has commonly been utilized as the failure criterion of ductile metal, it was

expected that failure occurred at the location of maximum von Mises strain in the FEA, that

is, the interfacial region between inter-metallic compound (IMC) and lead-free solder shown

in Fig. 3 (b).

2.2.2 Experimental measurements

The experiment using a thin top chip of 50 µm was employed to observe the maximum

induced warpage during the WLUF process. Fig. 4 shows the Scanning Electron Microscope

(SEM) images of the testing vehicle. An IMC layer has been formed between the Ni layer

and the SnAg solder, shown in Fig. 4 (b), after the assembly between the chip-side and

substrate-side microbumps during the WULF process. The edge of the top silicon chip was

less supported due to the layout design of microbump arrays, shown in Fig. 4 (b); therefore,

the resultant gap distance between the top chip and the substrate at the center of the

microbump array was larger than the one at the edge of the microbump array. It was expected

that the maximum warpage be found at the edge of the microbump array.

The shrinkage of top Si chip during the cooling step was negligible because of a

relatively lower CTE, i.e. 3 ppm/°C. Therefore, the maximum warpage equals the decrement

of the gap distance between the top chip and the substrate at the edge of the microbump array,

which was confirmed by the SEM images of the microbump arrays at the center and edge

regions, shown in Fig. 5 (a) and (b) respectively. Under the bonding force of 2.0 kg, the

former gap distance equals 21.5 µm while the later one equals 19.3 µm. Due to the

assumption of plane strain analysis, it is expected that the predicted result in 2D FEA, i.e.

1.861 µm in Fig. 3 (a), is smaller than the experimental result, which equals to

21.5−19.3= 2.2µm . Moreover, a comparison of gap distances under various bonding forces

was shown in Table 2. The experimental results showed the maximum warpage was found at

the edges of the microbump array. Due to the misalignment of microbumps during the

thermal compression process for WLUF, the gap distances at the both ends of the microbump

array were different, as shown in Table 2. Therefore, the magnitudes of warpage were

different at both ends. It is expected that larger bonding force would induce greater warpage.

However, the monotonic behavior between warpage and bonding force was only found and

confirmed in the conditions of bonding force greater than 1.0 kg because the misalignment in

the experiment under 1.0-kg bonding force was too severe. The SEM image in Fig. 6 further

indicated the occurrence of the fracture at the interface of the SnAg solder and the IMC layer

in the microbump at the edge region of the packaging structure. This finding confirmed that

failure would occur at the location of maximum von Mises strain in the FEA, shown in

Fig. 3 (b). The failure mode at the interface of the SnAg solder and the IMC layer was also

attributed to the brittleness of the IMC layer. Therefore, it is desirable to find the better

design variables to prevent the formation of warpage and to reduce the probability of the

occurrence of interfacial cracks. The later processes of parametric modeling and guidance for

reliable designs would focus on the investigation of maximum von Mises strain at the

interfacial region of IMC and solder in the outermost microbump.

On the other hand, the proposed process-oriented FEA was used to predict the warpage

magnitude of 3D ICs packaging with WLUF with respect to various thicknesses of the top

chip. The simulated results based on 2.0-kg bonding forces, shown in Fig. 7, indicated the

warpage at the edge of the top chip was larger than the one at the center of the top chip. It is

noted that severe warpage occurred at the edge of the top chip as the thickness of the top chip

was thinner than 100 µm. The chip-edge warpage for the 50-µm-thick top chip was about

1.84 µm, which has the same trend as compared with the experimental results in Table 2, i.e.

around 2.0 µm. Furthermore, a maximum plastic strain at the interface of the SnAg solder and

the IMC layer, as shown in Fig. 3, confirmed the occurrence of the crack failure. In this paper,

we are to determine the better design variables to reduce the probability of the occurrence of

crack failures at the interface of the SnAg solder and the IMC layer. That is to say, it is

desirable to find the feasible design space of the allowable levels of maximum strain and

warpage in the packaging structure.

To improve the warpage induced from the WLUF process, an array of dummy

microbumps is arranged nearby the critical microbump at various designed distances, denoted

by D: 30, 60, 90 and 120 µm. It is noted that D 0= represents zero dummy microbumps. The

layout designs of the dummy microbumps, shown in Fig. 8, were expected to release the

stress/strain exerted in the critical microbumps. In the next section, the responses of the

simulation results are parametrically model with respect to three key design variables to

provide new guidelines for reliable designs of the 3D ICs packaging with WLUF and dummy

microbumps.

3. Parametric Models and Design Guidance for 3D ICs Packaging with WLUF

To parametrically model the warpage and stress/strain behaviors, 125 uniformly

distributed sampling design points were chosen in the design space. The design variables

include the thickness of the top chip, the required bonding force for the thermal compression

process, and the location of dummy microbump arrays. The strain distribution of the entire

packaging assembly may vary dramatically with respect to the chosen design variables

because the thickness of the top chip and the location of dummy microbumps vary the

geometry of the structure. In order to accurately model the nonlinear behaviors between the

responses and the design variables, the Kriging response surface model [12] is utilized.

Kriging is composed of multiple kernel functions that model the covariance between the

design point and the sampling points. In this paper, the radial basis kernel function [13] is

chosen.

3.1. Kriging Response Surfaces

Kriging is a general method to predict the responses from experimental and

simulation data in terms of minimizing the variation of the estimation error [14]. The general

format is given as follows:

F x( ) =wTCx x,xS( ) (1)

where w is the weighting coefficient to be determined and Cx is a M-by-1 covariance vector.

M is the number of the sampling points; in our study, M =125 . When the radial basis

function is chosen, the jth component of Cx is the Euclidean distance between the design

point x and the jth sampling point x jS , as in

Cx, j x - x jS( ) = x - x jS (2)

Given the experimental and simulation data points, a covariance matrix C is obtained where

Ci, j = xiS - x j

S . Accordingly, the weighting coefficients are determined by

w =C-1 xS( )FS xS( ) (3)

where FS is the vector of the responses at the sampling points.

We have analytically confirmed that the minimal top-chip thickness was 50 µm to

avoid the collapse of thin-silicon chip at the outermost region (i.e. gap between chips larger

than 2 µm). For the response modeling of the warpage and strain behaviors, the chosen

design space is therefore spanned by the thickness of the top chip in the interval of [50,

230] µm, the required bonding force in the interval of [1, 5] kg, and the location of dummy

microbumps (denoted by D) in the interval of [0, 4] pitches. The length of the microbump

pitch is 30 µm; therefore, D can be 0, 30, 60, 90, or 120 µm. The sampling points are

uniformly chosen from the design space. The information of the sampling points is listed in

Table 3. Each dimension is normalized to avoid the scaling issue among each design variable.

Using the Kriging model with the radial basis functions, the warpage and strain

(denoted by ε ) responses have been formulated with respect to the three design variables, as

in Fig. 9 (a) and (b) respectively. The color maps represent the quantitative levels of the

three-dimensional contours. The Kriging model is capable of revealing the nonlinear

behaviors of the responses with respect to the design variables. As a result, the maximal

warpage and strain occur at the conditions of highest bonding force and smallest chip

thickness without the use of dummy microbumps while the use of dummy microbumps not

only reduces the warpage but also dramatically decreases the strain at the bonding interfaces.

3.2. Kriging-based Design Guidance (KDG)

Various design requirements have different levels of allowable warpage and strain of

the 3D ICs packaging with WLUF after the thermal compressions process. From the Kriging

response surface models, the design guidance for various upper bounds of warpage and strain

are shown in Fig. 10 (a) and (b) respectively. The potential failure regions are shown under

the hatched area while the solid curves serve as the Kriging-based Design Guidance (KDG)

for the performance limit states of the allowable 3D ICs packaging designs. The feasible

design space is smaller when the dummy microbumps are not used, that is, the warpage may

exceed the allowable limit for thinner top chip and larger compression force. For the finest

chip thickness = 50 µm, the use of dummy microbumps at D = 120 µm as well as the minimal

bonding force led to warpage less than or equal to 1 µm. For higher allowance of warpage,

larger compression force can be used.

The behavior of strain is different from the warpage. The Fig. 10 (b) shows the KDG

of various allowable levels of strain without the use of dummy microbumps. Thinner top chip

and larger compression force increase the strain at the critical microbump. The use of dummy

microbumps effectively releases the strain at the critical microbumps. All the designs have

strain less than 1.75% when D >= 30 µm. The deterministic design guidance will help the

designer and manufacturing control the key design parameters, including the bonding force

and top chip thickness, wisely. Furthermore, the KDG can be used in the deterministic design

optimization of the 3D ICs packaging.

4. Reliability-Based Design Guidance for 3D ICs Packaging with WLUF

In design optimization, the optimal design points are often found at the limit states of

the performance constraints. The designer of 3D ICs packaging can use the KDG, which is

previously introduced in the section 3.2, as the deterministic constraint functions during the

optimization processes. However, the probability of the optimal design point near the

boundary of KDG satisfies the performance constraints may be less than 50% if the design

uncertainty is not negligible. In this section, a Reliability-Based Design Guidance (RBDG) is

proposed to enhance the reliability of the design of 3D ICs packaging.

4.1. Reliability Analysis

In design optimization under uncertainty, the following probabilistic constraint is

often formulated:

( )[ 0]> <= fP g PX (4)

or

( )[ 0] 1-<= > fP g PX (5)

where g is the deterministic constraint function; X is the randomly distributed design

variable; fP is the allowable failure probability. Suppose 0<=g represent the deterministic

performance requirement, Eq. (4) states the failure probability must be less than or equal to

the allowable probability. Due to the uncertainty in X , the performance function ( )g X is

also randomly distributed. The evaluation of the failure probability in Eq. (4) can be

completed by the integration of joint probability density function in the infeasible space.

However, the integration process requires extremely large number of function evaluations.

The reliability index B [15] is utilized to represent the safety level of the design point, as in

( ) ( )* * *B ( )= ∇ ∇T g gu uu u u (6)

where *u is the most probable failure point in the standard normal u -space. In this paper, the

required reliability level is defined by B B 3>= =f , also known as the three-sigma design.

The allowable reliability is 99.87%.

4.2. Reliability-Based Design Guidance (RBDG)

Lin et al. [16] demonstrated a systematic strategy to design under uncertainty. The

deterministic performance functions are first formulated using the Kriging response surface

models in Eq. (1) associated with the performance upper limits chosen to meet the design

requirement. A coordinate shifting is then applied to the Kriging model in terms of the

reliability index to formulate the function RF of the RBDG:

( ) ( )( )B ,= ⋅ + SR x fF CX Xw xµ µ σ (7)

where B f is the required reliability index and σ is the standard deviation of the randomly

distributed design variable. In the design of the 3D ICs packaging, the uncertainty of the

compression force is inevitable. Suppose the standard deviation of the bonding force is

0.4 kg, the RBDG of allowable warpage and strain, shown in Fig. 11, are obtained to serve as

the new reliability standard for high-throughput production of 3D ICs packaging.

The Fig. 11 (a) shows the coordinate-shifted curves of the design guidance for

warpage behavior under the given reliability information, while the subfigure (b) shows the

RBDG for the strain behavior. A numerical Monte Carlo simulation process (sampling size =

610 ) has confirmed the reliability of the design points in the design space. The feasible

design spaces with allowable reliability become narrower due to the coordinate shift. The

tradeoff between the performance and the reliability is expected. In practical manufacturing

of 3D ICs packaging, the higher-reliability lower-performance production is often more

important than the higher-performance lower-reliability one. Therefore, the RBDG can be

utilized to enhance the mechanical reliability of the 3D ICs packaging with WLUF under

design uncertainty.

4. Conclusions

The design of 3D ICs packaging with WLUF under the thermal compression process

has been studied experimentally and numerically. The thermo-mechanical failures may occur

at the microbump structure due to the variations of thermal expansions of different materials.

The stress/strain behaviors of the entire chip-on-chip assembly have been investigated using

the FEA with the process-oriented simulation technique. The comparison of the experiment

results with the 50-µm-thick top chip with the simulation data has been made and the same

trends of physical behaviors were found. The warpage and strain at the most critical

microbumps varied with respect to two key design parameters: thickness of the top chip and

the bonding force. The responses were parametrically modeled using the Kriging method.

The parametric models showed top chip thickness of 50 µm led to server warpage formation.

The design of dummy microbumps were arranged near the critical microbumps to improve

the mechanical performance of the assembly structure. The simulation results showed the use

of dummy microbumps at the position of 120 µm away from the critical microbump

decreased the warpage level of the 50-µm-thick design down to 1 µm. However, the design

points at the deterministic design guidance lead to more than 50% of probability of failure.

Reliability-Based Design Guidance has been defined to perform the coordinate shifting to

deliver safety buffers between the design points and the deterministic limit states. The Monte

Carlo simulations confirmed the reliability levels of the design points. The proposed method

not only can be used as the design guideline for the mechanical reliability of the 3D ICs

packaging with WLUF and dummy microbumps but also can be applied to the

multidisciplinary design optimization processes [17, 18] in the microelectronic packaging.

The reliability-based design guidance provides the designers and engineers in the

semiconductor industry more insightful knowledge about the probabilistic feasible design

spaces of the complex design problems where multiple disciplines or physics can be

involved.

Acknowledgements

The authors would like to thank the National Center for High-performance

Computing (NCHC) for supporting this research, as well as the National Science Council

(NSC) of Taiwan, R.O.C. for providing financial support under the grants NSC-100-2218-E-

033-002-MY2 and 102-2221-E-033-020. Likewise, the fabricating support of the specimens

from Electronics and Optoelectronics Research Lab (EORL), Industrial Technology Research

Institute (ITRI), Taiwan is deeply appreciated by the authors. Furthermore, the supports and

suggestions from Kuo-Shu Kao, Ren-Shin Cheng, Chau-Jie Zhan, John H. Lau, and Tao-Chih

Chang at Assembly and Reliability Technology Department, ITRI, Taiwan are greatly

appreciated.

References

[1] J.H. Lau, T.G. Yue, Microelectronics Reliability 52 (2012) 2660-2669.

[2] C. Wu, M. Hsieh, K. Chiang, Microelectronic engineering 87 (2010) 505-509.

[3] K. Tu, Microelectronics Reliability 51 (2011) 517-523.

[4] S. Park, H. Bang, H. Bang, Microelectronic engineering 99 (2012) 38-42.

[5] C. Chiu, C. Huang, S. Yang, C. Lee, K. Chiang, Microelectronic engineering 87

(2010) 496-500.

[6] C.C. Lee, T.F. Yang, C.S. Wu, K.S. Kao, C.W. Fang, C.J. Zhan, J.H. Lau, T.H. Chen,

Microelectronic Engineering 107 (2013) 107-113.

[7] C.-C. Lee, T.-F. Yang, K.-S. Kao, R.-C. Cheng, C.-J. Zhan, T.-H. Chen, IEEE

Transactions on Components, Packaging, and Manufacturing Technology 2 (2012)

1412-1419.

[8] S. Lee, Ph.D. Dissertation at George W. Woodruff School of Mechanical

Engineering, Georgia Institute of Technology (2009).

[9] A. Taluy, S. Lhostis, A. Jouve, G. Garnier, E. Dezandre, A. Farcy, S. Cheramy, N.

Sillon, A. Sylvestre, in: Electronics Packaging Technology Conference (EPTC), 2011

IEEE 13th (2011) 129-134.

[10] Y.C. Chan, M.O. Alam, K.C. Hung, H. Lu, C. Bailey, Journal of Electronic

Packaging 126 (2004) 541-545.

[11] S. Lee, M.J. Yim, R.N. Master, C. Wong, D.F. Baldwin, IEEE Transactions on

Electronics Packaging Manufacturing 31 (2008) 297-305.

[12] P.T. Lin, Ph.D. Dissertation at Mechanical and Aerospace Engineering, Rutgers

University (2010).

[13] P.T. Lin, Y. Jaluria, H.C. Gea, Journal of Manufacturing Science and Engineering

131 (2009) 011011.

[14] L. Lebensztajn, C.A.R. Marretto, M.C. Costa, J.-L. Coulomb, IEEE Transaction on

Magnetics 40 (2004) 1196-1199.

[15] P.T. Lin, H.C. Gea, Y. Jaluria, Journal of Mechanical Design 133 (2011) 044501.

[16] P.T. Lin, H.C. Gea, Y. Jaluria, Frontiers in Heat and Mass Transfer 1 (2010) 013003.

[17] P.T. Lin, H.C. Gea, Structural and Multidisciplinary Optimization 47 (2013) 715-733.

[18] P.T. Lin, H.C. Gea, Journal of Mechanical Design 135 (2013) 021001.

Table 1. A list of material properties used in the stress simulations of 3D ICs package [7]

Materials Young’s Modulus Coefficient of Thermal

Expansion (ppm/°C) Poisson’s Ratio

Si 169.5 GPa 3 0.28

Cu

E = 122 GPa

Ref. T = 25°C

Yield stress = 173 MPa

Tensile strength = 1.2 GPa

17 0.35

Passivation

(Si3N4) 155 GPa 5 0.28

Wafer-level

underfill 6.8 GPa @ 25°C 53 0.33

SnAg solder Temperature-dependent

(shown in Fig. 2) 22.5 0.4

IMC

(Ni3Sn4) 85.6 GPa

16.3 @ -40°C

17.6 @ 25°C

18.1 @ 50°C

19.3 @ 125°C

0.31

Ni 186 GPa 12.5 0.342

Al 72 GPa 24 0.36

Table 2. Measurements of the gap distances between top thin chip and silicon substrate at

different locations under various bonding forces

Bonding

force

(kg)

Gap distance

at the left

edge (µm)

Gap distance

at the center

(µm)

Gap distance

at the right

edge (µm)

Warpage difference

due to

misalignment (µm)

Averaged

warpage

(µm)

1.0 20.8 22.6 19.8 1 2.3

1.5 21.8 22.5 21.3 0.5 0.95

2.0 19.5 21.5 19.2 0.3 2.15

2.5 18.8 22.4 19.1 0.3 3.45

Table 3. Various levels of the design variables

Design variables Five different levels of sampling points

1 2 3 4 5

Top chip thickness (µm) 50 80 120 170 230

Bonding force (kg) 1 2 3 4 5

D (µm) 0 30 60 90 120

(a)

(b)

(c)

Fig. 1. Simulation models of 3D ICs packaging using WLUF and microbumps. (a) 2D FEA at

the specified cutting line; (b) Cu/Ni/SnAg microbumps; (c) meshed model of a microbump.

Fig. 2. Temperature-dependent stress/strain curve of solder material [7].

(a)

(b)

Fig. 3. Numerical results: (a) distribution of warpage (millimeter) in the packaging after the

thermal compression process; (b) distribution of von Mises strain in the microbumps at the

corner region of the die.

(a) (b)

Fig. 4. SEM images of microbump assembly: (a) assembly with WLUF; (b) cross-section of

the SnAg interconnection.

(a) (b)

Fig. 5. Gap distance between the top chip and the substrate at (a) the center and (b) the edge

regions of microbump array after a 2.0-kg bonding process.

Fig. 6. A failure mode of microbump assembly with WLUF after a thermal-compression

procedure.

Fig. 7. Warpage estimations of FEA for the center and edge regions of a packaging structure

under a loading of 2.0 kg bonding force.

Fig. 8. Layout designs of the dummy microbumps at the distances of (a) 30, (b) 60, (c) 90 µm

from the critical microbumps.

(a)

(b)

Fig. 9. 3D contours of response surfaces of (a) warpage and (b) strain with respect to the

design variables.

(a)

(b)

Fig. 10. Deterministic design guidance in various levels of allowable (a) warpage and (b)

strain (D=0).

(a)

(b)

Fig. 11. Probabilistic design guidance in various levels of allowable (a) warpage and (b)

strain (D=0).