Applied Surface Science 48/49 (1991) 377-386 377 North-Holland

Si-Ge alloys: growth, properties and applications

Maur i z io Ar ienzo , S u b r a m a n i a n S. Iyer, Berna rd S. Meye r son , G a r y L. Pa t ton and J o h a n n e s M.C. S tork IBM Research Division. T.J. Watson Research Center, Yorktown Heights. N Y 10598. USA

Received 14 August 1990; accepted for publication 20 August 1990

Due to advances in epitaxial techniques, the ability to deposit high-quality epitaxial silicon-germanium alloys at lower temperature, has opened up the applications of pseudomorphic Si~_ ~G¢, films in advanced bipolar transistors and in novel device structures. In this review paper, the various methods of growth of Si-Ge alloys are discussed, including low-temperature epitaxy by ultra-high vacuum chemical vapor deposition (UHV/CVD) and molecular beam epitaxy (MBE). Tile morphology of growth and the stability of the deposited films are then presented. The major application of Si-Ge alloys in integrated processes has been in the bipolar transistors area. The appli :.qtion of these alloys to the bandgap engineering of bipolar devices is discussed, including the most recent accomplishment of 75 GHz fT heterojunction bipolar transistors using Si-Ge in the base.

I. Introduction

The knowledge and the ability to control key material characteristics have been essential in the development of silicon technology and will con- tinue to influence strongly its future directions. One of the foremost examples in the last few years is the progress in the area of s i l icon-germanium alloys. Once a research laboratory curiosity, the use of these alloys has quickly become a high leverage item incorporated in a number of ad- vanced devices, thanks to the tight coupling be- tween the material science and the device needs. The leverage is provided by the ability to build heterostructures and bandgap-engineered devices, until recently exploited only in compound semi- conductor systems, in the silicon system. The good quality material, necessary for manufacturability, has been provided by advances in epitaxial tech- niques. Although other materials have been used to form heterojunctions with silicon, like SiC and microcrystalline Si, both hydrogenated, oxygenat- ed or nitrogenated, the narrow-gap S i - G e alloys are by far the most exciting and the further devel- oped.

Silicon and germanium are completely miscible

over the entire compositional range and give rise to alloys with the diamond crystal structure. The lattice mismatch between Ge and Si is 4.17% at room temperature and increases only slightly with temperature. Due to the lattice mismatch, two types of epitaxiai growth are possible on a bulk substrate: pseudomorphic, or strained; and re- laxed, or dislocated. Fig. 1 illustrates the occur- rance of pseudomorphic growth when the strain due to the lattice mismatch is accommodated at or near the interface by tetragonal strain, rather than being relaxed by the formation of misfit disloca- tions. The interest in pseudomorphic growth is not only due to the lack of interracial dislocations which could give rise to interface states, band discontinuities, and unwanted electrical effects, but also to the fact that the presence of tetragonal strain in the alloy produces a further reduction in the baadgaps, with respect to the bulk alloy layer, due to the splitting of degenerate valence and conduction bands [1]. Fig. 2 shows the energy gap value as a function of Ge content. The top solid curve shows the bandgap for a bulk alloy layer due to Braunstein et al. [2]. The growth of pseudo- morphic Si t _xGex on Si substrates causes an even greater shrinkage of the indirect gap as shown in

0169-4332/91/$03.50 5", 1991 - Elsevier Science Publishers B.V. (North-Holland)

378 M. A rienzo et al. / Si-Ge alloy" growth, properties and applications

I I I I

Epitaxlal SiGe

+ I I I I I I I I I I I I I I I I I I I I

Substrate Si

I m

I I I I I I I I I I I I I I I I I i / _ l l I _ \ I I I I I I I I I I I I i i i I I I I I I I I I I I I I I I I !!!!I I I Ill

Unstrained

I I I l I l I I I I I I I I I I I I I I i l l l l l I I f I iiiii111 II!iiiiiii Iiiiliiiii

Strained (Pseudomorphie) Fig. l. Two-dimensional representation of pseudomorphic growth. An unstrained Sij _,Ge~ film is deposited on a silicon substrate. Depending on growth parameters, the growth could be pseudomorphic, with the lattice constant difference accom- modated by tetragonal strain or it could be dislocated and

unstrained•

the lower two curves of fig. 2, where most of this bandgap difference is present in the valence band. As it can be observed, the amount of bandgap narrowing in the grown film can be on the order of 100 meV for Ge contents of less than 10%. Therefore, a number of interesting bandgap-en- gineered devices can be built in silicon technology with small amounts of germanium.

In this review paper, after a review in section 2

1.2 i i " " l i i i i i i

I.O lay

"....'-'-., \ 0.8 S t ra in -Sp l i t V . B . ~ ~ ' ~ . Lo.e, \

~ Band

~ . Upper Band

0.6 I I I I I I I I I 0.2 0.4 0.6 0.8 1.0

Gormon lum Fraction

Fig. 2. Band gaps for unstrained bulk Si t _ ,Ge, alloys [ 2] and pseudomorphic Si 1 _. ,Ge, alloys. Both the strain-split light and heavy hole bands [53] are shown along with the experimental

optical absorption data [54].

of the various S i - G e alloy growth methods em- ployed in our laboratories, including low-tempera- ture epitaxy by ultra-high vacuum chemical vapor deposition ( U H V / C V D ) and molecular beam epi- taxy (MBE), the morphology of growth and the stability of the deposited films are discussed in section 3. The application of these alloys to the bandgap engineering of advanced devices, and in particular to bipolar devices is discussed in section 4, including the most recent accomplishment of 75 G H z fx heterojunction bipolar transistors using S i - G e in the base. Section 5 will conclude this paper.

2. Growth of S i / S i - G e structures

Device-quality S i - G e layer growth necessitates both a low-temperature growth method to mini- mize islanding and strain relaxation by dislocation nucleation and an oxygen-free surface passivation method to reduce the oxygen incorporated at the interface causing crystalline defects and degrada- tion of the electrical characteristics. Low-tempera- ture epitaxial growth techniques such as molecular beam epitaxy (MBE) [3] and low-temperature epi- taxy by chemical vapor deposition [4-6] are essen- tial for the growth of metastable alloys and for the preservation of sharp doping profiles. For these epitaxial growth methods to succeed, an atomi- cally clean starting surface is mandatory and, fur- thermore, the same level of atomic cleanliness must be preserved during growth.

In this article we will discuss the two tech- niques that we have used for S i - G e film growth: ultra-high vacuum chemical vapor deposition ( U H V / C V D ) and molecular beam epitaxy (MBE). Another method used in the literature, limited-re- action processing (LRP) [5], will not be covered in this paper.

2.I. U H V / C V D

U H V / C V D [4,7,8] is a growth method per- formed at a temperature of approximately 550 o C. A U H V / C V D system is shown schematically in fig. 3: a batch of 125 mm diameter wafers are placed within a load-lock, and transferred under

M. Arienzo et aL / Si-Ge alloys: growth, properties and applwatitms 3 7 9

clean conditions into the main growth chamber, a hot-walled isothermal furnace. Gaseous sources, like silane, germane, diborane, and phosphine, un- dergo heterogeneous pyrolysis and epitaxial films are grown at a temperature in the range 425- 650°C.

As already mentioned, the successful initiation of film growth relies upon the preparation and maintenance of an atomically bare Si surface on which neither contamination nor defect nucleation can occur. Conventional silicon epitaxy by CVD addresses both issues by brute force, employing high temperatures (T > 1000 o C) to volatilize any oxide present on the initial growth interface, while deposition itself is at temperatures in the range of 850-1000°C. In UHV/CVD, the growth is per- formed at a much lower temperature, 550 o C, and the preparation of the surface is accomplished chemically by the creation of a passivating layer of hydrogen bound to silicon. Samples are subjected to a standard clean, followed by a diluted hydro- fluoric 10:1 H 2 0 : H F dip. An air-stable hydro- gen-passivated surface [9] is thus obtained, pre- serving the initial growth interface and allowing the growth tc proceed without recontamination by oxides or carbon. It is to this objective [10] that the base pressure of the UHV/CVD system at idle is kept in the range of 10 -9 Torr, and the partial pressures of the oxidants 02 and H20 are maintained below those required to form the sta- ble SiO 2 phase, as it can be quantitatively de- ducted from refs. [11,12[. Under typical operating conditions, the partial pressures of oxygen and water are maintained at or below 10-=0 Torr, and the gases employed for film growth are free of oxygen and water to below the 1 ppm level.

UHV/LOAO CHAMBER MASS .SPEC GAS

FURNACE ~

. . . . . . . . . ]'1 !ll vA . A~o dill, , ROOTS B.OWER ' ~ TRC~;F E R ) I I lU , • - - APPAR&TUS

. . . . . . . . . . . TURBO PUMP

A1203 TRAP

ROTARY PUMP

Fig. 3. UHV/CVD system schematic [4].

1 0 1 l ' i ' i ' l ' , 1 0

Emi t t e r Rose Co l l ec to r 8

c 1 0 2 0 ~

= 6 o

d

1 0 1 6 , I , I £ , : U , I ,

t00 200 300 400 500 0epth ( nm)

Fig. 4. SIMS profile of a completed Si-Ge-hase device. A base width of 45 nm was achieved [45}.

The films grown by this technique have very abrupt transitions in both alloy composition and doping, since UHV/CVD operates under condi- tions of molecular flow, with very short gas resi- dence times (several milliseconds). This has been demonstrated by a two-dimensional hole gas (2DHG) formed at a S i /S i -Ge heterojunction to probe the abruptness of doping and compositional transitions [13,14]. The films can be grown in-situ doped, with active supersaturated amounts of dopant with high dynamic range, and do not require subsequent annealing steps to either activate the dopant or to remove the damage, as it is in the case of ion-implanted layers. Because of all of the above, junction depths are determined by the deposition thickness, and not by the dif- ference between two dopant froiits that diffuse during thermal annealing. An example of the over- all flexibility of this process is seen in fig. 4. It shows the secondary ion mass spectroscopy (SIMS) profi!e of a Si-Ge heterojunction bipolar tran- sistor. The entire profile consists of less than 100 nm of material deposited and, as long as the subsequent processing time-temperature cycles can be kept to a minimum, these as-grown com- plex junctions can be used to make record perfor- mance bipolar transistors as we will show in sec- tion 4.

2.2. Molecular beam epitaxy

As opposed to CVD, MBE is a physical vapor deposition method, or PVD. The growth, m fact,

380 M. Arienzo et al. / Si-Ge allo)~: growth, properties and applications

is accomplished by the direct impingement of ele- mental species on a heated substrate under ultra- high vacuum (UHV) conditions [15]. To first order, the growth rzte and film composition are de- termined only by the impinging species and are independent of substrate orientation and tempera- ture. Doping is carried out by the co-incorpora- lion of dopant species during epitaxy. A common approach is to use thermally generated elemental dopant beams. Due to vapor pressure considera- lions, the choice of dopants is limited to Ga and Sb for P- and N-type dopants, respectively. More recently, a variety of methods to incorporate B have been developed [16-19]. Although the tech- nology for elemental B incorporation is complex, the actual incorporation proceeds simply and di- rectly from the flux and in most cases is indepen- dent of substrate temperature. Direct ion implan- tation of dopant species at sub-kilovoh energies is practiced by some workers [20-22]. While prop- erly designed direct implantation methods are ca- pable of high uniformity and reproducibility, the technology is quite complex, since low-energy ( < 1 keV) beams at high currents (100 mA) are re- quired for high dc~ping levels. The effect of radia- tion damage enhanced diffusion needs to be ad- dressed as well.

Conventional cleaning in MBE involves the growth of a non-stoichiometric chemical oxide and its in-situ desorption at = 850 °C. More re- cently [23] i, has been demonstrated that HF treatment of Si is effective also in MBE, provided that the epitaxial process is commenced on the hydrogen-passivated surface left after the HF treatment. This passivation, indicated by a 1 × 1 pattern in the low-energy electron diffraction (LEED) patterns, is inert for several minutes -.-. air, and several days in UHV at room temperature [24]. The passivation is lost if the wafer is heat- treated in UHV above 400°C, resulting in the reconstruction of the surface to an unpassivated 2 x 1. To grow on the passivated surface, lower temperature growth, at least during the initial growth stages, is necessary in MBE in order to supply enough Si flux to keep exposing a fresh Si surface while the hydrogen passivation is being lost. As discussed previously, in the case of UHV/CVD growth using hydrides, the passiva-

lion is replenished in the course of the dissociative absorption of the hydride, and growth proceeds on an 1 x 1-terminated surface [23].

3. Properties of pseudomorphic Si-Ge layers

3.1. Crit ical th ickness

The maximum thickness for pseudomorphic growth ("critical thickness") of Si~_,Ge, alloys is simply defined as the thickness at which strain relaxation occurs due to the onset of dislocations. This quantity is clearly a function of the germanium fraction, and it is an important param- eter for device designers, since it is necessary to prevent strain relaxation and for dislocation gen- eration to occur. There have been many defini- tions of critical thickness, either theoretical or empirical, as summarized in ref. [25]. In some of the theoretical work, one difficulty has been to find good numerical values for the many parame- ters involved; another has been oversimplification. In the experimental observations, the onset of strain relaxation is limited by the experimental technique used. Conventional X-ray diffraction [26], transmission electron microscopy [27] and Raman spectroscopy [28] can detect relaxation only when it exceeds 0.1%. If the strain relaxation is via dislocation formation, the electrical effects may be felt long before the relaxation is de- termined by structural methods, and we have routinely used the measurement of the reverse leakage across appropriate p - n heterojunctions, the ideality of the forward injection, and measure- ment of band discontinuities to assess the quality o r the interface. One of the complications is that the electrical activity of the dislocations is not well understood, and it is very dependent on the inter- action with impurities (from the process itself or from subsequent processing). Therefore, while we cannot quantitatively correlate the electrical mea- surements to relaxation, they serve as a very sensi- tive measure of the heterojunction quality. These electrical measurements indicate that excellent junctions are attainable in our laboratories. Our experience suggests that proper substrate prepara- tion, the use of buffer layers, and particulate con-

M. Arienzo et aL / Si-Ge alloys: growth, properties attd applications 381

tamination during growth all play a key role in dislocation formation, and may be more im- portant than the energy and mechanical equi- librium theories would suggest, at least for the growth of low ( _< 25%) Ge content films on Si(100) substrates.

The critical thickness as defined either by the- ory or by experiments is summarized in fig. 5 for Sil_,Ge ~ grown on Si(100) as a function of x. Note that different workers have used different substrate preparation techniques, growth tempera- tures and growth rates, and different measurement criteria to determine critical thickness. Also shown in fig. 5 are points of composition and thickness, at which Sil_.~Ge~ base heterojunction bipolar transistors have been fabricated.

In the case of pseudomorphic III-V layers, it is generally accepted that relaxation is sudden and almost complete once the critical thickness is ex- ceeded. However, in the case of covalent alloy semiconductors such as Si-Ge, the onset of re- laxation is gradual, and film thickness much greater than the critical thickness may be required before significant relaxation occurs, as suggested by Fiory et al. [29]. Also, as complex Ge profiles

I~,m i

IOOnm

-~ 10nm

t3

lnm

t 2 3 Misfit(~)

~ ' ~ Peoal'e-Beon Theory

• Bean et al. ".Oo'~b~ "MBE • Kohama et al.

i ~ "• ~ • Kingetal. c o.

LRP " ~ . . ~ i n e d

Slroined (Pseudomorphle)

I I I I I I I I 0.2 0.4 0.6 0.8 1.0

Germanium Fraction

Fig. 5. Crit ical thickness p lo t ted as a func t ion of G e con ten t . Shown are the emperical curve of People and Bean [55] and their exper imenta l poin ts ob ta ined f rom channe l ing and T E M : EBIC de te rmined points of K o h a m a et al. [56]: and , po in t s de te rmined f rom b a n d g a p measu remen t s f rom H B T ' s due to K ing and co-workers [57]. Also shown are some representa t ive compos i t ions and thicknesses used in H B T fabr ica t ion . The

L R P point is discussed in ref. [5].

are grown, like triangular or trapezoidal, with the Ge percentage varying during the growth, the onset of relaxation will become profile-dependent.

Extensive transmission electron microscopy (TEM) studies, both planar and cross-section, have been performed on the Si and Si-Ge samples grown by UHV/CVD and MBE. In fig. 6 we show the cross-sectional TEM pictures of a tran- sistor grown by UHV/CVD with a vertical profile similar to that in fig. 4. A high-resolution view of the Si -Ge/Si interface clearly shows the good epitaxial quality of the Si-Ge film, and shows the lack of any feature at the interface.

3.2. Thermal relaxation

After the material is grown, subsequent processing will be necessary to complete the de- vice formation. The metastable nature of pseudo- morphic Si-Ge layers places several restrictions on the way this material may be processed. During thermal annealing, the layers may relax. The mode of relaxation may be either via intermixing or via additional misfit dislocation formation. Work by Legoues et al. [30] shows that the initial condition of the interface plays a crucial role in determining which relaxation mechanism will dominate.

From a device perspective, a single threading dislocation through the active area of the device will have little electrical effect. However, the threading component can act as a diffusion "pipe" leading to enhanced impurity diffusion and conse- quent junction leakage. Clearly, limiting processing temperatures will minimize this effect. On the other hand, the edge component of the dislocation that lies in the depletion region is potentially a high density of recombination centers which would contribute to junction leakage, particularly when decorated with metallic impurities.

In fig. 7, the forward and reverse base-emitter characteristics of Si-Ge-base devices grown by UHV/CVD are shown. As it can be observed, consistent with the TEM observations of material quality, excellent electrical characteristics were ob- tained for two types of poly-emitter anneals: (1) furnace anneals of 850-900°C and (2) a furnace

382 M. Arien:o et al. / Si-Ge alloys." growth, propertie.~ and applications

anneal of 8 5 0 ° C followed by a rapid thermal anneal (RTA) at 950-1050°C. The base-emit ter junction is positioned, in all cases, within the epitaxial grown layer. Forward characteristics for the base-emit ter junctions show ideality factors

near unity into the picoampere range for devices as large as 10000 p.m-'. Reverse leakage levels were the same for both the Si and Si -Ge-base tran- sistors. This leakage was "tunneling"-related, as confirmed by temperature measurements and by

A

B

Fig. 6. Cross-sectional TEM micrographs of a completed Si-Ge-base device formed using UHV/CVD low-temperature epitaxy: (A) low-magnification view; (B) high-resolution view of the Si-Ge/Si interface showing the epitaxial nature of the film [42].

M. Arienzo et aL / Si-Ge alloys: growth, properties and applications 3 8 3

i t i i

I 0,000/~m 2 /

10 -3 / ~ IO_l i " " - . . 850'C4" "-~ ~ "'" NO RTA I / /

,o-,, , - ;' -1.5 0 1.5

Ve[ (Volts) Fig. 7. Base-emitter junction characteristics of Si-Ge-base devices given a furnace anneal at 850°C and, in one case, a subsequent rapid thermal anneal (RTA) at 1050°C. In both cases, the base-emitter space charge region lies completely

within the LTE layer [421.

the dependence of this leakage on the peak base doping level.

3.3. Oxidation of Si-Ge layers

The thermal oxidation kinetics of Si-Ge alloys are found to be faster initially [31-34]. The oxide formed does not contain germanium, that instead piles up, resulting in a Ge-rich epitaxial layer at the oxide/substrate interface. The quality of the thermal oxides thus obtained are affected by the presence of germanium at the interface, and inter- face state densities below 10 u cm -2 eV-i are not easily attained for oxides thermally grown directly on Si I _~G¢~ layers. It is for this reason, as well as to try to minimize the thermal budget after the junction growth, that we have used in all our experiments either deposited oxides or thermal high pressure oxidation of Si buffer layers to achieve junction passivation.

4. S i / S i - G e heterojunction devices

Heterostructures and bandgap engineering have been widely exploited in compound semiconduc- tor systems, but only recently the ability to de- posit high-quality epitaxial silicon at low tempera- tures has opened the possibility to build these structures in silicon. By depositing in-situ doped

layers at temperatures below 700°C with high level of control, UHV/CVD has the unique capa- bility to form very shallow active layers of silicoii and silicon-germanium. This has to be contrasted with the conventional method of ion implanting silicon and determining the junction depth by the difference between two doping profiles, and eliminates the need of high-temperature heat treatments to activate dopants and eliminate the damage generated during implantation. As a re- sult, very sharp and narrow-doped regions can be obtained.

The major application of Si-Ge alloys in in- tegrated processes has been in the bipolar tran- sistors area. As mentioned earlier, pseudomorphic Si-Ge layers provide a bandgap reduction in the base which is dependent on the Ge content and the strain in the layer. Careful design of the band- gap profile is crucial in optimizing the device performance. When abrupt heterojunctions are used, conduction band spikes can form at the interfaces. At the base-emitter junction, such a spike can reduce the bandgap improvement, intro- duce a potential source of non-uniformity, and provide a sink for space charge recembination. At the edge of the base-collector jun." ion. a conduc- tion band spike can act as a barri~:r to minority- carrier transport across the base, resulting in in- creased charge storage and neutral base recombi- nation [35]. These problems can be avoided [36-38] and a possible improvement in the stability of the Si-Ge film [39] can be achieved by grading the bandgap across the space charge regions as shown in fig. 8.

The effect of a smaller bandgap in the base is to increase minority carrier injection into that region for a given base-emitter bias, resulting in an increase in collector current and current gain. This, in turn, implies less minority-carrier charge storage in the emitter at a given collector current level ('rE---- 1/fl, where fl is current gain and I" E is the emitter transit time [40]).

As proposed and analyzed by Kroemer [41], the base transit time in a heterojunction bipolar tran- sistor (HBT) can be shortened by providing a quasi-field across the base, i.e., grading the band- gap (Ge concentration) across the base, as also shown in fig. 8.

384 M Arienzo et al. / Si-Ge alloys: growth, properties and applications

N ~ P N-

1 OA.'" "-.

- !

- 2 I I I

0 50 100 150 200 Depth (nm)

Fig. 8. Band diagrams of Si I _ ~Ge,-base heterojunction devices. Grading across the junction avoids the presence of spikes at the interface, while grading across the base introduces an

aiding quasi-electric field.

The total collector current increase depends exponentially on the bandgap reduction integrated over the heavily doped portion of the neu~.ral base (wb*):

l~.(Si) Rhi(Si) [ w : e l~.(SiGe-~ ~ Rbi(SiGe ) X "o at'~t,)//,r dx,

(1)

where Rh, is the pinched base resistance. When the germanium is linearly graded across the base, and for grading >> kT. this can be written as [42]:

• ,.. (SiGe) fl(Si) l~(Si) • q:(Si) p(SiGe) l~(SiGe)

Rbi(Si) kT R hi (SiGe) e-a%'~'/~rAEg(~C- hE)

(2)

and the base transit time, %, is

% ( S i G e ) - 2kT [1 kT l , (3) %(Si) A Egta('- BE) AEgtaC_ BE)

where A Egtm.) is the germanium-induced bandgap reduction at the base-emitter depletion edge and AEg(IW_BI. ) is the bandgap grading across the heavily doped portion of the neutral base profile.

As it can be observed, the decrease in rE (due to the increase in current gain fl) depends ex-

ponentially on the bandgap reduction at the edge of the base-emitter junction, and is inversely pro- portional to the variation in bandgap across the base. rhe decrease in % depends solely upon the field induced by the variation in bandgap across the base. Note that only a 100 meV variation in bandgap across the base can improve the base transit time by 38% at room temperature. There- fore, the leverage of a Si-Ge-base transistor lies not exclusively in a higher current gain, but rather in the ability to reduce the pinched base resistance and emitter and base transit times. If the emitter delay is small, as it is in the case of polysilicon emitter devices, the gain improvement can be traded for lower base resistance and thus better circuit performance at high current.

An example of the final intrinsic transistor profile is given in fig. 4. The polysilicon/silicon interface is indicated by the peak in the arsenic profile, while the base-emitter junction is marked by the dip in the boron profile (caused by the electric-field coupling between arsenic and boron during diffusion [43,44]). The base-collector junc- tion occurs where the measured boron and phos- phorus concentrations intersect. As reported in ref. [45], we have built, using UHV/CVD, and measured the performance of transistors with the profiles shown in fig. 4, obtaining an emitter junc- tion depth and a base width of 30 and 45 nm, respectively. The intrinsic base sheet resistance of these devices was measured to be 17 k~2/EI. The germanium concentration was graded over :he heavily doped portion of the base to a peak con- centration of about 7% (as confirmed by Ruther- ford backscattering (RBS) analysis), adding a drift field of approximately 20 kV/cm to the base.

Fig. 9 shows the typical Gummel characteristics of the Si-Ge-base transistors. As can be seen in this figure, the junction characteristics are nearly ideal and the devices have a peak current gain of approximately 135. The frequency response of these transistors was measured, obtaining a peak cut-off frequency (fT) of 75 GHz, and a higher f r than the corresponding Si-base devices over a wide range of output current levels, as shown in fig. 10. Extraction of the intrinsic transit time from the measured dependence of fx on collector current (I¢) yielded a minimum value of 1.9 ps.

M. Arienzo et aL / Si-Ge alloys: growth, properties and apphcattons 385

L i i i i

I0-3

ic g 10 -6 m

i0-9

10-12 T 0 0.4 0.8 1.2

v~ (volts) Fig. 9. Oummel plot of the Si-Oe-base transistor. The intrinsic base sheet resistance is 17 kfl/[:3 and the on-wafer emitter area

is 0.9 x 4.5/tm -~ [451.

80 . . . . . . . i . . . . . . . . i AE=O.9x4.5 p.m 2

60 VCS=I V ~ ! I

20 _1~"-<,/,~ (x I0 '7 /c m3 NC

0 . . . . . . . l , , i iooool o n

I 1o Ic (mA)

Fig. 10. Dependence of f t on collector current for V(. B = 1 V: a

peak ]'r value of 75 G H z was obtained at 12.2 mA 145].

100 . . . . , . . . . , , l.-

SlGe LTE .--.l,,-e

50 F S I ~ L T E ~ -

Silicon Bipolar Transistor . 1 _ _ / I . . v~ =. Pv~ .',,"mon~e Records

g 20 v v T

~ ' • • • • • SIGe Rose ,o ." • . - : . . . . : a,0,,

1980 1985 1990 Publicolion Date

Fig. 11. Performance history of silicon bipolar transistors.

This high fT number is a world record, as indi- cated in fig. 11, where we have reported the highest values of f r reported in the literature for silicon- based bipolar transistors.

Other applications of Si heterojunctions to novel devices include modulation-doped field-ef- fect transistors (MODFET's) [46,47]. resonant tunneling diodes [48-50]. and bipolar inversion channel field-effect transistors (BICFET's) [51,52]. While pure silicon has found extended use in discrete detectors (such as APD's, PIN's) in the short wavelength regime ( --- 0.8/~m), the large gap of Si has precluded its use in integrated devices, or for long wavelength applications. Bandgap en- gineering combined with quantum-mechanical principles may allow Si t _ ~Ge, films to find poten- tial use in optoelectronic applications. For exam- ple, Si/Si I _.,Ge, strained layer superlattices (SLS) may be incorporated into the i-layer of PiN detec- tors. The smaller gap coupled with sub-band tran- sitions will allow the detectability range to be extended well into the long-wavelength regime (~ _> 1.3 /tm). Furthermore, these devices may be integrated with Si-based waveguides and device technology to provide front-end optoelectronic function in silicon technology.

4. Conclusions

The possibility offered by low-temperature epi- taxial processes to grow excellent quality strained SiGe alloys has given us the opportunity to lever- age band structure modifications and heterostruc- ture engineering in silicon technology. Abrupt doping transitions and ultra-thin, heavily doped layers grown by UHV/CVD have contributed to obtain record performance bipolar transistors in a process that can be easily integrated in conven- tional bipolar technology. Many other applica- tions will continue to be investigated to increase our understanding of the material, and to explore optoelectronic and quantum-mechanical applica- tions. The remaining challenges include the in- tegration of these devices in appropriate circuits, and the demonstration of their manufacturability and long-term reliability.

386 M A rwn:o el al. / S t -Ge alh~vs: growth, properne~ and apphcat,ms

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