Silicon nanowire FETs with uniaxial tensile strain S.F. Feste a, * , J. Knoch b , S. Habicht a , D. Buca a , Q.-T. Zhao a , S. Mantl a a Institute for Bio- and Nanosystems, IBN1-IT, Forschungszentrum Jülich, 52425 Jülich, Germany b TU Dortmund University, Micro- and Nanoelectronics Group, 44227 Dortmund, Germany article info Article history: Received 11 May 2009 Received in revised form 16 October 2009 Accepted 17 October 2009 Available online 4 November 2009 The review of this paper was arranged by Dr. M.C. Lemme Keywords: Si Nanowire Multi-gate devices Strained silicon Strain engineering abstract We present experimental results on on-current and transconductance gain and mobility enhancement in Si nanowire FETs (NW-FETs) fabricated on silicon-on-insulator (SOI) and biaxially tensile strained SOI (SSOI). The Si NW-FETs show very high I on =I off -ratios of 10 7 and off-currents as low as 10 13 A. Inverse sub-threshold slopes of about 80 mV/dec for SOI n- and p-FETs and 65 mV/dec for strained SOI n-FETs were obtained. The on-current and transconductance of Si NW-nFETs fabricated on strained SOI sub- strates are 2.5 and 2.1 times larger, respectively, compared to identical devices on SOI due to uniaxial ten- sile strain along the wires. An electron mobility enhancement by a factor of 2.3 in uniaxial tensile strained NW-FETs was found. Moreover, the on-currents of n- and p-NW-FET are more symmetrical compared to planar devices, differing only by a factor of 1.6, for h110i NW channel direction on a (1 0 0) wafer. Ó 2009 Elsevier Ltd. All rights reserved. 1. Introduction Improving the performance of field-effect transistors by down- scaling of the conventional silicon MOSFETs has become extremely difficult and technologically challenging: to avoid the appearance of short channel effects multi-gate architectures such as FinFETs and in particular gate-all-around (GAA) nanowire (NW) FETs have to be employed in ultimately scaled devices [1]. Recently such GAA NW-FETs with excellent performance have been demonstrated [2]. At the same time a lot of effort is devoted to high-mobility channel materials that enable performance improvements without scaling. In particular strained silicon is currently accepted as the key solu- tion for CMOS performance improvements being integrated into leading edge fabrication processes [3]. It is therefore appealing to combine a GAA NW-FET architecture with a high-mobility material in order to achieve the best performance possible. Biaxially strained silicon-on-insulator (SSOI) is particularly suited for this purpose since NW devices can be fabricated with accurate control of device position and crystalline direction in a top-down ap- proach. However, it is known that small islands of SSOI tend to re- lax depending on the structure length to width ratio leading to uniaxially strained silicon [4]. This can be employed in NW-devices to transform tensile biaxial strain to uniaxial tensile strain along the NW by lateral strain relaxation. In this study we investigate the performance improvement regarding on-current and transconductance gain, as well as elec- tron mobility enhancement, in Si NW-FETs fabricated on un- strained and biaxially strained SOI. Comparing SOI and SSOI a 2.5 times larger on-current, a 2.1 times higher transconductance and an electron mobility enhancement by a factor of 2.3 are observed in long channel SSOI NW-FETs. 2. Device and material fabrication Si NW-MOSFETs with h110i-channel orientation were fabri- cated on p-type doped (N A ¼ 1 10 15 cm 3 ) SOI and SSOI (100) wafers with an initial silicon thickness of 50 nm. The SSOI was manufactured using our unique thin virtual substrate technology together with wafer-bonding and layer transfer [5]: in the first step, a heterostructure consisting of a 6 nm pseudomorphic Si film and 180 nm Si 1x Ge x was grown by reduced pressure chemical va- por deposition (RPCVD) on 200 mm Si (1 0 0) wafers. The Ge con- tent for the material used in this experiments was x ¼ 0:23. After growth, the pseudomorphic Si 0:77 Ge 0:23 is compressively strained and strain relaxation was performed using the so called ‘‘Jülich process” which consists of He þ -ion implantation into the Si sub- strate and subsequent annealing; a detailed physical model of strain relaxation based on the generation of dislocation loops, the gliding of dislocation loops to the SiGe/Si (1 0 0) interface, the for- mation of threading dislocations (TD), their motion in the SiGe layer and the strain transfer to the thin top Si layer can be found elsewhere [6,7]. After the relaxation, the thin top Si layer is biaxi- ally tensile strained. By epitaxial growth the thickness of the strained Si layer is increased to 25 nm which is sufficient for the 0038-1101/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2009.10.013 * Corresponding author. Tel.: +49 2461 614505; fax: +49 2461 614673. E-mail address: [email protected](S.F. Feste). Solid-State Electronics 53 (2009) 1257–1262 Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Transcript
Solid-State Electronics 53 (2009) 1257–1262
Contents lists available at ScienceDirect
Solid-State Electronics
journal homepage: www.elsevier .com/locate /sse
Silicon nanowire FETs with uniaxial tensile strain
S.F. Feste a,*, J. Knoch b, S. Habicht a, D. Buca a, Q.-T. Zhao a, S. Mantl a
a Institute for Bio- and Nanosystems, IBN1-IT, Forschungszentrum Jülich, 52425 Jülich, Germanyb TU Dortmund University, Micro- and Nanoelectronics Group, 44227 Dortmund, Germany
a r t i c l e i n f o a b s t r a c t
Article history:Received 11 May 2009Received in revised form 16 October 2009Accepted 17 October 2009Available online 4 November 2009
The review of this paper was arranged byDr. M.C. Lemme
We present experimental results on on-current and transconductance gain and mobility enhancement inSi nanowire FETs (NW-FETs) fabricated on silicon-on-insulator (SOI) and biaxially tensile strained SOI(SSOI). The Si NW-FETs show very high Ion=Ioff -ratios of 107 and off-currents as low as 10�13 A. Inversesub-threshold slopes of about 80 mV/dec for SOI n- and p-FETs and 65 mV/dec for strained SOI n-FETswere obtained. The on-current and transconductance of Si NW-nFETs fabricated on strained SOI sub-strates are 2.5 and 2.1 times larger, respectively, compared to identical devices on SOI due to uniaxial ten-sile strain along the wires. An electron mobility enhancement by a factor of 2.3 in uniaxial tensile strainedNW-FETs was found. Moreover, the on-currents of n- and p-NW-FET are more symmetrical compared toplanar devices, differing only by a factor of 1.6, for h110i NW channel direction on a (100) wafer.
� 2009 Elsevier Ltd. All rights reserved.
1. Introduction tron mobility enhancement, in Si NW-FETs fabricated on un-
Improving the performance of field-effect transistors by down-scaling of the conventional silicon MOSFETs has become extremelydifficult and technologically challenging: to avoid the appearanceof short channel effects multi-gate architectures such as FinFETsand in particular gate-all-around (GAA) nanowire (NW) FETs haveto be employed in ultimately scaled devices [1]. Recently such GAANW-FETs with excellent performance have been demonstrated [2].At the same time a lot of effort is devoted to high-mobility channelmaterials that enable performance improvements without scaling.In particular strained silicon is currently accepted as the key solu-tion for CMOS performance improvements being integrated intoleading edge fabrication processes [3]. It is therefore appealing tocombine a GAA NW-FET architecture with a high-mobility materialin order to achieve the best performance possible. Biaxiallystrained silicon-on-insulator (SSOI) is particularly suited for thispurpose since NW devices can be fabricated with accurate controlof device position and crystalline direction in a top-down ap-proach. However, it is known that small islands of SSOI tend to re-lax depending on the structure length to width ratio leading touniaxially strained silicon [4]. This can be employed in NW-devicesto transform tensile biaxial strain to uniaxial tensile strain alongthe NW by lateral strain relaxation.
In this study we investigate the performance improvementregarding on-current and transconductance gain, as well as elec-
ll rights reserved.
: +49 2461 614673.
strained and biaxially strained SOI. Comparing SOI and SSOI a 2.5times larger on-current, a 2.1 times higher transconductance andan electron mobility enhancement by a factor of 2.3 are observedin long channel SSOI NW-FETs.
2. Device and material fabrication
Si NW-MOSFETs with h110i-channel orientation were fabri-cated on p-type doped (NA ¼ 1� 1015 cm�3) SOI and SSOI (100)wafers with an initial silicon thickness of 50 nm. The SSOI wasmanufactured using our unique thin virtual substrate technologytogether with wafer-bonding and layer transfer [5]: in the firststep, a heterostructure consisting of a 6 nm pseudomorphic Si filmand 180 nm Si1�xGex was grown by reduced pressure chemical va-por deposition (RPCVD) on 200 mm Si (100) wafers. The Ge con-tent for the material used in this experiments was x ¼ 0:23. Aftergrowth, the pseudomorphic Si0:77Ge0:23 is compressively strainedand strain relaxation was performed using the so called ‘‘Jülichprocess” which consists of Heþ-ion implantation into the Si sub-strate and subsequent annealing; a detailed physical model ofstrain relaxation based on the generation of dislocation loops, thegliding of dislocation loops to the SiGe/Si (100) interface, the for-mation of threading dislocations (TD), their motion in the SiGelayer and the strain transfer to the thin top Si layer can be foundelsewhere [6,7]. After the relaxation, the thin top Si layer is biaxi-ally tensile strained. By epitaxial growth the thickness of thestrained Si layer is increased to 25 nm which is sufficient for the
Fig. 2. Main process steps for the fabrication of SOI and SSOI NW-FETs. The SEMimages show the device in several process steps: (i) after RIE etching of the NW andthe S/D areas; (ii) cross-section SEM of the NW channel after oxidation and polySideposition; and (iii) overview of the device after gate patterning.
fabrication of fully-depleted devices. Strained silicon-on-insulatorwafers were obtained by layer transfer to an oxidized handle waferusing wafer-bonding, splitting and SiGe spin-etch [8].
For the realization of partially depleted devices and in particularfor the geometry-dependent strain relaxation studies presentedhere, thicker SSOI layers are required. Therefore, a third epitaxialgrowth step was performed in which the strained Si thicknesswas increased to 60 nm. The final SSOI structure used in our exper-iments consists of 60 nm SSOI on 145 nm buried oxide (BOX) and isshown in Fig. 1. The SSOI layer has a very smooth surface with anrms roughness of 0.4 nm and a threading dislocation density below1� 105 cm�2. The strain in the SSOI layer was determined by Ra-man Spectroscopy and Rutherford Backscattering/Channeling mea-surements to be �biax ¼ 0:65%, corresponding to a stress ofrbiax ¼ 1:2 GPa. These values indicate a relaxation degree of 70%for the Si0:77Ge0:23 layer, with full strain incorporation (and norelaxation) into the top Si cap layer during the SSOI fabrication.
The SSOI is first thinned to a thickness of 50 nm by a cycle oflow temperature thermal oxidation, followed by diluted HF strip-ping of the oxide. Different types of NW devices were fabricatedon 50 nm SOI and SSOI substrates: (1) p-type FETs withL ¼ 1:5 lm on SOI and (2) n-type FETs with L ¼ 1:5 lm andL ¼ 3 lm on SOI and SSOI. The cross-section and gate oxide thick-ness of all fabricated devices was � 42� 42 nm2 and tox ¼ 5 nm,respectively. Source/drain areas and the NW channel were definedby electron-beam (e-beam) lithography and reactive ion etching(RIE). To reduce side-wall roughness of the NWs after RIE etching,samples were subject to a sacrificial oxidation, followed by dilutedHF stripping before the gate oxide was grown by dry oxidation at850 �C for 15 min. The remaining silicon thickness was 42 nm(Fig. 2). Two hundred nanometer n-type poly-Si and 80 nm SiO2
were deposited immediately after the gate oxidation in a low-pres-sure chemical vapor deposition (LPCVD) tool. E-beam lithographyand RIE were used to define the gate. The p-type devices were im-planted with boron ð4 keV;1� 1015 cm�2Þ and the n-type deviceswith arsenic ð16 keV;5� 1014 cm�2Þ. A protective 80 nm SiO2 layerwas deposited by LPCVD before the dopants were activated by RTAat 1000 �C for 10 s. Contact windows were opened and an alumi-num metallization was deposited by electron-beam evaporationand lift-off. Finally, the devices were annealed at 400 �C for10 min in forming gas ðH2 : N2=10 : 90Þ. Fig. 2 shows the main pro-cess steps together with SEM pictures of devices after RIE etchingof the NW (i), a cross-section SEM of the NW after oxidation and
Fig. 1. TEM image of the SSOI structures used in the experiments. The SSOI layerhas a thickness of tSSOI ¼ 60 nm with a stress of rbiax ¼ 1:2 GPa. The thickness of theBOX is tBOX ¼ 145 nm. The threading dislocation density in SSOI is below1� 105 cm�2 and the surface roughness has an rms value of 0.4 nm.
poly-Si deposition (ii), and a bird’s eye view of the whole transistorincluding the large source, drain and gate electrodes (iii).
3. Electrical characterization
In this section we will discuss the electrical properties of n- andp-type NW-FETs fabricated on SOI and SSOI with emphasis on theperformance improvement of n-type devices obtained using SSOIsubstrates.
Fig. 3 shows the transfer characteristics of n- and p-type SOINW-FETs with a gate length of L ¼ 1:5 lm. Both devices feature ahigh Ion=Ioff -ratio, low off-currents and good inverse sub-thresholdslopes of about 80 mV/dec.
In multi-gate devices current flows on planes with different sur-face orientations which have different mobilities due to the anisot-ropy of Si. It is therefore possible to optimize Ion of n- and p-typedevices by choosing the appropriate channel direction andheight-to-width ratio of the channel [9]. Hole mobility is largeston the (110)-surface with transport in the h110i-direction, whileelectron mobility is much lower on the (110)-surface comparedto its maximum value on the (100)-surface [10]. However, evenwhen electron mobility is low on the (110)-surface with currentalong a h110i-direction, this orientation is preferred since it pro-vides the best compromise between n- and p-type NW-FET perfor-mance [11]. Therefore, in this study channels were aligned alongthe h110i-direction, the vertical side-walls of the devices thusbecoming ð1 �10Þ-planes, while the top surface is a (001)-plane asschematically illustrated in Fig. 6. In this case the performance ofn- and p-type NW devices with identical geometry should bemore symmetric if the source/drain resistances are comparable.We estimated the on-current ratio between n- and p-type FETsfor our devices, where 2/3 of the inverted surface area is of(110)- and 1/3 of (100)-type and for an inversion charge density
Fig. 4. (a) 50 nm SSOI with 1.2 GPa biaxial tensile stress on top of 145 nm BOX isused as starting material. (b) Sketch of the fabricated device. Uniaxial tensile strainalong the NW is obtained by lateral strain relaxation of patterned SSOI layers.
V (V) g 2 -1 0 1
I (A
) d
10 -11
-2
S=81
mV/
dec S=83m
V/dec
V (V) g
2 1 0 -3 -2 -1 3 0.0
0.5
1.0
1.5 I (µ
A)
d
2.0
3.0
2.5
3.5
V = 50..350mV ds
10 -9
10 -7
10 -5
Fig. 3. Transfer characteristics of n- and p-type NW-FETs fabricated on 50 nm SOI.Both devices have a channel length of L ¼ 1:5 lmand a gate oxide thickness oftox ¼ 5 nm. Very low off-currents and good Ion=Ioff -ratios were obtained. The on-currents of n- and p-NW-FETs are more symmetrical compared to planar devices,differing only by a factor of 1.6, for h110i channel direction on a (100) wafer.
of ninv ¼ 1� 1013 cm�2, on the basis of the mobility values reportedin [10], to be Id;n=Id;p � 1:2 using the simple approximation:
Id / W ð1 0 0Þlð1 0 0Þe=h;h1 0 0i þW ð1 1 0Þlð1 1 0Þ
e=h;h1 1 0i
� �: ð1Þ
However, in our case the current of the n-type devices atVg ¼ Vd ¼ 1:2 V is still 1.6 times larger than that of the p-type de-vices of equal geometry. This value is smaller compared to value ofcommonly found for standard planar devices of Id;n=Id;pðplanarÞ � 3but not as small as theoretically expected [12]. We interpret thisdiscrepancy as follows: (i) the fabricated p-type devices had a largersource/drain resistance compared to the n-FETs as extracted fromthe output characteristics at low Vds and high Vg and (ii) the trape-zoidal cross-section of the NWs indicates a deviation of the verticalside-walls from the (110)-surface, thereby reducing the contribu-tion of the high hole mobility (110) surfaces to the effective widthof the device.
The low electron mobility on the (110)-surface in the h110i-direction can be improved through strain engineering. Uniaxialtensile strain has been shown to alter the sub-band structure inthe inversion layer [13]. On (100)- and (110)-surfaces tensile uni-axial strain along h110i lowers the energy of the D2-valleys rela-tive to the D4-valleys, thereby increasing their occupation(Fig. 6b). On the (110)-surface the D2-valleys have the transverseeffective electron mass in h110i-direction and the longitudinaleffective electron mass ml along the h001i-direction, ensuring ahigh mobility and a high density of states for the sub-band(Fig. 6c). Regarding the (100)-surface, uniaxial tensile strain alongh110i achieves nearly equal electron mobility enhancement asbiaxial strain [10]. The preferentially occupied D2-valleys havethe lower effective electron mass mt in transport direction andconduction band warping, caused by tensile uniaxial strain alongh110i, additionally reduces mt below its value in bulk Si (Fig. 6d)[14,15].
In order to investigate the improvement of device performancethrough strain n-type devices were also fabricated on SSOI. Waferlevel unpatterned biaxial SSOI layers are robust to relaxation evenwhen the critical thickness of strained Si is exceeded. However,small isolated structures of strained Si become susceptible to strainrelaxation [4]. The relaxation sensitively depends on the island
dimensions and the process conditions [16]. In a previous workwe have shown that strain relaxation depends on the geometryof the structure using 2D finite element (FEM) simulations [17].In FEM simulations shown here an initial biaxial tensile stress of1.2 GPa for the unrelaxed state was assumed as measured on fullSSOI layers. Strain relaxation was modeled by removing the tensileforces from the long sides of the NW and allowing these sides tomove freely [24]. It was found that lateral stress relaxation in longNWs increases with increasing length-to-width-ratio while most ofthe initial tensile strain is preserved along the lines. For the struc-ture displayed in Fig. 5 (with a large length to width ratio as in thefabricated long channel devices) about 80% (�1 GPa) of the initialstress is maintained along the NW after relaxation according tothe FEM simulations. This result is in agreement with nanobeam-diffraction (NBD) and micro-Raman measurements performed onstructures with similar cross-section and length of several lm[18–21]. Our simulation results indicate a nearly complete lateralstress relaxation (Fig. 4b) as measured using NBD by Irisawaet al. [21], while Collaert et al. [20] measured a lateral stress relax-ation of about 70% employing micro-Raman. Note that micro-Ra-man measures an average of the two in-plane stress componentsrxx and ryy. To decouple the components of the stress tensor alongand perpendicular to the NWs, input from and comparison withFEM simulations is necessary [22,23].
On the basis of our FEM simulation results and the micro-Ra-man and NBD data obtained on similar structures, we expect thatlateral strain relaxation occurs during device processing of NW-FETs fabricated on biaxial tensile strained SSOI. The tensile stressalong the NW is maintained at a high degree due to the connectionof the wire to the large source/drain contacts. This is illustrated inFig. 5a and b. Measurements on planar long channel MOSFETs fab-ricated using our SSOI substrates showed a 1.8 times higher on-current and a similar improvement in mobility.
In Fig. 7a the transfer characteristics of a SSOI n-FET withL ¼ 1:5 lm are shown on a linear and logarithmic scale. As forthe SOI devices, a high Ion=Ioff -ratio and inverse sub-thresholdslopes close to ideal with a value of S ¼ 65 mV=dec are measuredon strained NW-nFETs. In Fig. 7b the output characteristic isshown, featuring good saturation. Comparing parallel processedSOI and SSOI devices it was observed that the average inversesub-threshold slope of the SSOI devices was better than that ofthe SOI devices which we assume to be related to strain improve-ments of the Si=SiO2 interface.
To investigate the influence of the retained tensile strain in aNW channel patterned from SSOI after lateral strain relaxation,SOI and SSOI devices were compared. Fig. 8a shows the transfercharacteristics of a strained and an unstrained n-NW-FET withL ¼ 3 lm. The nanowires have an identical square cross-sectionof � 42� 42 nm2 and a length of 3 lm. The inverse sub-thresholdslope of both devices is between 70 and 80 mV/dec. Both deviceshave a very low off-current and a high Ion=Ioff -ratio while the on-current of the uniaxially strained device is strongly enhanced. InFig. 8b a statistical Ion=Ioff -plot for SOI and SSOI NW-FETs with
Fig. 5. 2D finite element simulation of the stress distribution after lateral stressrelaxation of a long channel NW. An initial biaxial tensile stress of 1.2 GPa wasassumed. (a) After lateral stress relaxation a tensile along the NW of �1 GPa isobtained. (b) The stress perpendicular to the long wire axis relaxes nearlycompletely.
001
110
3,5
4,6
1 2
(110)
110
110
3
4
5
6
(001)
tens
ile s
tress cu
rrent
flow
curre
nt fl
ow
tens
ile s
tress
Δ6Δ4
Δ2
ΔEst
rain
ΔEco
nf
+
E0Δ2
E0Δ4
E1Δ2
ΔEst
rain
uniaxial tensile strain
strain +confinement
Δ2
Δ2
Δ4
Δ4
Δ4
Δ4
3
4
56
1
2
100
010001
curre
nt flo
w &
stra
in
110(b)(a)
(d)(c)
Fig. 6. (a) Constant energy surfaces of the silicon conduction band. Current andstrain in the fabricated devices are along the [110]-direction. (b) Uniaxial tensilestrain along the [110]-direction lifts the six-fold degeneracy of the siliconconduction band minimum by lowering the energy of the D2-valleys and increasingthe energy of the D4-valleys on the (001)- and on the (110)-surface. Confinementfurther increases the splitting between the D2- and D4-levels. The projections ofthe constant energy surfaces on the ð1 �10Þ and the (001) surface are shown in (c)and (d). The lower lying D2-valleys have on both surfaces the low transverseelectron mass mt in the direction of current flow. Strain induced conduction bandwarping on the (001) plane decreases mt below the unstrained value.
V (V) ds
2.0 1.5 0 0.5 1.0 0
4
8
12
I (µ
A)
d
16
SSOI L=1.5µm V = -25...950mV gt
V (V)g
1.51.00.5-1 0.5 0.0
I (A
)d
10-7
10-5
10-9
10-11
10-13
0
1.0
2.0
3.0
I (µ
A)d
4.0
5.0
2.0
6.0SSOIL=1.5µm V = 50..250mVds
S=65
mV/
dec
(a)
(b)
Fig. 7. (a) Transfer characteristic of a n-type NW-FET fabricated on 50 nm SSOI witha tensile stress of 1.2 GPa. Due to the good electrostatics the device has a low off-current and a high Ion=Ioff -ratio and (b) output characteristic of the NW-FET on SSOIfeaturing good saturation.
L ¼ 3 lm is displayed. Uniaxial tensile strain results, on average, ina 2.5 times larger on-current, while no degradation in Ioff is ob-served. A similar enhancement of the transconductance of SSOIcompared to SOI devices was found. In the inset of Fig. 8 the trans-conductances of an unstrained and a strained NW-FET withL ¼ 3 lm are plotted for Vds ¼ 250 mV. The maximum transcon-ductance of the strained NW-FET is a factor 2.1 times larger thanthat of the unstrained FET. These results are in excellent agreementwith published data on similar devices: Irisawa et al. [21] reportedon-current and transconductance enhancements of 2.5 and 2.2times, respectively, for a similar device and stress of 1.2 GPa whileCollaert et al. [20] found an on-current enhancement of 1.8 timesfor long channel devices with a lower stress of 800 MPa.
An accurate determination of the carrier mobility relies on mea-surements of the carrier concentration and the channel resistance.For planar devices capacitance–voltage (C–V) or Hall-effect mea-surements are widely used to determine the carrier concentration.Due to the non-planar geometry of NW-FETs the Hall-effect cannotbe employed to access the carrier concentration and C–V measure-ments are very difficult due to the ultra-small capacitances of indi-vidual NWs (aF to fF level) over large background capacitances (pFlevel) [25,26]. Approximating the capacitance by analytical formu-las easily results in inaccurate values for the capacitance and there-fore for the mobility [27]. Here, we investigated the impact ofstrain on electron mobility in individual NW-FETs using theId=
ffiffiffiffiffiffigmp
-method. The inset of Fig. 8a shows a plot of Id=ffiffiffiffiffiffigmp
versusVg for a strained and an unstrained device measured at a source-drain voltage of Vds ¼ 50 mV. The slope
ffiffiffiAp
of the linear part ofthe curves is related to the carrier mobility by A ¼ lCox
WL Vds. To
extract the carrier mobility from this formula it is necessary toknow the gate capacitance Cox. For devices with equal channelcross-section and gate-oxide thicknesses, as is the case for the
Fig. 8. (a) Transfer characteristics of two NW-FETs, one fabricated on SOI and oneon SSOI. The channel length of both devices is L ¼ 3 lm and the gate oxidethickness tox ¼ 5 nm. Both devices have sub-threshold slopes of 70–80 mV/dec. Dueto uniaxial tensile strain the device fabricated on SSOI has a larger on-current. Theinset shows the Id=
ffiffiffiffiffiffigmp
-plot for the two devices. The slope in the linear region isrelated to the carrier mobility. An electron mobility enhancement by �2.3 is foundfor SSOI devices. (b) Statistical Ion=Ioff -plot for SOI and SSOI NW-devices withL ¼ 3 lm. Uniaxial strain in SSOI NW-FETs results in a �2.5 larger Id;sat, while nodegradation of Ioff is seen. In the inset the transconductance for two NW devices isplotted. The strained NW-FET features a �2.1 larger transconductance compared tothe unstrained FET.
investigated devices, a mobility enhancement factor x can be deter-mined without knowing the capacitance:
x ¼ lSSOI
lSOI¼ ASSOI
ASOI� LSSOI
LSOIð2Þ
where LSOI and LSSOI are the channel length of the SOI and SSOIdevices, respectively. For the compared devices the mobilityenhancement due to uniaxial tensile strain is found to be x ¼ 2:3.This mobility enhancement is consistent with the results reportedfor similar devices in Ref. [13] and for long channel devicesunder biaxial tensile strain in Refs. [10,28,29]. These results demon-strate that the uniaxial tensile strain generated in the NW by lateralstrain relaxation is large enough to significantly improve deviceperformance.
4. Conclusion
We experimentally studied on-current and transconductancegain as well as the electron mobility enhancement of NW n-FETsaligned along the h110i-direction fabricated on (001) SSOI com-pared to SOI. A 2.3 times higher on-current and equally improvedtransconductance was obtained. An electron mobility enhance-ment factor of 2.3 for NW-FETs on SSOI over identical devices onSOI was found. These enhancements are attributed to the highlevel of uniaxial tensile strain maintained in NWs on SSOI afterlateral strain relaxation. Furthermore, it was shown that the on-current difference between n- and p-type multi-gate devices onSOI can be reduced if the channels are aligned along the h110i-direction on a (100) wafer.
Acknowledgements
This research has received Nanosil funding from the EuropeanCommunity (FP7, Grant No. 216171) and from the German FederalMinistry of Education via the MEDEA+ project DECISIF (2T104).
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