Stepwise equivalent conductance circuit simulation technique

612 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12. NO. 5 , MAY 1993

Stepwise Equivalent Conductance Circuit Simulation Technique

I

Shen Lin, Member, IEEE, Ernest S . Kuh, Fellow, IEEE, and M. Marek-Sadowska, Member, IEEE

Abstruct-In this paper we introduce a new circuit simulation technique based on a stepwise equivalent conductance model of a nonlinear resistive device. The major advantage of this technique is to eliminate the need for employing Newton-Raphson iterations for the implicit integration. The technique, when ap- plicable, is consistent, absolutely stable, and convergent. Fur- thermore, we demonstrate that a second order of accuracy (the local truncation error for integration is of the cubic order of the time step used) is achieved by solving linear equations for each integration step.

When applied to digital MOS circuits, the technique takes advantage of the fact that voltage waveforms can be modeled to a good approximation as piecewise-linear functions and thus achieve further speed-up in the simulation. The program, called SWEC, has been implemented, and has proven to be accurate and efficient on a large number of circuit examples. The com- parisons of results with Relax2.3 [7], iSPLICE3.0 [5], [17], XPsim [2], and SPECS2 [3] are given.

I. INTRODUCTION ENERAL-PURPOSE circuit simulators such as G. SPICE and ASTAP have been the bread and butter

of industry and university researchers in circuit simulation for over two decades. However, as VLSI circuits get larger, new approaches are sorely needed. Timing simulators based on relaxation and other techniques have proven useful, but they lack predictability and are thus not generally trusted or accepted. Another approach is to em- ploy parallel processing. Although some research has been done, its value has been restrictive because parallel ma- chines are not generally available today. In this paper we present a simple method which replaces nonlinear elements with a stepwise equivalent time-varying model. We will demonstrate its generality as well as its effectiveness in handling digital CMOS circuits.

The implicit multistep integration algorithms used in SPICE2 and ASTAP are computationally much more expensive than explicit integration schemes, because at each step an implicit solution of a large nonlinear algebraic

Manuscript received September 7, 1990; revised September 22, 1992. This work was supported by NSF under Grant 88-0371 and MICRO. This paper was recommended by Associate Editor A. Ruehli. S. Lin was with the Department of Electrical Engineering and Computer

Science, University of California, Berkeley, CA. He is now with the IBM Thomas J . Watson Research Center, Yorktown Heights, NY 10598.

E. S. Kuh is with the Department of Electrical Engineering and Com- puter Science, University of California, Berkeley, CA 94720.

M. Marek-Sadowska is with the Department of Electrical Engineering and Computer Science, University of California, Santa Barbara, CA 93106.

IEEE Log Number 9206837.

system needs to be determined. However, compared with explicit algorithms, the extra computation does not really improve the solution’s accuracy. We need to go through the computationally expensive Newton-Raphson iterations in the implicit algorithms mainly to achieve stability. This leads us to wonder if there really is no easy way of obtaining stability while retaining accuracy, and that is the motivation of our research.

If the circuit simulation program is intended for the simulation of MOS digital circuits, then it is possible to make use of the special properties of such circuits to improve the efficiency of the implicit integration. Digital MOS circuits can be decomposed into subcircuits with weak coupling between them; due to the time latency behavior, each subcircuit can be integrated with different time steps to maintain the desired accuracy. These characteristics have been exploited in relaxation-based simulators, such as SPLICE [41, [ 5 ] , [17], and waveform-relaxation simulators, such as Relax2.1 [6], [7] and IDSIM2 [ 121 (the Partial Waveform Convergence [ 151). However, the efficiency will be impaired when simulating tightly coupled analog circuits, For tightly coupled analog circuits, it takes a lot of computation for the solutions to converge. To avoid being trapped in the lengthy iteration process, a single iteration Gauss-Jacobi-Newton method has been proposed and applied in the simulators of MO- TIS [9] and Event-EMU [ 101. They conjectured that there exists a small enough time step to obtain the solution in exactly one iteration. However, to maintain the desired accuracy in most cases very small time steps need to be used, and that unfortunately degrades the efficiency.

To gain efficiency, simplified circuit models have been proposed, e.g., the electrical logic model (ELogic) [8], the piecewise-constant model of SPECS2 [3], and the ex- ponential integration method of XPsim [2]. All of them, however, experience problems with accuracy and some- times stability because of their explicit integration approach.

In this paper, we propose a stepwise equivalent conductance circuit simulation method, which treats every nonlinear resistance device as a two-terminal linear time- varying conductor. We show that implicit integration can be efficiently applied to this type of circuit under a given error criterion. No nonlinear equations need to be solved. The technique is proved to be consistent, absolutely stable, and convergent.

The stepwise equivalent conductance circuit simulation

0278-0070/93$03.00 0 1993 IEEE

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LIN er al.: STEPWISE EQUIVALENT CONDUCTANCE SIMULATION 613

makes the following two assumptions regarding the simulated circuits:

Every node in the circuit has nonzero capacitance to ground. In fact, this assumption does not place any restriction on the simulated circuit because practically every node in a real circuit has nonzero para- sitic capacitance to ground. Every nonlinear device in the circuit has a unique current path. Examples of these kinds of devices are MOS, JFET, and diodes.

When focusing on digital CMOS circuits, we demonstrate that additional speedups can be achieved by the use of a specific event-driven approach to take advantage of the piecewise linear waveforms. Most of the time the voltage waveforms of the outputs from CMOS gates can be approximated by straight-line segments. We show how to make use of this property in the timing simulation. In [ l ] a preliminary version of a timing simulator, SWEC, was discussed.

The paper is organized as follows. In Section 11, we introduce the transformation from a nonlinear circuit to an equivalent circuit of two-terminal linear time-varying conductors and discuss the exactness of the solution of the linear time-varying circuit under the “smooth” I-V characteristic assumption. In Section 111, an accurate and efficient algorithm to integrate the linear time-varying circuit is introduced. The accuracy and the convergence of the algorithm are analyzed. In Section IV, we discuss the choice of timesteps for integration. In Section V, a CMOS timing simulator, SWEC, which is based on the above concepts, is introduced. We discuss SWEC’s event- driven mechanism, which exploits the piecewise-linear voltage waveform property, in detail. In Section VI, we present experimental results of SWEC along with com- parisons with SPICE, iSPLICE3.0, Relax2.3, XPsim, and SPECS2 programs. Finally, Section VI1 offers our conclusions and future work.

11. EQUIVALENT LINEAR TIME-VARYING CIRCUIT TRANSFORMATION

2.1. Circuit Equations For the sake of simplicity, we start with the assumption

that there are no inductors in the simulated circuit and that all the capacitors are constant. We extend the discussion to circuits with linear inductors, nonlinear capacitors, and nonlinear inductors in Appendix A by using modified nodal analysis. The KCL nodal equations for the simulated circuit will be of the form:

(1) where V( t ) is the node voltage vector, 5 ( - ) is a vector function of V ( t ) with its ith entry representing the total current flowing out of node i through resistive devices, C is the constant capacitance matrix, and Z,(t) is the vector of inputs (represented as current sources). Independent voltage sources can be considered by the modified nodal

S(V( t ) ) + CV(t) = Z,(t)

analysis as well. Since every node is assumed to have nonzero-grounded capacitance, C is diagonally dominant. If 5 is nonlinear, then the implicit integration of (1) for each timestep involves solving a system of nonlinear equations. Computationally expensive Newton-Raphson iterations are generally needed to find the solutions.

The unique current path assumption of nonlinear devices implies that the simulated circuit can be treated as an equivalent circuit with two-terminal resistive elements only. To be more specific, the I-V characteristic of every nonlinear device at each time point can be characterized by its instantaneous equivalent conductance G(t ) defined as the ratio of I and V across the two terminals of the current path evaluated at that time instant. I Therefore, during the entire simulation process, we are simulating a circuit composed of only linear time-varying conductors and linear time-invariant elements.

Then, (1) can be transformed into the equation below:

G(t) V( t ) + CV(t) = Z,(t). (2)

Here, G(t ) represents the instantaneous equivalent conductance matrix for every branch in the circuit at time t. G(t) will satisfy the following relation:

G(t) V( t ) = S(V(f ) ) (3)

for every time r . Instead of solving for the V ( t ) of (1) directly, the step-

wise equivalent conductance circuit simulation solves for the V ( t ) of (2) and uses it as the solution for (1). An efficient implicit integration scheme for (2) is developed, and no nonlinear equations need to be solved. The integration scheme will be introduced in Section 111.

The question remaining is whether the solution of (2) will be equal to that of (1).

2.2. Exactness of the Transformation If we know G(t ) beforehand, then the uniqueness of the

solution of (1)’ implies that the solution of (2) will be the same as the solution of (1). However, during the process of solving (2), for every time t, we only know the function G up to time t and not beyond that. Will we end up with a different solution due to the lack of information of G? To answer this question, we state the following theorem.

Theorem 1: If 5 ( - ) and I , ( - ) of (1) are continuously differentiable, then the solution of (2) will be exactly the same as that of (1).

Proof: We prove this by contradiction. Denote the solution of (1) by VI (t) and the solution of (2) by Vz( t ) . If they are not the same, then there exists a time to such that VI and V, coincide at to but depart from each other afterwards, i.e., there exists a positive integer k such that

‘G( t ) is set to zero if V ( t ) = 0. The situation where I ( t ) # 0 when v(t)

’The sufficient condition of the uniqueness of the solution of ( 1 ) is that = 0 is practically impossible.

V i s Lipschitz continuous at every time t .

614 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 5 , MAY 1993

Vy)(to) = Vf)(to) v i < k and Vy)(to) # Vf’(to), where Vy’(to) denotes the ith derivative of VI (t) evaluated at to.

(4)

We know, from ( l ) ,

V, ( t ) = c - ’ ( - s ( v , ( t ) ) + Z,(t))

V2(t) = c - ’ ( - G ( t ) V,(t) + Z,(t)>

and from ( 2 ) and (3),

= c - 1 ( - 5 ( v * ( t ) ) + ZAt)). ( 5 )

Note the inverse of C exists because C is diagonally dominant as mentioned before. From successive differentiation of VI (t) we have that V\k)(to) is a function of Vy’(to) and Zf)( to) for i < k. Similarly, Vik) (to) is the same function of V$)(to) for i < k. Since Vy’(to) = Vf’(to) V i < k, we find that V\k’(to) is equal to Vik’(t0), which con- tradicts that to is a departing point for VI (t) and V2(t).

0 Theorem 1 tells us that for the numerical integration of

( 2 ) , although we do not know the function G after the current time t, we do know the time derivatives of G at t up to the infinite order and thus can uniquely determine G for a small time interval beyond c . This can in turn be used to determine Vfor that small interval.3 The sufficient condition of theorem 1 is that 5 of (1) be continuously differentiable, which seems rather restrictive because it excludes piecewise-continuous I- V characteristics. To relax this restriction for the purpose of numerical integration we do the following:

use small time steps only when any piecewise characteristic in the circuit undergoes two different operating regions, use an absolutely stable integration scheme.

Then, even though the sufficient condition is not satisfied strictly, the numerical solution of ( 2 ) can still yield very good accuracy.

111. THE STEPWISE EQUIVALENT CONDUCTANCE INTEGRATION ALGORITHM

For the integration of each time step, we assume that the equivalent conductances of the time-varying conductors remain constant during the time step. Therefore, for the calculation purpose, we are dealing only with linear constant circuit elements. The constant value assumed for each time-varying conductor can be determined to yield the necessary accuracy .4

’For the integration from t,, to t , + I, we only know 5 ( V ( t ) ) is equal to C(t) V( t ) up tot,. The above proves that 5 ( V ( t ) ) will be equal to G(r) V(r) from t , to t , + I once they coincide with each other up to t , .

4At first glance, our approach may seem similar to Crystal [ l 11 since both exploit the idea of using efecrive conductances. For the whole transition, Crystal replaces every MOS transistor by an effective conductor to estimate the timing information. There is no integration in Crystal, whereas, our approach is trying to determine the effective conductances which can summarize the total electrical effects during a time step. Furthermore, the goal of our approach is to determine the complete transient characteristics.

Using Taylor’s series expansion of G(t) at t = t,. we obtain from (2),

[G(t,) + G ( f , ) ( t - t,) + iG(t , ) ( t - t,)2 + - * * ] V(t)

+ CV(t) = Z,(t). (6)

Let

h, = t, + I - t,. (7)

We show that for t E [t,, t , + (6) can be approximated by

SV(t) + CV(t) = I&) (8)

with 6 = G(t,) + ( h n / 2 ) G ( t n ) . To solve V(t,+ I ) from a given V(t,) an error is introduced which is proven in Ap- pendix B to be

- c - I G (t,) V(t,) ($) - c - I a t , ) (C - I G(t,) V(t,)

(9)

By using the trapezoidal rule of integration, we obtain

(10)

This leads to the total local truncation error for the integration from r, to r, + of the order 0 (h3). The method is, therefore, consistent with respect to the local truncation error, and since we know that the integration scheme- the trapezoidal rule-is absolutely stable, we have demonstrated the convergence of the algorithm.

IV. TIME STEP SELECTION The local truncation error for each integration will be

equal to the error given in (9) plus the error introduced from the trapezoidal rule approximation of V(t, + I ) . Therefore, given the error criterion on the local truncation error at t,, we can solve for the necessary time step h, exactly. A variable timestep integration scheme can be implemented. However, (9) is very complicated. Deter- mining h, involves several matrix operations. It would be impractical to perform the matrix operations at every time point. Therefore, we introduce a simpler scheme of choosing h,. By using two parameters, a voltage error A V and a relative error E , we can derive the following: For each conductance Gi and for each node voltage 5, if h, meets the constraints imposed on (1 l) , then the norm of the error introduced in (9) will be less than (€ /3)AV, which is derived in Appendix C:

LIN et al.: STEPWISE EQUIVALENT CONDUCTANCE SIMULATION 675

and

h,,c(t , ,) I A V v j . (1 IC) The advantage of this is that the computation of deter-

mining a timestep meeting all the constraints in (11) is linear in terms of nodes or devices in the circuit, while the computation needed to solve (9) is of the cubic order.

V. SWEC: A STEPWISE EQUIVALENT CONDUCTANCE TIMING SIMULATOR FOR DIGITAL CMOS VLSI

CIRCUITS As an application, a timing simulator for digital CMOS

VLSI circuits, SWEC, has been implemented based on the above concepts [l]. To speed up further the simulation, SWEC first decomposes the circuit into weakly cou-

ductance technique to each of the subcircuits. In addition, SWEC exploits another special property of CMOS circuit; that is, the voltage waveforms of the outputs from

- - -

f -

I bD+Es pled subcircuits and applies the stepwise equivalent con- -

Fig. 1. Electrical model for a MOS transistor.

CMOS gates can be approximated by straight-line segments most of the time. Because of this property, larger timesteps can be used. To handle feedback inside the circuits and to exploit further the latency and multirate behavior of MOS circuits, a special event-driven mechanism based on the piecewise linearity of voltage waveforms has also been developed and built into SWEC. We have developed an algorithm to determine the breakpoints of the piecewise-linear voltage waveforms under the desired accuracy requirements.

5.1. MOS Electrical Models and Timestep Selection of SWEC

sistor is given by the conventional formula: The analytical expression for the G(t) of a MOS tran-

G(t) = P * (2 * ( V G ~ - V d - VDS)Itr

if VGS - Fh L VDS L 0

if VDS > VGs - Vth 2 0

G(t) = 0.0,

if VGs e Fh (12) where Vth, the threshold voltage, is a function of VsB. Fig. 1 shows the electrical model of a MOS transistor. Be- tween the drain node and the source node there is a time- varying conductor with the conductance G(t) . The voltage at the gate node is represented by the voltage sources VG,. The grounded capacitors, CD and C,, represent the side-wall and bottom junction grounded capacitances at the drain and the source nodes, respectively. CG is the gate-oxide capacitance and wiring capacitance. CGD and CGs represent the gate-to-drain and gate-to-source overlap capacitances, respectively. Note that they are lumped with CG at the gate node GI as an approximate total capacitance

looking at that node. Since in general CG is much larger than CGs or CGD, turning CGs or CGD into grounded capacitors is a reasonable simplification when looking at the gate node. However, this is not true when looking at the source or drain node because C, is comparable with CGD, and Cs is comparable with CGs. We account for this by introducing the two voltage sources VG, representing the effects coming from the gate node.

In this way, the determination of the gate voltage does not depend on the voltage at the source node or the voltage at the drain node as long as there is no other charge transfer path (resistor, capacitor, transistor channel) connected between them. Furthermore, if the gate voltage is evaluated prior to the evaluation of the voltages of the source node and the drain node, then VG, can be treated as a constant voltage source in determining the voltages of the source node and the drain node. If we can keep this ordering correct during the simulation, then solving the voltage at the gate node can be separated from solving them at the source and the drain nodes, and no iterations are needed between the two solving processes. Our event- driven approach is based on this idea and will be discussed in Section 5.3.

Since there is no direct charge transfer path between the gate node and the conducting channel of the transistor (one-way circuits), we are able to perform circuit parti- tioning [16]. Prior to simulation, the circuit is partitioned into subcircuits. They are tightly coupled groups of nodes connected by a charge transfer path. Each subcircuit is integrated with its own timestep to take advantage of the time latency (or multirate behavior) existing in the circuit. The integration of each subcircuit employs the stepwise equivalent conductance technique. For a subcircuit, the time steps are determined according to the slopes at inputs and the value of the equivalent conductance of each transistor before integration.

The conductance of each transistor used for the integration from r,, to r,, + h,, is S,, which is equal to G(t,)

676 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 5, MAY 1993

+ (h , , /2 )G( tn) . The expressions are as follows:

6, = 0.0,

if VGs < F h . (13) For the sake of efficiency, we neglect those terms as-

sociated with (d /d t ) Vth in deriving G ( t ) of (13). For the situation that VDs > VGs - Vth, the term associated with

a (VGS - Vth)2 VDS -

avDS VDS

is also neglected because after the differentiation, we will have the result

which is considered to be small due to VDs > VGs - Vth. In [l], we have demonstrated that, for a CMOS inverter, the term

is negligible compared with the rest terms of G ( t ) . By making use of the piecewise linearity and from (1 l ) ,

we find that the timestep selection of SWEC for each integration is

(14) where i is the index of the transistors which are ON a n d j is the index of nodes. The A V / $ ( t , ) term inside the min function comes directly from (1 IC); the other term function is due to the consideration of (1 lb). The G(&) of ( l l b ) can be derived from the differentiation of (12). Equation (1 la) is not considered in (14) because the node voltage waveform is piecewise linear. Hence the second derivative for any node voltage vanishes.

5.2. Piecewise-Linear Approximation of Waveforms After each integration of a subcircuit, a piecewise-lin-

ear approximation is applied to the output waveform of the subcircuit. This piecewise-linear waveform can then be fed to the fan-outs of the subcircuit as one of their in-

puts. Thus during the simulation, the input and the output waveforms of every subcircuit are piecewise linear. When scanning the data points of the original waveform, the piecewise-linear approximation tries to skip as many points as possible as long as those skipped points stay on an approximated linear segment. Those points which are not skipped are kept as the break points of the piecewise- linear curve. The break points of a piecewise-linear curve are the data points at which the curve changes slope.

To determine which points can be skipped, we have developed a local error criterion. The original waveform is assumed to be fed into a CMOS inverter as the input. The corresponding output waveform can be determined. Then the errors on the output of the inverter are monitored when piecewise-linear approximations are applied to the original waveform. The approximation algorithm searches for a piecewise-linear approximation of the original waveform with errors within a prespecified error bound and thus obtains as few breakpoints as necessary. The tighter the error bound, the more points of the original waveform will be left as breakpoints.

The details of the algorithm are as follows. For every point on the waveform, we calculate the worst possible relative error on the inverter’s output when the extrapo- lation from the two preceding data points is used, instead, as the input. As shown in Fig. 2 , ( t i , vi) is the point being considered currently and ( t i , 0;) is the extrapolating point from (ti - 2 , vi - 2) and (ti - vi - I ) at ti. We check all the possible errors’ on the inverter’s output at ti when the line segment from (ti - I , vi - I ) to ( t i , 0) is used as the input. If the worst relative error violates a given local error bound, then the immediately preceding point, which is (ti - in Fig. 2, should be kept as a break point. If not, the immediately preceding point can be skipped. When the local error criterion is violated, the waveform has a relatively large slope change around the immediately preceding point, and so it should be kept as a break point. The situation is shown pictorially in Fig. 2 .

Hence, the piecewise-linear approximation algorithm we developed for SWEC is based on examining every three consecutive samples, say (ti - 2 , vi-2), ( t i - vi - I ) , and (ti , vi): if,

vi -

then (ti - I , vi - 1) is kept as a breakpoint. Otherwise, (ti - vi - I ) is not a breakpoint. The next triplet to be examined is ( t i - , , ~ i - 1 ) ~ ( t i , v i ) , and ( t i + I , U i + l ) -

The E ’ is the constant controlling the tolerable percent- age errors. The number 2 in (15) is the average voltage value of VGs - Vth during a transition. The detailed derivation of (15) is given in [l].

In [l], an example is given. Seven breakpoints out of 228 data points of the glitch output of a NAND gate were

’Since the inverter can be in different operating regions and the effect of the approximation on its input may be different, we need to consider all the possible situations.

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LIN et al.: STEPWISE EQUIVALENT CONDUCTANCE SIMULATION

subcircuit A subcircuit B

Fig. 3. A circuit with a feedback loop.

611

Fig. 2. Piecewise-linear waveform approximation.

picked by our algorithm. Then, the piecewise-linear waveform was fed into an inverter. Again, eight breakpoints out of 169 data points were picked from the output of the inverter. Both piecewise-linear waveforms show a very good match with the SPICE results,

5.3. The Event-Driven Approach of SWEC SWEC uses an event-driven mechanism to handle feed-

back loops in large circuits and further exploit the latency of MOS circuits. The time instants at which each individ- ual subcircuit is to be evaluated are termed event times for the subcircuit. Thus an event is a prediction of the time when integration should take place for the time step between the previous event time and the current even time. Events are predicted, stored, and scheduled on an event queue as in [lo], [8], [3]. The prediction is based on the information at the input slopes and the conductances of MOS transistors in the subcircuit given by (14). After the integration of a subcircuit, the slope of its output may or may not change according to the piecewise-linear waveform approximation introduced in Section 5.2. If the slope changes, then the events associated with its fan-out subcircuits will be incorrect because they were based on the previous slope. It is thus necessary to delete existing events for the fan-outs and reschedule them by using the new slope for (14). The whole simulation can be viewed as a series of event processes. Processing the event at the head of the queue involves the following steps:

Integrate the subcircuit for the timestep between the subcircuit’s previous event time and the current time. Use the piecewise-linear waveform approximation to check if the output slope has changed; if yes, delete the events of all the fan-outs and reschedule them. Calculate the timestep of the subcircuit and insert an event associated with the subcircuit into the queue with the event time being equal to the sum of the event time and the timestep.

The procedure works for circuits with feedback loops, which can be justified as follows. Let us consider the circuit given in Fig. 3, which has two subcircuits, A and B, and a feedback loop. The output of A, called x, is fed to B and the output of B, called y, is fed back to A . The next

event time (or the next integrating time point) of A is determined by choosing the minimum of the two predictions (timestep criterion) :

when x will change slope, when the voltage change of any node in A goes beyond a AV.

The derivation of the h, given in (14) satisfies the above criterion for small AV and E [ 11. Therefore, for the integration of A, say from t,, to t,, + I , the slope of x will not change, which guarantees that y is correct from t, to t, +

This implies that the integration result for x is correct because y is as predicted. Even though, after the integration, x may change slope beyond t, + I , causing y to change slope, the correctness of the results up to t, + still holds. By induction, the results of our approach are correct for the entire simulation.

The h, satisfying the criterion given above for circuits with feedback loops will be greater than zero because of the time latency in the circuits. The output slope of a subcircuit does not change immediately after any of its input changes slope. However, it is possible that a negative feedback loop will have very small or even zero time latency. In the negative feedback case, the subcircuits along the loop should be collapsed into one bigger subcircuit as done in the waveform-relaxation approach. The collaps- ing steps will not happen very often for digital circuits because the feedback loops inside digital circuits, such as those for flip-flop latches, are usually positive.

Event rescheduling using conventional means based on voltage level [lo], [5] is computationally expensive. In SWEC the overhead is very small because the waveforms are assumed to be piecewise linear. A subcircuit’s fan- outs need to be rescheduled only when its output waveform changes slopes. Since the piecewise-linear output waveforms of digital MOS circuits seldom change slopes, relatively few reschedulings are necessary. If the output waveform from a subcircuit is a straight-line segment, then no event rescheduling will be needed for all its fan- out subcircuits because the first prediction on the output waveform is true for all the time instances. Additionally, to avoid large computational overhead in even rescheduling, SWEC uses a very simple mechanism for calculat- ing the updated event time. Only the second term inside the min of (14) needs to be reevaluated.

VI. EXPERIMENTAL RESULTS FOR SWEC We compared the performance of SWEC with the sim-

ulators SPICE, SPECSZ, iSPLICE3.0, XPsim, and Relax2.3. Note that SPECS2 and XPsim use the explicit

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 5, MAY 1993

integration approach. The others use the implicit integration approach. The current version of SWEC uses the SPICE level one process technology. To make fair com- parisons, we used the same device models and the same capacitance models for all the simulators. Unless otherwise mentioned, all the simulations are performed on a DEC station 5O00.

6.1. Ring Oscillator with Seven Inverters The first test circuit was a ring oscillator made of an

inverter chain of seven inverters. The summary of accuracy and CPU times is listed in Table I. The Period column lists the period of the waveform obtained from each simulator. The % error refers to that compared with the SPICE results. We did not observe any oscillation on the result of XPsim, so we put 100% error for XPsim on the table.

6.2. 8-bit Ripple Carry Adder We built an 8-bit ripple carry adder with about 442

MOS transistors. We applied eight different input vectors and monitored the carry-out waveform of the adder. In the worst case, the carry would propagate from the carry-in through the whole adder to the carry out. In this way, the errors would be accumulated so we would tell the accuracy of each simulator. The waveforms from the simulators are depicted on Fig. 4. The solid line is the result of SPICE, which is assumed to be the correct result. We found that the results of SWEC, XPsim, iSPLICE and Relax2.3 completely overlapped the SPICE result. The result of SPECS2 had a slight error as shown. Table I1 lists the summary of the CPU times.

6.3. 1 &bit Multiplier We simulated a 16-bit multiplier with about 7200 tran-

sistors using 12 input vectors on all the simulators. Part of the multiplier was made of pass gate logic, which means certain subcircuits would have quite a few transistors. The largest subcircuit has 24 transistors and 10 nodes. Since SPICE, Relax, and SPICE cannot solve the dc solution of the circuit, ramping-up power inputs were used. Fig. 5 shows the waveforms of the 32nd bit output (the most significant bit) from different simulators. The total simulation time was 600 ns; however, to magnify the details, only part of the simulation results are shown in Fig. 5 . We found that the results from Relax2.3, SPECS, and XPsim showed discrepancies from SPICE'S result. The SPICE result convinced us that SWEC was correct. We did not do the whole simulation on SPICE. The simulation terminated at the 100 ns. The CPU time for this simulation was 8800 s. The simulation for SPECS2 was performed on an IBM RS/6000. The corresponding CPU time was measured on the IBM RS/6000, which is about 2.0 times faster than DEC stations 50oO. Table I11 gives the summary of the CPU times.

TABLE I CPU TIMES FOR RING OSCILLATOR

Simulator CPU Time Period % Error

SPICE 470 s 4.52 ns 0% SWEC 0.6 s 4.52 ns 0% iSPLICE3.0 1.7 s 4.52 ns 0% Relax2.3 1.2 s 4 .52 ns 0% SPECS2 1.7 s 4 .35 ns 3.1% XPsim 1.8 s OD ns 100%

carry out Vah

-r -mUim-J-

WE----- w- -. w!FH-- m---

-

TABLE I1

CARRY ADDER CPU TIMES FOR S-BIT RIPPLE

Simulator CPU Time

SPICE 174 s SWEC 5 .6 s iSPLICE3.0 82.6 s Relax2.3 11.8 s SPECS2 159 s XPsim 141 s

- V* 32nd bit 0

s.m

4 3

4.00

3 3

311)

ZYI

ua

I 3

1 .m

0 3

am

-3 sksaxprim

Fig. 5 . 16-bit multiplier.


sn

s.m

stiff circuit TABLE I11

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ , - $ -

CPU TIMES FOR BIT MULTIPLIER

c _ _ _ _ _

Simulator CPU Time

SPICE 8800 s SWEC 146 s iSPLICE3.0 39 990 s Relax2.3 179 s XPsim 2165 s SPECS2 1092 s

6.4. A S t i f Circuit To evaluate the stiff stability, we simulated a stiff cir-

cuit on all simulators. The circuit was an output pad with 14 transistors and 8 very small resistors, each connected with very small node capacitors. The time constants associated with those resistors were about two to three or- ders smaller than the input rise or fall time. The waveforms from the simulators are depicted on Fig. 6. Table IV summarizes the CPU times.

Since SWEC is absolutely stable, the timestep selection for SWEC is based on the accuracy consideration alone. From the simulation results, we found that SWEC was indeed both accurate and efficient. The 0.2-s CPU time is the minimum computation for SWEC which is used to build the look-up table for device evaluation routines. We did not observe the expected numerical blow-ups in the results of SPECS2 and XPsim. We believed that the minimum time steps were used for most of the simulation to assure stability. In fact, the CPU times were more than one order of magnitude larger than the other implicit methods.

VII. CONCLUSIONS AND FUTURE WORK Accuracy, stability, and efficiency are the three major

issues in circuit simulation. Previously, stability was often traded for efficiency, which led to the unpredictable behavior. For this reason, SPICE and ASTAP remain the only simulators trusted in industry. In this paper, we pre- sented a new circuit simulation technique. To simulate a nonlinear circuit using an implicit multistep integration, we manage to achieve the same order of accuracy with the amount of computation required to simulate a linear circuit. The technique is proved to be consistent, stable, and convergent. We introduce a CMOS VLSI timing simulator, SWEC, which is based on the proposed technique. When focusing on digital CMOS circuits, we demonstrate that additional speedups can be achieved by the use of a specific event-driven approach to take advantage of the piecewise-linear waveforms. Our experimental results confirm that the techniques are very efficient, stable, and accurate.

In the future, we plan to expand SWEC to include lossy transmission lines. Preliminary results were given in [ 131 and [14]. We believe that the stepwise equivalent conductance circuit simulation technique can make multichip module simulation feasible.

TABLE IV CPU TIMES FOR A STIFF CIRCUIT

Simulator CPU Time

SPICE 2.02 s SWEC 0.2 s iSPLICE3.0 0.8 s Relax2.3 0.5 s SPECS2 2 . 3 s XPsim 5.1 s

APPENDIX A CIRCUITS WITH INDUCTORS, NONLINEAR CAPACITORS

AND NONLINEAR INDUCTORS If there are linear inductors in the simulated circuit, we

can use either the state equations or the modified nodal approach [ 181. For the latter the circuit equation will be of the form below

(16) 3 ( X ( t ) ) + HX(t) = I&). Equation (16) is composed of the nodal equation for

each node, which is the (1) mentioned earlier, and the inductor equation for each inductor, which specifies that the voltage drop across the inductor is equal to the in- ductance of the inductor times the time derivative of the current through the inductor. The variable X is composed of the node voltages and the currents through the inductors.

Equation (16) can also be transformed into a linear time- varying circuit equation

(17)

A(?) is composed of the instantaneous equivalent conductance matrix at time t and submatrices with their entries being equal to 1, 0, or - 1 to specify the inductor equations. A (t) satisfies the relation below:

A(t )X( t ) + HX(t) = I,(t).

A ( t ) X ( t ) = %(X( t ) ) . (18)

Equation (17) is of the same form as (2). Therefore, all the discussions regarding (2) in this paper can directly be

I

680 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 5 , MAY 1993

extended to (17). The sufficient condition of the exactness of the transformation from (16) to (17) is that 9 is continuously differentiable.

If there are nonlinear capacitors or nonlinear inductors in the simulated circuit, then the charge of each nonlinear capacitor or the flux of each nonlinear inductor can be thought of as a time-varying function. The charges or the fluxes will also be considered as variables. Their time derivatives will be either the branch currents through the nonlinear capacitors or the voltage differences across the nonlinear inductors. The circuit equations will still be of the same form as (2). Therefore, the discussions in this paper can also be extended to cover these kinds of circuits.

APPENDIX B APPROXIMATION ERROR

In this appendix, the numerical error introduced from t,, to f , , + I by using the solution of (8) as the approximated solution of (2) will be derived. Let us denote this approximation error 7,. Then, the local truncation error for the integration of (2) from tn to f , , + I will be the sum of 7, and the error introduced by the integration scheme that we use to integrate (8) for the time step.

Let us rewrite (2) below:

G(t) V( t ) + CV(t) = Z,(t). (19)

The G(t ) can be expanded into Taylor series around the Given V(t,,), we are trying to solve for V(t,,+ I ) of (19).

neighborhood of t,,:

(G(t,,) + G(t,,)(t - t,,) + ;G(t,,)* + * - e ) V( t )

+ CV(t) = I&). (20) Let us consider the first two terms of the Taylor series,

(G(t,,) + G(t,,)(t - t,,)) V ' ( t ) + CV'(t) = Z,(t) (21) with V' (t,,) = V(t,,). Then, V' (t,, + I ) will be the approximated solution of V(t,, + I ) . We use a column vector T A to denote the errors, i.e., 7; = V ( t , + , ) - V'(t,,+ J .

To solve V'(t,, + I ) of (21), we further approximate (21) by the following equation:

(22) with 6 = G(t,,) + (h,/2) G(t,,), where h, = tn + I - t,, and V"(tn) = V'(t , ,) = V(t,,). V"(t , ,+ I ) is then the approximated solution of V'(t,, + I ) , and let us denote the errors due to this by 7; = V'(t , ,+ I ) - V"(tn + I ) .

SV"(t ) + CV" (t) = Z,(t)

Then, 7" = 71, + T i . (23)

B. I . The Analysis of 7; The solutions for V ' ( t ) for (21) are composed of two

parts: one is the homogeneous solution with Z,(t) = 0, denoted by Vf(t), and the other is the zero initial state solution, denoted by V & ( t ) , where V&(t,,) = 0. There- fore, V'( t ) = Vf(t) + V & ( t ) . Similarly, V " ( t ) , V " ( t ) = Vfl(t) + V $ ( t ) .

By setting Zs(t ) = 0 in (21), we get

(G(t,,) + G(t,,)(t - t,,)) Vf(t) + CVf ( t ) = 0 (24) Equation (24) can be solved exactly with the solution:

Vf(r) = exp ( -C- ' (G( t , ) ( t - t,) + ~ G ( r , , ) ( r - tJ2)V0

(25) where Vo = Vf (t,,) = V: (f , , ) . Hence,

Vf(t,,+l) = exp (C-'(G(t, ,)h, + iG(t , , )hi))Vo. (26)

On the other hand, by setting Z,(t) = 0 in (22), we get

(27) Vf ' ( t ) = exp (-c-'S(t - t,,))Vo.

Vf l ( t , ,+ , ) = exp (-C-IS~,)VO. (28)

Hence,

By using the fact S = G(t,) + (h,,/2)G(rn), we have Vf (t,, + I ) = Vfl (t,, + I). Therefore, T : is not caused by the zero input solution part.

Let us next look at the situation with Vo = 0. By subtracting (22) from (21), we get

G(t,)(V&(t) - V $ ( t ) ) + C(V&(t) - V c ( t ) )

= G(tJ - V $ ( t ) - ( t - t")V&(t) , ("; ) or

G(t,,)e(t) + Ce(t)

= &(f,,) V $ ( t ) - ( t - r,,)V&(r)) (29)

where e( t ) = V & ( t ) - VZ(t). V&( t ) and V $ ( t ) on the right-hand side of (29) can be

expanded into Taylor series around t,,. By neglecting the higher order terms and by using the fact V&(t,,) = V$(t,,) = 0, we have

C(t,,)e(t) + Ce(t)

(:

) = G(tJ (2 ( t - t,) VZ(t,,) - ( t - t,,)2V&(tn) .

(30) By replacing t of (21) with t,,, we get V&(t,,) =

C-'Z,(t,,) because V&(t ) is the solution of (21) with V&(t,,) = 0. Similarly, by replacing the t of (22) with tn, we get V$(t,,) = C-lZs(r,,). Hence, V&(t,,) = V$( f , , ) . Note, C-'Z,(f,,) = C-'G( t , , ) V(t,,) + V(t,). We can use either expression for V&(t,,) depending on which information is available.

G(t,,)e(t) + Ce(t)

Therefore,

( t - t,,) - ( t - Q2

I

LIN et al.: STEPWISE EQUIVALENT CONDUCTANCE SIMULATION 68 I

We can use the Laplace transform method to solve for e (r, +

e(r,+ 1)

which is given by the convolution integral,

tn + ha

= 1 exp (C-'G(r,)(r, + h, - s)) "

C-'G(f,)C-'Zs(t,) "(s - t,) - (S - tJ2 ds.

(32) Since h is small, C-' G(t,) (r, + h - s) is approxi-

mately a zero matrix, during the integral interval, exp ( -C- 'G( t , ) ( t , + h - s)) = 1, the identity matrix. Therefore,

(", )

tn + hn

e ( t , + h,) =

- ($ (s - r,) - (s - rJ2 ds ) = c-'G(r,)C-'zs(r,) - . (33) (I$)

Because 7: = e(t, + h,),

(2) 7: = c-I G(r,)c-'z$(r,)

or

7: = c-I G(r,)(c-' G(r,) V(f,) + V ( r , ) ) (2). (34)

B.2. The Analysis of 71,

Subtracting (21) from (20), we get:

(G(r,) + G(r,) (r - r,)) e' (r) + Ce' (r)

= -(iG(r,)(r - rJ2 + * - .)V(r) (35) where e'(r) = V(r) - V ' (r), and e' (r,) = 0. e' (r) represents the error introduced by using V' (r) as the solution of V(r). We next solve for e' (r, + h,).

Equation (35) is of the form of (21) with Z,(r) equal to

-(iG(r,)(r - r,)2 + - - ) V(r). (36) As mentioned in Section B. 1, we can solve the equations below :

se" (r) + cetf (r) = -($(r,) (r - r,)2 + * V(r)

(37) with s = G(t,) + (hn/2)G(r,) = e"(r,) = 0, and use e" (r, + h,) as the approximated solution for e' (r, + h,). This approximation will introduce a 7* type of error as explained in Section B. 1. However, when we calculate (36) with t = t,, we have zero currents. This means that e; (r,) = e$ (r,) = 0 because both are equal to C - ' I, (r,). Therefore, we need to consider the second-order terms for

the Taylor expansions of e'.@) and e" (t), respectively. In this way, we will have G(r,)(h,/2(r - r,)2#$(r,) - (r,J3#&(r,)) on the right-hand side of (30). Since the power of (t - t,) is one more than that of (30), we get the 7 2

type of error by using e" (r, + I ) as e' (r, + is of the order of o(h4), which is much smaller than the 7 2 derived previously. In fact, later in this subappendix, we will show 7; is also of o(h3), so we can neglect the o(h4) errors. Therefore, we will assume that no error is introduced by using e" (r, + as e' (t, + 1).

From Taylor's expansion of V(t) in (37) around r, and neglecting the higher order terms, we have

se" (r) + Ce" (r) = - - (' - rn)2 G(r,) V(r,). (38)

Again, we can use the Laplace transform method to solve for e" (r, + '), which is

e"@, + h)

2

tn + h

= 1 exp(-C-Is(t , , + h - s)) I

- c-I e@,) V(r,) (- q) ds. (39)

Since h, is a very small number, during the integral interval, exp (-C-I s (r, + h - s)) = 1. Therefore,

(s - a2 ds e(r, + h) = n c-'e(r,)V(r,) (- T)

Hence,

71, = c-'%(r,)v(r,) (-:) - Combining the 7: derived previously, we have

7, = 71, + 7:

APPENDIX C APPROXIMATION ERROR UNDER TIMESTEP

CONSTRAINTS In this appendix, the upper bound on the infinity norm

of (9) under the constraints of h, on (1 1) is derived. The infinity norm of a column vector is the largest absolute value of the entries of the vector. Since the column vector of (9) represents the approximation errors on the node voltages, the infinity norm of (9) can give the measure of the error introduced.

To make the notations simple, we follow the notations

682 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 12, NO. 5, MAY 1993

used in the previous appendix. The column vector of (9) is denoted by 7,, which is equal to 7: + 7:. We will first derive the upper bound on 11 7111 under (1 l) , and then the upperboundon 117i11 under(l1). Then, 1 1 ~ ~ 1 1 I 1 1 ~ : 1 1 . We will show that the upper bound on 117.11 is approximately ( E / ~ ) A V .

For the purpose of the derivation, the following two theorems have been developed.

Theorem 2: If

then

Proofi

1 =

and G(t,) is

(lzl) I E V device i, (43)

represents the largest diagonal element of where d,,, C(t ,) . Note that

0 Theorem 3: If (lsl) I E V device i (49)

then

II (h, G(t,N G (t,) - I II 5 E . (50)

The proof for Theorem 3 is similar to that of Theorem 2 , so the details are omitted.

(:) I1 = I/ C-'G(t,)G(t,)-'G(t,) V(t,)

(:)I- = ( 1 G(t,,)G(t,)-' C-' G(t,) V(t,)

Since the matrix C is diagonally dominant and so is C-', the error introduced on the norm by commuting C-' is

small. Note that if C is a diagonal matrix, then the commutation of C-' in (51) will not introduce any approximation.

Under the constraints of (1 l ) , we have

I :AV. 6

In (52) , we use the approximation IIV(t,)II = \ ~C- lG( f f l )V( f f l )~~ . If in ( 2 ) l s (r , , ) = 0, then there will be no approximation introduced. For the case where Z, (t,) # 0, if AV is very small, the approximation incurred will be very small.

On the other hand,

= 11 C-'G( t , )G( t , ) - 'G( t , ) (h ,C- lG( t , )V( t , )

= I/ G k ) c(t,)-' c - I G(t,) (h, c - I G(t,) V(t,)

(53)

Again, the approximate commutation of the matrix C-' is used in (53).

Under the constraints of (1 l ) , we have,


[I21 D. Overhauser and I. Hajj, “IDSIM2: An environment for mixed- mode simulation,” in Proc. IEEE Custom Integrated Circuits Conf., PP. 5.2 .1-5 .2 .4 , 1990.

[I31 Shen Lin and Ernest Kuh, “Transient simulation of lossy intercon- nect,” in Proc. 29th Design Automation Conf., pp. 81-86, June 1992.

1141 -, “Transient simulation of lossy interconnects based on the re- ~~

cursive convolution formulation,” IEEE Trans. Circuits Sysr., vol. 39, Nov. 1992.

1151 P. Debefve, H. Y. Hsieh, and A. E. Ruehli, “Wave convergence - - algorithms for the waveform relaxation method,” in IEEE Proc.

1161 J . White and A. Sanaiovanni-Vincentelli, Relaxation Techniques for ICCAD, pp. 33-35, NOV. 1984.

.~ the Simulation of Vis1 circuits. 1987.

Boston, MA: Kluwer Academic,

Boston, MA: 1171 R. Saleh and A. R. Newton, Mixed-Mode Simulation.

AV I E - .

6 (54)

In (54), the approximation IIV(t,)l( = \lC-’G(t,) V(t,)II is used again. For the last two lines of (54), the reason why ~ ~ h , , C - ‘ G ( t , ) ~ ~ e(AV/6) I 6(AV/6 ) is because llh,C-’G(t,>ll I 1, which is the basic requirement for the integration timestep h,, otherwise h, can not be kept to the first-order accuracy.

Combining (54) and (52),

117,Il 5 117!I11 + 11~;11

Shen wise

AV AV I€-+€-

6 6 AV -

-7- REFERENCES

Lin, M. Marek-Sadowska, and Ernest Kuh, equivalent conductance timing simulator for

“SWEC: CMOS VI

(55)

A step -SI cir-

cuits,”-in Proc. EDAC, pp. 142-148, Feb. 1991. 121 R. L. Baner, J. Fang, A. Ng, and R. K. Brayton, “XPsim: A MOS

VLSI simulator,” in IEEE Proc. ICCAD, pp. 66-69, 1988. [3] C. Visweswariah and R. A. Rohrer, “Piecewise approximate circuit

simulation, IEEE Trans. Computer-Aided Design, vol. 10, pp. 861- 870, 1991.

[4] A. R . Newton and A. Sangiovanni-Vincentelli, “Relaxation based electrical simulation,” IEEE Trans. Computer-Aided Design, vol.

[5] R. A. Saleh and A. R. Newton, “The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1286-1298, Dec. 1989.

[6] E. Lelarasmee and A. E. Ruehli and A. Sangiovanni-Vincentelli, “The waveform relaxation method for the time-domain analysis of large scale integrated circuits,” IEEE Trans. Computer-Aided De- sign, vol. CAD-l, pp. 131-145, July 1982.

[7] 1. White and A. Sangiovanni-Vincentelli, “Relax2.1: A waveform relaxation based circuit simulation program,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 232-236, 1984.

[SI Y. H. Kim, S. H. Hwang, and A. R. Newton, “Electrical-logic simulation and its application,” IEEE Trans. Computer-Aided Design, pp. 8-22, Jan. 1989.

191 B. R. Chawla, H. K. Gummel, and P. Kozak, “MOTIS-An MOS timing simulator,” IEEE Trans. Circuits Syst., vol. 22, pp. 901- 910, 1975.

[ lo] B. D. Ackland and R. Clark, “Event-EMU: An event-driven timing simulator for MOS VLSI circuit,’’ in IEEE Proc. ICCAD, pp. 80- 83, 1989.

[ I l l J . K. Ousterhout, “A switch-level timing verifier for digital MOS VLSI,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 336- 349, July 1985.

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~- Kluwer Academic, 1990.

[I81 J. Vlach and K. Singhal, “Computer methods for circuit analysis and design,” Van Nostrand Reinhold electrical/computer science and eng. Ser. Sec. 4.4, 1983.

Shen Lin (S’89-M’91) received the B.S. degree in electrical engineering from National Taiwan University in 1985, and the M.S. degree and the Ph.D. degree, both in electrical engineering and computer sciences, from the University of Cali- fornia, Berkeley, in 1989 and 1992, respectively.

He is a research staff member at the IBM T. J. Watson Research Center. His research interests include different aspects of CAD and VLSI, with emphasis in circuit simulation and physical design.

Mr. Lin received a Best Paper Award at the fifth international conference on VLSI design, Bangalore, India, in 1992.

Ernest S. Kuh (S’49-A’52-M’57-F’65) received the B.S. degree from the University of Michigan, Ann Arbor, in 1949, the S.M. degree from the Massachusetts Institute of Technology, Cam- bridge, in 1950, and the Ph.D. degree from Stan- ford University, Stanford, in 1952.

Ernest S. Kuh is the William S. Floyd, Jr., Pro- fessor in Engineering of the Department of Elec- trical Engineering at the University of California, Berkeley. He joined the EECS Department faculty in 1956. From 1968 to 1972 he served as chair of

the department; from 1973 to 1980 he served as Dean of the College of Engineering. From 1952 to 1956 he was a member of the Technical Staff at Bell Telephone Laboratories in Murray Hill, New Jersey.

Dr. Kuh is a member of AAAS, the National Academy of Engineering, the Academia Sinica, and Honorary Professor of the Shanghai Jiao Tong University, Tsinghua University, and Tianjin University. He has received a number of awards and honors, including: NSF Senior Postdoctoral Fel- low (1962), Miller Research Professor (1965-66), University of Michigan Distinguished Alumnus Award (1970), IEEE Guillemin-Cauer Award (1973), Alexander von Humboldt Senior Scientist Award (1977), IEEE Ed- ucation Medal (1981), the Lamme Award of the American Society for En- gineering Education (1981), the Japan Society for Promotion of Science Award (1981), the British Science and Engineering Research Fellowship (1982). the IEEE Centennial Medal (1984), the IEEE Circuits and Systems Society Award (1988). and the Society of Hong Kong Scholars Award (1990).

Malgorzata Marek-Sadowska (M’87) received the M.S. degree in applied mathematics in 1971 and the Ph.D. degree in electrical engineering in 1976 from the Technical University of Warsaw, Poland.

From 1976 to 1982 she was Assistant Professor at the Institute of Electron Technology at the Technical University of Warsaw. She was a Vis- iting Professor in the Electrical Engineering De- partment of the University of California at Berke- ley from 1979 to 1980. She became a Research

Engineer at the Electronics Research Laboratory in 1979 and continued there until 1990, when she joined the Department of Electrical and Com- puter Engineering at the University of California in Santa Barbara as a Professor.

I

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