Note: Within nine months of the publication of the mention of the grant of the European patent in the European PatentBulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with theImplementing Regulations. Notice of opposition shall not be deemed to have been filed until the opposition fee has beenpaid. (Art. 99(1) European Patent Convention).

Printed by Jouve, 75001 PARIS (FR)

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(12) EUROPEAN PATENT SPECIFICATION

(45) Date of publication and mention of the grant of the patent: 30.03.2016 Bulletin 2016/13

(21) Application number: 12162346.6

(22) Date of filing: 30.03.2012

(51) Int Cl.:H04B 1/00 (2006.01) H04H 40/18 (2008.01)

H04N 5/455 (2006.01) H04N 5/46 (2006.01)

(54) SOFTWARE DEFINED RADIO FOR UNIVERSAL MODULATION AND DEMODULATION OF DIGITAL AND ANALOG COMMUNICATION SYSTEMS

Softwaredefinierter Funk für Universalmodulation und -demodulation digitaler und analoger Kommunikationssysteme

Radio définie pour modulation et démodulation universelle de systèmes de communication numériques et analogiques

(84) Designated Contracting States: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30) Priority: 01.04.2011 IN CH11062011

(43) Date of publication of application: 03.10.2012 Bulletin 2012/40

(73) Proprietor: Saankhya Labs Private Limited560 043 Bangalore, Karnataka (IN)

(72) Inventors: • Naik, Parag

Bangalore-94 Karnataka (IN)• Saha, Anindya

560 017 Bangalore, Karnataka (IN)

• Mallapur, Hemant560 034 Bangalore, Karnataka (IN)

• Ramesh, Sunil Hosur560 092 Bangalore, Karnataka (IN)

• Padaki, Gururaj560 097 Bangalore, Karnataka (IN)

• Kayergadde, VishwakumaraBangalore 560024 (IN)

(74) Representative: D Young & Co LLP120 HolbornLondon EC1N 2DY (GB)

(56) References cited: JP-A- 2005 167 737 US-A1- 2007 174 875US-A1- 2009 274 202 US-A1- 2010 075 611

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Description

BACKGROUND

Technical Field

[0001] The embodiments herein generally relate tomodulation, demodulation, and trans-modulation of aninput signal, and, more particularly, to a software definedradio subsystem that is capable of supporting modula-tion, demodulation and trans-modulation for multiple an-alog and digital communication standards.

Description of the Related Art

[0002] Typical demodulator solutions today which ca-ter to communication standards such as Digital TV (DTV)standards and/or Analog TV (ATV) standards consist ofseparate pieces of digital signal processing hardwareblocks which are standard specific. With the proliferationof medium specific and region specific communicationstandards, supporting all standards on a single chassisis becoming necessary to reduce the diversity cost ofmaintaining different production lines for different stand-ards. If one were to make a system solution using differ-ent region and medium specific demodulators, the bill ofmaterials cost would be very high for end customers. Theprocess of developing a single chip to address such di-versity using system on chip integration of signalprocessing hardware blocks leads to very large siliconarea thus leading to prohibitively higher costs.[0003] In addition, supporting such a multitude ofstandards using a single programmable processor wouldnecessitate operating it at an extremely high frequency(e.g., several tens of Gigahertz) which would consumeextremely high power thus making it unviable for con-sumer usage. Hence there is a need to develop a solutionwhich is area inexpensive, that consumes lower power,and that also caters to a multitude of both digital andanalog communication standards. Also, RF tuners whichinterface with various TV demodulators operate at vari-ous intermediate frequencies (IF), like a standard IF (36MHz or 44 MHz), a low IF (4-4.5MHz) or a zero IF. Thisalso requires different signal processing hardware blocksbased on the IF type. Hence additional area and powerwould have been incurred if multiple tuners catering tovarious standards have to be supported on the samechip.[0004] Further, DTV and ATV systems found in themarket today are extremely inflexible. They cannot sup-port field upgradeability, additional support of a non-im-plemented standard, or even support a new feature foran existing standard without mandating a device rede-sign. With more new DTV standards evolving today, suchplatforms would need to be redesigned from scratch, dueto which a market opportunity window would be lost.There have been attempts made to address these re-quirements individually. One such approach to address

the issue of demodulators interfacing to multiple types oftuners (e.g. standard IF, low IF and zero IF) is to buildDSP hardware which is standard specific.[0005] For interfacing to zero-IF tuners, typically twoseparate sampling paths obtained from an IQ ADC (An-alog to Digital Converter) are required whereas for inter-facing to a standard IF or a low IF tuner only one samplingpath is required. Some implementations which can utilizea shared hardware for two standards can be envisioned,but they are not capable of handling more digital TVstandards (ATSC,DVB-T,DVB-S,J.83A.J.83B,J.83C,IS-DB-T,CDMB-T) and analog TV standards (NSTC,SE-CAM and PAL). One such architecture tries to performsymbol processing tasks on a DSP processor and signalconditioning stages like filtering and spectrum shapingin beginning stages within an optimized hardware accel-erator. However, due to this, it is impossible for the ar-chitecture to interface to different tuners with differingintermediate frequencies.[0006] In addition, a requirement for supporting differ-ent intermediate frequencies (e.g., 4.5 MHz, 36 MHz, and44 MHz) and different types of tuners (e.g., a CAN tuner,a silicon tuner) requires multiple hardware signalprocessing chains working in parallel. Such a solutionwould inevitably be area expensive thus increasing costof the demodulator. FIG. 1 illustrates a typical AdvancedTelevision Systems Committee (ATSC) demodulationsignal chain 100. The ATSC demodulation signal chain100 includes (i) a Numerically Controlled Oscillator(NCO) 102, (ii) a pilot frequency estimation stage 104,(iii) an adjacent channel filter 106, (iv) an upsamplingfilter 108, (v) a sample rate convertor & matched filter110, (vi) a band extraction stage 112, (vii) a samplingfrequency offset estimation stage 114, (viii) a carrier re-covery stage 116, (ix) a pilot removal stage 118, (x) asegment sync & frame sync detection stage 120, (xi) aLeast Mean Square (LMS) equalizer 122, (xii) an innerdeinterleaver stage 124, (xiii) a trellis decoding stage126, (xiv) an outer deinterleaver 128, and (xv) a Reed-Solomon (RS) decoder & de-randomizer stage 130.[0007] FIG. 2 illustrates a typical cable demodulation(J.83A and J.83C) signal chain 200. The cable demod-ulation (J.83A and J.83C) signal chain 200 includes aNumerically-Controlled Oscillator (NCO) 202, a down-sampling filter 204, an adjacent channel filter 206, anupsampling filter 208, an interpolation filter 210, a timingrecovery stage 212, a coarse carrier recovery stage 214,a Least Mean Square (LMS) equalizer 216, a de-mapper218, a frame sync detection stage 220, an outer deinter-leaver 222, and a Reed-Solomon (RS) decoder & de-randomizer stage 224.[0008] FIG. 3 illustrates a typical cable demodulation(J.83B) chain 300. The cable demodulation (J.83B) chain300 includes a Numerically Controlled Oscillator (NCO)302, a down-sampling filter 304, an adjacent channel fil-ter 306, an upsampling filter 308, an interpolation filter310, a timing recovery stage 312, a coarse carrier recov-ery stage 314, a Least Mean Square (LMS) equalizer

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316, a trellis decoding stage 318, a frame sync detectionstage 320, an outer deinterleaver 322, and a Reed-Solo-mon (RS) decoder & de-randomizer 324.[0009] FIG. 4A illustrates a typical Digital Video Broad-casting - Terrestrial (DVB-T) demodulator chain 400Athat includes a Numerically Controlled Oscillator (NCO)402, an IF to baseband conversion stage 404, a down-sampling filter 406, an adjacent channel filter 408, aninterpolation filter 410, a time domain synchronizationstage 412, a Fast Fourier Transform (FFT) stage 414, afrequency domain synchronization stage 416, a pilotprocessing stage 418, a channel estimation stage 420,a fine symbol synchronization stage 422, a frame syncdetection stage 424, a channel correction and de-mapperstage 426, a bit deinterleaver stage 428, a viterbi decod-ing stage 430, an outer deinterleaver 432, and a Reed-Solomon (RS) decoder & de-randomizer stage 434.[0010] FIG. 4B illustrates a typical Digital Video Broad-casting - Satellite (DVB-S) demodulation chain 400B thatincludes a numerically-controlled oscillator (NCO) 402,a down-sampling filter 406, an adjacent channel filter408, an upsampling filter 436, an interpolation filter 410,a timing recovery stage 438, a coarse carrier recoverystage 440, a data selection & discard stage 442, an innerdeinterleaver stage 444, a trellis decoding stage 446, aframe sync detection stage 424, an outer deinterleaver432, and a Reed-Solomon (RS) decoder & de-randomiz-er stage 434.[0011] FIG. 5 illustrates a typical Integrated ServicesDigital Broadcasting-Terrestrial(ISDB-T) demodulatorchain 500 that includes (i) a Numerically Controlled Os-cillator (NCO) 502, (ii) an IF to baseband conversionstage 504, (iii) a down-sampling filter 506, (iv) an adjacentchannel filter 508, (v) an interpolation filter 510, (vi) a timedomain synchronization stage 512, (vii) a Fast FourierTransform (FFT) stage 514, (viii) a frequency domainsynchronization stage 516, (ix) a Transmission and Mul-tiplexing Configuration Control (TMCC) decoding stage518, (x) a frequency and time domain deinterleaver 520,(xi) a channel estimation stage 522, (xii) a hierarchicalmultiplexer stage 524, (xiii) a channel correction and de-mapper stage 526, (xiv) a bit deinterleaver stage 528,(xv) a viterbi decoding stage 530, (xvi) an outer deinter-leaver stage 532, and (xvii) a Reed-Solomon (RS) de-coder & de-randomizer stage 534.[0012] FIG. 6 illustrates a typical analog TV signal de-modulation chain 600 for the analog TV standards PhaseAlternating Line (PAL), National Television System Com-mittee (NTSC) or Sequential Couleur Avec Memoire (SE-CAM). The analog TV signal demodulation chain 600 in-cludes (i) a Numerically Controlled Oscillator (NCO) 602,(ii) a carrier recovery stage 604, (iii) an image rejectionand down sampler stage 606, (iv) an adjacent channelnyquist filter 608, (v) a video low pass filter 610, (vi) agroup delay equalization filter 612, (vii) a DC and gainadjust stage 614, (viii) an upsampling filter 616A, (viii) anupsampling filter 616B, and (ix) an audio band pass filter618. The signal chains of FIGS. 1 to 6 are typically im-

plemented either using hardwired architectures, generalpurpose DSPs or Application specific Signal processors(ASSP).[0013] Hardwired architectures are ideally suited forimplementing standard specific demodulation. Howeverthey are not flexible and cannot be reused as they aremore expensive. The hardwired architecture does notscale with addition of new features or standards. Receiv-ers perform complex signal processing algorithms thatneed to be adaptive. Any minor changes force an expen-sive silicon re-spin. Further, as the number of standardsto be supported increases, hardwired architectures needmore ’silicon real estate’. This results in higher recurringcosts. In addition, moving hardware implementationblocks across product lines is difficult and expensive. Ageneral purpose programmable DSP like the TI C6x canbe an alternative to the hardwired architectures. Howevera general purpose DSP is targeted for a wide range ofapplications like MPEG decoding, graphics and others.This leads to a solution that is prohibitively expensive forconsumer applications.[0014] The hardwired architectures and general pur-pose DSPs are two ends of the spectrum. The benefitsof both a hardwired architecture and a DSP can be metby an architecture based on Application Specific SignalProcessors (ASSP). These ASSPs are designed specif-ically to solve a class of signal processing problems inan application.[0015] FIG. 7 illustrates a cost 702 versus flexibility 704a curve 700 for different architectures such as an ASIC,a GPP (General Purpose Processor), a DSP (Digital Sig-nal Processor), and an ASSP (Application specific Signalprocessor). The cost versus flexibility curve 700 illus-trates that ASSPs are characterized by maximum flexi-bility at lowest cost.[0016] An alternative implementation of a demodulatorcan be envisioned by integrating standard specific de-modulators with separate paths in their receive signalprocessing chains. This could start from IntermediateFrequency (IF) processing which is done at sample rate,and end with demapping which is performed at a symbolrate, just before an inner and an outer decoding is per-formed. However such a demodulator that is constructedby integrating standard specific demodulators would bearea and cost expensive, and would also consume sig-nificantly more power. It is extremely difficult to create areusable-shared hardwired architecture to cater to all dig-ital and analog TV standards due to a multitude of rea-sons. One such reason is that the sampling rate of IFsignals obtained in various TV standards required for re-ceiving them with minimum adjacent channel interfer-ence is different for each of the standards. The frequen-cies may range from 25 MHz to 80 MHz.[0017] In addition, for zero IF tuners, there is additionalprocessing required for IQ imbalance correction, whichis absent in standard and low-IF tuners. Hence, it is im-possible to supporting all types of tuners for several In-termediate frequencies (IF) using shared resources,

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since several replicas of hardware for IF processingtuned to respective standards are required. Further,some standards are based on a single carrier (e.g. ATSC,single carrier mode of CDMB-T, NTSC, PAL and SE-CAM) while some others like DVB-T, DVB-S, ISDB-T,multicarrier mode of CDMB-T are based on multi-carriermodulation techniques like OFDM. While demodulationof multicarrier standards is typically done using blockbased techniques, single carrier standards cannot betreated in a similar way. This typically leads to two differ-ent philosophies of hardware design which are impossi-ble to merge and thereby support on a shared signalprocessing hardware.[0018] Further, carrier and timing recovery methodsused for different digital TV and analog TV standardsdiffer because for single carrier standards (e.g., ATSC)there is a suppressed pilot or analog TV standards whichhave colour and sound carriers. For Multi-carrier stand-ards (like DVB-T, DVB-S, ISDB-T, CDMB-T etc) the re-ceived signal consists of multiple tones. For Cable stand-ards (ITU-T J.83A/J.83B and J.83C) the transmitted sig-nal is pilot-less. Thus the carrier/timing recovery schemerequired for supporting multiple TV standards on a singlechip would require different signal processing hardware.This inevitably leads to a much larger area and increasedcost. For instance, a Television (TV) communicationstandard is considered as an example. Further, othercommunication standards include a 3G standard, a Wi-Fi standard, a LTE standard, a Bluetooth standard, orany other such standards are also having same draw-backs discussed in the TV standards.[0019] Equalization methods used across differentstandards to overcome multipath environments are alsoradically different. While most of the multi-carrier (OFDM)based standards estimate channel impulse response us-ing frequency domain analysis (like FFT) or a combina-tion of time and frequency domain analysis, most of thesingle-carrier based standards require a time domainequalizer with variable feed-forward and feedback taps.Again such a huge difference makes it impossible toshare the same resource in a hardware based implemen-tation. Thus supporting multiple communication stand-ards would need disparate hardware to be integratedthereby increasing area significantly.[0020] US 2009/0274202 discloses a multi-standardSDR including codec, multimode modem and up/downconversion circuitry between IF and baseband.

SUMMARY

[0021] In view of the foregoing, an embodiment hereinprovides a Software Defined Radio (SDR) subsystem ca-pable of supporting multiple communication standardsfor modulation and demodulation of an input signal. TheSDR subsystem includes (i) a Signal Conditioning Clus-ter (SCC) unit (ii) a Signal Processing Cluster (SPC) unitand (iii) a Channel Codec Cluster (CCC) unit that per-forms a channel encoding and a channel decoding. The

SCC unit (a) receives a baseband signal from the SPCunit and produces a digital Intermediate Frequency (IF)signal for the modulation and (b) receives an IF signalfrom a tuner and produces a complex baseband signalfor the demodulation. The SPC unit (a) receives encodedbits from the CCC unit and produces the baseband signalfor the modulation and (b) receives the complex base-band signal from the SCC unit and produces decisionbits for the demodulation. The CCC unit (a) receives theinput signal and produces the encoded bits the modula-tion and (b) receives the decision bits from the SPC unitand produces a decoded data for the demodulation. Inone embodiment, The SCC unit (a) receives the base-band signal from the SPC unit and produces the digitalIntermediate Frequency (IF) signal based on a first com-munication standard for a trans-modulation and (b) re-ceives the IF signal from the tuner and produces the com-plex baseband signal based on a second communicationstandard for the trans-modulation. The SPC unit (a) re-ceives the encoded bits from the CCC unit and producesthe baseband signal based on the first communicationstandard for the trans-modulation and (b) receives thecomplex baseband signal from the SCC unit and produc-es the decision bits based on the second communicationstandard for the trans-modulation.[0022] The multiple communication standards includeanalog and digital communication standards. The SCCunit further includes (i) a Digital Front End (DFE) unit, (ii)a plurality of Signal Conditioning (SCON) CPUs adaptedto sample based signal processing and (iii) a memorysub system. The DFE includes a Numerically ControlledOscillator (NCO) that operates at a sample-rate frequen-cy and that performs a digital down-conversion of the IFsignal into the complex baseband signal. The SCONCPU (a) perform a pulse shaping of the baseband signalfrom the SPC unit for the modulation and (b) perform aFinite Impulse Response (FIR) filtering, an Infinite Im-pulse Response (IIR) filtering, an interpolation, and asample rate conversion filtering on the complex base-band signal from the NCO for the demodulation. Thememory subsystem includes (i) a store-and-forward buff-er or a cut-through buffer for storing the complex base-band signal or the baseband signal and (ii) a Direct Mem-ory Access (DMA) unit that extracts data that corre-sponds to the complex baseband signal or the basebandsignal from the store-and-forward buffer or the cut-through buffer based on a programmed threshold.[0023] The SPC unit includes (i) a plurality of SignalProcessing (SPROC) CPUs adapted for block based sig-nal processing (ii) a Least Mean Squares (LMS) coproc-essor that is coupled to the plurality of SPROC CPUsand (iii) a memory subsystem. The SPROC CPU (a) per-form a modulation, a framing and a mapping on the en-coded bits from the CCC unit to produce the basebandsignal for the modulation of the input signal and (b) per-form a demodulation, a channel estimation, a channelcorrection, and de-mapping of symbols on the complexbaseband signal received from the SCC unit to produce

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the decision bits for the demodulation of the input signal.The Least Mean Squares (LMS) coprocessor performsan adaptive feedback and feed-forward FIR filtering, acoefficient or tap adaptation, and a high speed FIR filter-ing operation on multiple streams. The memory subsys-tem includes (i) an Inter-Cluster Buffer (ICB), (ii) a DMAunit that processes a transfer of a processed data to theCCC unit and (iii) a Shared Memory Subsystem (SHM)that is connected across the SPROC CPU. The SHM isused as a buffer for storing and exchanging of computedresults between the SPROC CPUs. The SPROC CPUsincludes (i) a complex arithmetic slot that performs atleast one of real and complex arithmetic operations,wherein the operations include N-way Single InstructionMultiple Data (SIMD) operations, and (ii) a cordic slot thatgenerates (i) sine and cosine values and (ii) magnitudeand phases of complex signals, wherein the cordic slotis coupled to the LMS coprocessor to perform cycle effi-cient read and write operations during an equalizer op-eration. The complex arithmetic slot also supports FastFourier Transform (FFT) butterfly operations. The cordicslot further performs N-way arithmetic, logic and extractoperations.[0024] The CCC unit (a) receives the input signal andperforms at least one of a viterbi encoding, a Reed Solo-mon (RS) encoding, and a Low-Density Parity-Check(LDPC) to produces the encoded bits for the modulationand (b) receives the decision bits from the SPC unit andperforms at least one of a viterbi decoding, a Reed Solo-mon (RS) decoding, and a Low-Density Parity-Check(LDPC) to produces the decoded data for the demodu-lation.[0025] In one aspect, a method for demodulating aninput signal in software defined radio (SDR) subsystemis provided. The SDR subsystem is capable of supportingmultiple communication standards. The method includes(i) receiving the input signal in a tuner and converting theinput signal into one of a zero Intermediate Frequency(IF) signal, a low IF signal, and a standard IF signal (ii)converting the one of the zero IF signal, low IF signal andstandard IF signal into a digital signal, (iii) down convert-ing the digital signal into a complex baseband signal, (iv)performing a FIR filtering, an IIR filtering, an interpolationand a sample rate conversion filtering on the complexbaseband signal to produce a filtered complex basebandsignal using a first hardware adapted for a sample basedsignal processing, (v) performing a demodulation, achannel estimation, a channel correction, and a de-map-ping on the filtered complex baseband signal based onthe multiple communication standards to obtain decisionbits using a second hardware adapted for block basedsignal processing and (vi) performing at least one of aviterbi decoding, a Reed Solomon (RS) decoding, and aLow-Density Parity-Check (LDPC) decoding on the de-cision bits to obtain decoded data. In one embodiment,the first hardware is a Signal Conditioning CPU (SCONCPU) that includes (i) a load-store slot that performs load-ing and storing of the complex baseband signal to enable

filtering operation, (ii) a filter slot that receives the com-plex baseband signal from the load-store slot and per-forms the FIR filtering, IIR filtering, interpolation and sam-ple rate conversion filtering and (iii) an arithmetic slot thatperforms arithmetic operations required for filtering op-eration. In another embodiment, the second hardware isa Signal Processing CPU (SPROC CPU) that includes(i) a complex arithmetic slot and a cordic slot that per-forms the demodulation, the channel estimation, thechannel correction, and the de-mapping on the filteredcomplex baseband signal.[0026] In another aspect, a method for modulating aninput signal in a software defined radio (SDR) subsystemthat is capable of supporting multiple communicationstandards is provided. The method includes (i) perform-ing at least one of a viterbi encoding, a Reed Solomon(RS) encoding, convolution encoding and a Low-DensityParity-Check (LDPC) encoding on the input signal to pro-duce encoded bits, (ii) performing a modulation, a fram-ing, and a mapping on the encoded bits based on themultiple communication standards to obtain basebandsignals using a first hardware adapted for a block basedsignal processing, (iii) performing an up-conversion anda pulse shaping of the baseband signals to produce adigital IF signal using a second hardware adapted for asample based signal processing and (iv) converting thedigital IF signal into an analog signal. In one embodimentthe first hardware is a Signal Processing CPU (SPROCCPU) that includes a complex arithmetic slot and a cordicslot that performs the modulation, framing and mappingon the encoded bits. In another embodiment, the secondhardware is a Signal Conditioning CPU (SCON CPU)that includes a load-store slot, a filter slot and an arith-metic slot that performs the up-conversion and the pulseshaping of the baseband signals.[0027] These and other aspects of the embodimentsherein will be better appreciated and understood whenconsidered in conjunction with the following descriptionand the accompanying drawings. It should be under-stood, however, that the following descriptions, while in-dicating preferred embodiments and numerous specificdetails thereof, are given by way of illustration and not oflimitation. Many changes and modifications may be madewithin the scope of the embodiments herein, and the em-bodiments herein include all such modifications.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The embodiments herein will be better under-stood from the following detailed description with refer-ence to the drawings, in which:

FIG. 1 illustrates a typical ATSC demodulation signalchain;FIG. 2 illustrates a typical cable demodulation (J.83Aand J.83C) signal chain;FIG. 3 illustrates a typical cable demodulation(J.83B) chain;

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FIG. 4A illustrates a typical DVB-T demodulationchain;FIG. 4B illustrates a typical DVB-S demodulationchain;FIG. 5 illustrates a typical ISDB-T demodulatorchain;FIG. 6 illustrates a typical analog TV signal demod-ulation chain;FIG. 7 illustrates a cost versus flexibility for differentarchitectures;FIG. 8 illustrates a top level architecture of softwaredefined radio (SDR) subsystem for universal modu-lation, demodulation or trans-modulation;FIG. 9 illustrates an architecture of a software de-fined radio (SDR) receiver system that includes asoftware defined radio subsystem of FIG. 8 for uni-versal TV signal demodulation according to an em-bodiment herein;FIG. 10 illustrates an exploded view of the signalconditioning cluster of FIG. 9 according to an em-bodiment herein;FIG. 11 illustrates an exploded view of the signalprocessing cluster of FIG. 9 according to an embod-iment herein;FIG. 12 illustrates a mapping of a ATSC demodula-tion on the software defined radio subsystem of FIG.9 according to an embodiment herein;FIG. 13 illustrates a mapping of a DVB-T demodu-lation on the software defined radio subsystem ofFIG. 9 according to an embodiment herein;FIG. 14 illustrates a cable demodulator partitioning(J.83A and J.83C) on the software defined radio sub-system of FIG. 9 according to an embodiment herein;FIG. 15 illustrates a cable demodulator partitioning(J.83B) on the software defined radio subsystem ofFIG. 9 according to an embodiment herein;FIG. 16 illustrates a mapping of an ISDB-T standardto the software defined radio subsystem of FIG. 9according to an embodiment herein;FIG. 17 illustrates a DMB-T single carrier mode map-ping to the software defined radio subsystem of FIG.9 according to an embodiment herein;FIG. 18 illustrates a DMB-T Multi-carrier mode map-ping to the software defined radio subsystem of FIG.9 according to an embodiment herein;FIG. 19 illustrates an analog TV standard mappingon the software defined radio subsystem of FIG. 9according to an embodiment herein;FIG. 20 illustrates a FM and AM demodulation map-ping on the software defined radio subsystem of FIG.9 according to an embodiment herein;FIG. 21 illustrates a DAB demodulation on mappingon the software defined radio subsystem of FIG. 9according to an embodiment herein;FIG. 22 illustrates the software defined radio trans-mitter system that includes a software defined radiosubsystem of FIG. 8 for universal TV signal modu-lation according to an embodiment herein;

FIG. 23 illustrates a usage of the software definedradio modem that includes a software defined radiosubsystem of FIG. 8 for a universal modulation anddemodulation function according to an embodimentherein;FIG. 24 illustrates a flow chart for a method of per-forming universal TV signal demodulation in the SDRreceiver system of FIG. 9 according to an embodi-ment hereinFIG. 25 illustrates a flow chart for a method of per-forming universal TV signal modulation in the SDRtransmitter system of FIG. 22 according to an em-bodiment herein; andFIG. 26 illustrates a graphical comparison of an in-cremental cost of ownership versus a number of TVstandards supported for a system integration ap-proach, an ASIC integration approach as comparedto the proposed software defined radio subsystemof FIG. 8 according to an embodiment herein.

DETAILED DESCRIPTION OF PREFERRED EMBOD-IMENTS

[0029] The embodiments herein and the various fea-tures and advantageous details thereof are explainedmore fully with reference to the non-limiting embodimentsthat are illustrated in the accompanying drawings anddetailed in the following description. Descriptions of well-known components and processing techniques are omit-ted so as to not unnecessarily obscure the embodimentsherein. The examples used herein are intended merelyto facilitate an understanding of ways in which the em-bodiments herein may be practiced and to further enablethose of skill in the art to practice the embodiments here-in. Accordingly, the examples should not be construedas limiting the scope of the embodiments herein.[0030] As mentioned, there remains a need for a Soft-ware Defined Radio (SDR) subsystem that is capable ofperforming a modulation, a demodulation or a trans-mod-ulation of digital and analog signals covering differentmediums like cable, terrestrial, satellite and radio stand-ards. The embodiments herein achieve this by providingthe modulation, the demodulation or the trans-modula-tion of digital as well as analog signals using a softwaredefined radio subsystem. Referring now to the drawings,and more particularly to FIGS. 8 through 24, where similarreference characters denote corresponding featuresconsistently throughout the figures, preferred embodi-ments are described herein.[0031] Fig. 8 illustrates a top level architecture diagramof software defined radio (SDR) subsystem 800 for mod-ulation, demodulation or trans-modulation of input sig-nals according to embodiment herein. The SDR subsys-tem 800 is capable of supporting multiple communicationstandards that includes a multiple analog and digital com-munication standards. The SDR subsystem 800 includes(i) a signal conditioning cluster (SCC) unit 802, (ii) a signalprocessing cluster (SPC) unit 804 and (iii) a channel co-

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dec cluster (CCC) unit 806. The SCC unit 802 includesa signal conditioning CPU (SCON CPU) that is adaptedfor a sample based signal processing. The SPC unit 804includes a signal processing CPU (SPROC CPU) whichis adapted for a block based signal processing.[0032] During the modulation, the CCC unit 806 per-forms a channel encoding operation on a packetized datato produce encoded bits. The SPC unit 804 (a) receivesthe encoded bits and performs a mapping of encodedbits to a baseband signal, (b) a framing operation thatinserts data and carrier into the baseband signal, and (c)performs modulation on the baseband signal based onmultiple analog and digital communication standards.The SCC unit 802 receives a baseband signal and per-forms an up-conversion and pulse shaping of a modulat-ed baseband signal to produce a digital Intermediate Fre-quency (IF) signal.[0033] During the demodulation, the SCC unit 802 re-ceives an Intermediate Frequency (IF) signal from tunerand down-converts into a complex baseband signal andalso performs a Finite Impulse Response (FIR) filtering,an Infinite Impulse Response (IIR) filtering, an interpola-tion, a sample rate conversion filtering on the complexbaseband signal. The SPC unit 804 receives the complexbaseband signal and performs a demodulation, a chan-nel estimation, a channel correction and de-mapping toproduce a decision bits. The CCC unit 806 unit performsa channel decoding operation on the decision bits to pro-duce decoded bits.[0034] During the trans-modulation, the SDR subsys-tem is capable of modulating the input signal in one com-munication standards among the multiple communica-tion standards and capable of demodulating the inputsignal in another communication standard.[0035] For instance, a Television (TV) communicationstandard is considered as an example. FIG. 9 illustratesarchitecture of a software defined radio (SDR) receiversystem 900 for universal TV signal demodulation accord-ing to an embodiment herein. The SDR receiver system900 includes (i) a tuner 902, (ii) an Analog to Digital Con-verter (ADC) 904 and (iii) a software defined radio sub-system 906. The software defined radio subsystem 906includes (i) a signal conditioning cluster (SCC) unit 908,(ii) a signal processing cluster (SPC) unit 910, (iii) a con-trol cluster unit 912, and (iv) a channel decoding clusterunit 914. The SCC unit 908 performs digital down-con-version from Intermediate Frequency (IF) rate samplesto symbol-rate samples. The SCC unit 908 may include(i) one or multiple signal conditioning CPUs (SCON CPU)which is adapted for a sample based signal processing,(ii) a digital front end (DFE), (iii) a memory subsystemthat includes a SCC FIFO, and a SCC-DMA block. Amessage box (MSGBOX) is used to interact with otherCPU Clusters. A programmable interrupt controller (PIC)is used to interface to interrupts generated on chip fromsame or different clusters. The SCC unit 908 interfacesto the control cluster unit 912 via a bridge and to an inter-cluster buffer (ICB) memory of the SPC unit 910 via a

DMA. For instance, a Television (TV) signal receiver isconsidered as an example.[0036] The SPC unit 910 may include (i) one or moreLMS accelerators (a LMS coprocessor), (ii) a plurality ofsignal processing CPUs (SPROC CPUs) which is adapt-ed for a block based signal processing and (iii) a memorysubsystem that includes an inter-cluster buffer (SPC-ICB), a shared memory buffer (SPC-SHMB), a packingbuffer, and SPC-DMA block. The SPC unit 910 performsone or more tasks such as symbol synchronization, achannel estimation, a channel correction and a demap-ping to bits to produce a decision bits. In one embodimentthe decision bits may be a hard decision bits or soft de-cision bits. The SPC unit 910 receives the samples in theinter-cluster buffer to be used for further processing. TheSPC unit 910 interfaces to the control cluster unit 912 viaa bridge to the Inter-cluster buffer (ICB) memory of theChannel Decoding cluster unit 914 via a DMA block.[0037] The overall scheduling and control of the entiresoftware defined radio subsystem 906 is performed bythe control cluster unit 912 which includes a general pur-pose processor with some general purpose peripheralssuch as a UART, a 2-wire interface and/or a boot ROM.The control cluster unit 912 accesses all individual clus-ters via the bridge. The channel decoding cluster unit 914performs the tasks of a viterbi decoding, a Reed Solomon(RS) decoding, and a LDPC decoding along with a bytedeinterleaver. The decoded data is finally pushed out astransport stream data in case of Digital TV Standards orCVBS and SIF stream in case of Analog TV Standardsto interface to an on-chip/off-chip Digital to Analog Con-verter (DAC).[0038] FIG. 10 illustrates an exploded view of the signalconditioning cluster unit 908 of FIG. 9 according to anembodiment herein. In particular, FIG. 10 illustrates howthe signal conditioning cluster unit 908 is adapted for asample based signal processing of signals. Signal con-ditioning cluster unit 1000 includes (i) a digital front end1002, (ii) an input to receive ADC samples 1004, (iii) oneor more SCON CPUs 1012, (iv) a memory data bus andarbiter 1014, (v) a program memory 1024, (vi) a SCCdata memory 1026, (vii) a SCC FIFO 1028 and (viii) aSCC-DMA 1030. The digital front end 1002 includes (a)a numerically controlled oscillator (NCO) 1006, (b) a mix-er 1008, and (c) an automatic gain control (AGC) circuitry1010. The digital front end 1002 receives samples ob-tained by digitizing the incoming intermediate frequencysignal from analog-to-digital converter (ADC) samplesinput 1004. The numerically controlled oscillator 1006operates at a sample-rate frequency.[0039] The mixer 1008 obtains a digitally synthesizedwaveform from the NCO 1006 and down-converts the IFsignal to a baseband signal. The automatic gain control(AGC) circuitry 1010 ensures that the full-scale range ofthe analog to digital converter is used effectively. Thedigital front end 1002 includes an internal FIFO storingincoming sample converted to baseband. The signal con-ditioning CPUs 1012 may include (i) a filter slot 1016, (ii)

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a load-store broadcast slot 1018, (iii) an arithmetic slot1020, and (iv) a logical slot 1022. In one embodiment,the signal conditioning CPU 1012 is capable of interfac-ing a high speed streaming input samples and imple-ments a FIR filtering, an IIR filtering, and sample rateconversion filters.[0040] In addition, the SCON CPU 1012 also performscarrier synchronization by implementing PLL’s in soft-ware. The SCON CPU 1012 also performs the task of IQimbalance correction when input samples are obtainedfrom IQ ADC. The SCON CPU 1012 has a program mem-ory 1024 which interfaces via the program memory inter-face. The SCON CPUs 1012 interfaces with its dedicateddata memory signal conditioning cluster (SCC) datamemory 1026, the digital front end 1002, the SCC FIFO1028 and the SCC DMA 1030 through a data memoryinterface. The digital front end (DFE) 1002 interfaces withthe SCON CPUs 1012 as a memory-mapped device onthe digital memory data bus 1014.[0041] The filter slot 1016 is capable of performing realmultiply and real MAC operations (with 64 MACs). Thefilter slot 1016 includes one or more MAC unit that arecapable of performing high sample rate FIR filtering andIIR filtering, a decimation operation, an Interpolation, adown-sampling and Up-sampling operation.[0042] The load-store broadcast slot 1018 is capableof performing 128 bit or 8 x 16bit sample load-store op-erations. To support interpolation features there is a loadwith extract feature which enables retention or rejectionof samples from previous load operations and concate-nation with incoming loaded samples. The arithmetic slot1020 is capable of performing basic arithmetic functionssuch as an addition operation, a subtraction operation,an absolute finding operation, an exponent calculationand swapping of IQ pair of complex signals operation. Inaddition, the arithmetic slot 1020 also processes accu-mulator values either by a horizontal addition with post-scaling or just by moving scaled accumulator values intoone or more general purpose registers. The logical slot1022 is capable of supporting basic logical operationssuch as one or more Boolean operations and Compareoperations.[0043] The program memory 1024 is 128 bits wide.The bridge is used at a boot-up time to download eachCPU’s code into its program memory 1024. The bridgeinterface is used for transferring control information froma control CPU in the control cluster unit 912 to the SCCunit 908. The SCC data memory bus and arbiter 1014 isa 128-bit wide bus internal to the SCC unit 908 throughwhich the SCON CPUs 1012 and the bridge (e.g., shownas bridge i/f in FIG. 10) may access slaves on the datamemory bus. The slaves on this bus are a SCC datamemory 1026, a DFE 1002, a SCC FIFO 1028, and aSCC-DMA 1030. The SCON program memory bus (e.g.,shown as PMem Arb in FIG. 10) is 128 bits wide.[0044] After completion of processing by the SCONCPUs 1012, the data is written by the SCON CPUs 1012over DMEM bus 1014 to the SCC FIFO 1028. The SCC

FIFO 1028 serves either as a store-and-forward or as acut-through buffer. The SCC FIFO 1028 is a 256 bit widebus with programmable depth. Data is pushed into theSCC FIFO 1028 by writing to its push-address by theCPU. The attached DMA engine (i.e., a SCC-DMA 1030)pops out data from the SCC FIFO 1028 through a dedi-cated interface independent of data memory bus 1014when a programmed threshold is reached.[0045] The signal conditioning cluster DMA (SCC-DMA) 1030 is programmed and enabled to perpetuallyexecute data transfers without any need for reprogram-ming. This is customized to handle bank-based and cir-cular nature of an inter-cluster buffer. Before starting towrite a new bank of data, the SCC-DMA 1030 first sendsa bank request to the inter-cluster buffer and waits toreceive a confirmation for that bank from the signalprocessing cluster-inter-cluster buffer. When the SCCFIFO 1028 indicates that it is ready with a block of data,the SCC-DMA 1030 starts reading from the SCC FIFO1028 and writes it into sequential addresses of the Inter-cluster buffer in Signal Processing Cluster.[0046] The SCC-DMA 1030 further samples the SCCFIFO 1028 ready status when it has completed the pro-grammed transfer count (DMA Count) number of double-words. When a bank boundary is reached, the SCC-DMA1030 communicates the status of current bank to the ICB(inter-cluster buffer) and requests for a next bank. TheSCC-DMA 1030 is programmed with information aboutthe range of ICB addresses over which it needs to main-tain circularity. The SCC-DMA 1030 assumes the size ofeach bank as a predefined size to determine when a bankcrossover occurs. Associated with the SCON CPUs 1012is a message box (e.g., shown as SCC MSGBOX in FIG.10) which allows the SCON CPUs 1012 to exchange sin-gle word (32bit) messages with each of the other CPU’sin different clusters. The message box includes a collec-tion of registers and is connected to the DMEM bus 1014of the SCC unit 908. The message box receives mes-sages in its Inbox from all other CPU’s and sends mes-sages to other CPU’s via Outbox. The SCC unit 908 in-cludes a programmable interrupt controller (SCC PIC)which aggregates multiple source events into two levelsof interrupts (INT1, INT2) and an exception (EXCP) forthe SCON CPUs 1012.[0047] FIG. 11 illustrates an exploded view 1100 of thesignal processing cluster unit 910 of FIG. 9 according toan embodiment herein. In particular, FIG. 11 illustrateshow the signal processing cluster unit 910 is adapted fora block based signal processing of signals. The signalprocessing cluster unit 910 is capable of handling com-plex arithmetic computations such as a complex MACsoperation, a complex multiplication operation and is fur-ther capable of handling large (8192, 4096 or 2048-point)FFT’s including non-power of 2, a prime factor DFT com-putation, etc. In OFDM based standards, a signalprocessing CPUs (SPROC CPUs) 1108 are used for per-forming symbol synchronization, a channel impulse re-sponse interpolation, a symbol de-interleaving and de-

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mapping. The SPROC CPUs 1108 include one or moreexecution slots (e.g. 4 execution slots) such as (i) a com-plex arithmetic slot 1104, (ii) a cordic slot 1106, and (iii)two 64-bit load-store slots 1102.[0048] Special instructions for dividing complex signalby a real signal and Single depth trace-back for viterbidecoding are provided for channel estimation. The load-store slots 1102 are capable of 64 bit load and store op-erations. They support linear, circular and bit-reverse ad-dressing. In one embodiment, few registers are markedin the register file as address pointers. In addition to load-store operations, the load-store slots 1102 are also ca-pable of performing boolean, compare and extract oper-ations. Additionally, the load-store slots 1102 are capableof executing arithmetic operations such as ADD, SUBand 2-way or 4-way SIMD variants of ADD and SUB op-erations.[0049] The 2 load-store slots 1102 ensure that a highbandwidth memory interface is required for all symbolprocessing tasks. The complex arithmetic slot 1104 iscapable of performing operations on complex signals. Itsupports complex multiply, complex conjugate multiply,complex MAC, real multiply, real MAC and real multiplyand add operations. These operations may include either2-way or 4-way SIMD operations. The complex arithmeticslot 1104 also supports very efficient FFT butterfly oper-ations which enable low cycle count FFT operations. Toenable division operations required by the channel equal-izer, the complex arithmetic slot 1104 supports opera-tions such as a 1-way or a 2-way SIMD complex numberdivided by a real number.[0050] The cordic slot 1106 is capable of generatingtwiddle factors (e.g., sine and cosine operations) as wellas non-normalized magnitudes and phases of complexsignals. The cordic slot 1106 is tightly coupled with theLMS coprocessor 1110 which enables to perform a cycleefficient read and write operations during equalizer op-eration. The cordic slot 1106 also performs logic, extract,shift, packed extract, packed shift and single or multi-wayadd, subtract, add-subtract paired operations. The LMScoprocessor 1110 is a compute engine used for channelestimation in digital TV standards and high speed FIRfiltering in analog TV Standards. It has efficient hardwarestructures to perform adaptive feedback and feed-for-ward FIR filtering, coefficient/tap adaptation based onleast-mean-squared algorithm, and high speed FIR fil-tering operations on multiple streams.[0051] The LMS coprocessor 1110 interfaces to theSPROC CPUs 1108 through either of the load-store slots1102 (or Bridge) for a transfer of configuration parame-ters and a tightly coupled register-like interface for trans-fer of sample update and reading back the result value.A signal processing cluster inter-cluster buffer 1112 is abank-based memory with wide data width meant for con-tinuous transfer of processed signal from the signal con-ditioning cluster unit 908 to be consumed by the signalprocessing cluster unit 910. The signal processing clusterinter-cluster buffer bank 1112 can be written by signal

conditioning cluster DMA (one bank at a time) and canbe read (multiple banks at a time) by one of the signalprocessing cluster CPUs 1108. Banks are contiguous inaddress space and are used in a circular mode by signalconditioning cluster DMA because it is provided for trans-ferring continuous signal data.[0052] The inter-cluster buffer bank 1112 is used in alinear or a circular mode depending on the signal condi-tioning cluster DMAs parameters. Once programmed,the signal conditioning cluster DMA can carry on writingperpetually. The signal conditioning cluster DMA also in-corporates a mode where it stops after transfer of a pro-grammable block of data. A combination of hardware andsoft-arbitration techniques are used for accessing thebanks in the signal processing cluster inter-cluster bank1112 amongst the different available masters like DMA,bridge and signal processing cluster CPUs. An error in-terrupt can be triggered if a non-owner tries to access abank.[0053] A signal processing cluster shared memorybuffer 1114 is a bank-based buffer with a wide data pathmeant for storage and exchange of computed results be-tween signal processing cluster CPUs 1108. Since theaccess paths to bridge are also required they could alsohave similar types of access schemes. There are specificregisters for programming a signal processing clusterDMA (SPC-DMA) 1120, a deinterleaver buffer (DEINTBFR)1118, and to select between different signalprocessing CPUs 1108 for ownership of the shared mem-ory banks, to ensure that only one CPU has exclusiveaccess. The access to the SPC Shared Memory buffer(SHM) 1114 and CPU-exclusive slaves (PIC, MSGBOX)are arbitrated between the SPROC CPUs 1108 andBridge either using priority based or round-robin algo-rithms.[0054] A signal processing data memory 1116 is usedas a local memory by the SPROC CPUs 1108. The dein-terleaver buffer 1118 assists in a data packing operationto be performed on data written by a SPROC CPUs 1108before it is transferred by SPC-DMA 1120 to a channeldecoding cluster. Specific packing modes for differentdigital TV standards (like ATSC, DVB-T, ISDB-T and CD-MB-T) and analog TV modes exist, which are pro-grammed using configuration registers. The packingbuffer accepts data of a certain programmed data widthfrom signal processing CPUs 1108 in a non-sequentialorder.[0055] SPC-DMA 1120 waits for an indication that datablock is ready along with the block size from deinterleaverbuffer after which it transfers data to Inter-cluster bufferof channel decoding cluster unit 914. Here the channeldecoding cluster unit 914 consists of accelerators per-forming the tasks of a viterbi and TCM decoder, a ReedSolomon (RS) decoder and a LDPC Decoder. In additionthe byte deinterleaver is also present in this cluster.These processes act on the data in various phases asinner decoder and outer decoder. Additional processessuch as an inner deinterleaver, an outer deinterleaver

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and a de-randomizer etc. are monitored in the channeldecoding cluster unit 914.[0056] The decoded data is finally collected in thetransport stream output block. This contains a ping-pongbuffer that accepts packets of transport stream afterchannel decoding steps are complete and sends themout in 8-bit parallel or serial mode outputs. In case ofanalog TV standards the processed data from the SPCunit 910 is bypassed through the channel decoding clus-ter unit 914. The video data (CVBS) is appropriately rout-ed to the Video DAC and the audio data (SIF) is appro-priately routed to the SIF DAC.[0057] FIG. 12 illustrates a mapping 1200 of ATSC de-modulation on the SDR subsystem 906 of FIG. 9 on thedifferent clusters according to an embodiment herein..The NCO 1202 and mixer operation is followed by a pilotfrequency estimation 1204, an adjacent channel filtering1206, an up-sampling 1208, a sample rate conversionand matched filters 1210. All are performed on the SCCunit 908. A band extraction 1212, a sampling frequencyoffset estimation 1214, a carrier recovery 1216, a pilotremoval 1218, a segment sync detection and frame syncdetection 1220 are performed on the SPC unit 910. ALMS equalizer 1222 is responsible for a channel equal-ization. The remaining processes constituting an innerdeinterleaver 1224, a trellis decoding 1226, an outerdeinterleaver 1228, a Reed-solomon decode and de-ran-domizer 1230 are expected to be performed in the chan-nel decoding cluster unit 914. The final transport streampackets are created using a TSO module to be sent to amedia processor.[0058] FIG. 13 illustrates a mapping 1300 of a DVB-Tdemodulation on the software defined radio subsystem906 of FIG. 9 according to an embodiment herein. In par-ticular, the mapping 1300 illustrates how various DVB-Tdemodulation processes are partitioned across the dif-ferent clusters. The NCO and mixer 1302 followed by anIF to baseband converter 1304, a down-sampler 1306,an adjacent channel filtering 1308 and an interpolationfilter 1310 functions are performed on the SCC unit 908.A time domain synchronization 1312, a Fast FourierTransform (FFT) 1314, a frequency domain synchroni-zation 1316, a pilot processing 1318, a fine symbol syn-chronization 1322, a frame sync detection 1324, a chan-nel estimation 1320, a channel correction and de-map-ping 1326 and a bit interleaving 1328 are performed onthe SPC unit 910 using one or multiple CPUs. The LMSequalizer is optionally used for long echo channel short-ening. The remaining processes constituting a viterbi de-coding 1330, an outer deinterleaver 1332, a reed-solo-mon decoder and de-randomizer 1334 are performed inthe channel decoding cluster unit 914. The final transportstream packet creation is done using the TSO module.[0059] FIG. 14 illustrates a cable demodulator parti-tioning 1400 (J.83A and J.83C) on the software definedradio subsystem 906 of FIG. 9 according to an embodi-ment herein. The NCO and mixer 1402 is followed by adown sampling filter 1404, an adjacent channel filter

1406, an up sampling filter 1408, an interpolation filter1410 and a timing recovery functions 1412 are mappedon the signal conditioning cluster unit 908. The functionsof a coarse carrier recovery 1414, a LMS equalization1416, a de-mapping 1418 are mapped on the SPC unit910. The remaining functions such as a frame synchro-nization 1420, an outer deinterleaver 1422, a reed-solo-mon decoder and de-randomization 1424 are implement-ed on the channel decoding cluster unit 914.[0060] FIG. 15 illustrates a cable demodulator parti-tioning (J.83B) 1500 on the software defined radio sub-system 906 of FIG. 9 according to an embodiment herein.A NCO and mixer 1502 followed by a down samplingfilter 1504, an adjacent channel filter 1506, an up sam-pling filter 1508, an interpolation filter 1510 and a timingrecovery functions 1512 are mapped on the SPC unit908. The functions of a coarse carrier recovery 1514 anda LMS equalization 1516 are mapped on the SPC unit910. The remaining functions such as a trellis decoding1518, a frame synchronization 1520, an outer deinter-leaver 1522, a reed-solomon decoder and de-randomi-zation 1524 are implemented on the channel decodingcluster unit 914.[0061] FIG. 16 illustrates a mapping 1600 of an ISDB-T standard to the software defined radio subsystem 906of FIG. 9 according to an embodiment herein. The map-ping 1600 illustrates how the various ISDB-T demodula-tion processes are partitioned across the different clus-ters. A NCO and mixer 1602 followed by an IF to base-band conversion 1604, a down-sampler 1606, an adja-cent channel filtering 1608 and a sample rate convertor1610 functions are performed on the SCC unit 908.[0062] A time domain synchronization 1612, a FastFourier Transform (FFT) 1614, a frequency domain syn-chronization and a pilot processing 1616, a TMCC de-coding 1618, a frequency & time domain deinterleaver1620, a channel estimation 1622, a hierarchical multi-plexer 1624, a channel correction and de-mapping 1626and a bit deinterleaver 1628 are performed on the SPCunit 910 across one or multiple CPUs. The remainingprocesses constituting a Viterbi decoding 1630, an outerbyte de-interleaving 1632, a reed-solomon decoder andde-randomizer 1634 are performed in the channel de-coding cluster unit 914. The final transport stream packetis generated by the TSO module.[0063] FIG. 17 illustrates a DMB-T single carrier modemapping 1700 to the software defined radio subsystem906 of FIG. 9 according to an embodiment herein. A NCOand mixer 1702 enables an IF to baseband conversion1704 in the SCC unit 908. This is followed by a down-sampler 1706, an adjacent channel filtering 1708, a sam-ple rate convertor 1710, a timing recovery and matchedfilter 1712 functions performed on the SCC unit 908. Aframe recovery 1714, a fine carrier recovery 1716, achannel estimation processes are performed in the SPCunit 910. The LMS equalizer 1718 in case of single carriermode is responsible for channel equalization. Furtherprocesses of extraction of a system information 1720, a

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time domain de-interleaving 1722 and de-mapping 1724are performed on the SPC unit 910 across one or multipleCPUs. The remaining processes constituting a LDPC De-coding 1726, BCH decoding 1728 and a de-randomizer1730 are performed in the channel decoding cluster unit914. The final transport stream packet is generated bythe TSO module.[0064] FIG. 18 illustrates a DMB-T multi-carrier modemapping 1800 to the software defined radio subsystem906 of FIG. 9 according to an embodiment herein. A NCOand mixer 1802 are followed by IF to baseband conver-sion 1804, a down-sampler 1806, an adjacent channelfiltering 1808, a sample rate convertor 1810, a timingrecovery and a matched filter 1812 functions on the SCCunit 908. A frame recovery 1814, a fine carrier recovery1816, a channel estimation and correction 1818, a 3780point DFT and frequency de-interleaving 1820, an ex-traction of system information 1822, a time de-interleav-ing and de-mapping 1824 processes are performed inthe SPC unit 910 on one or multiple CPUs. The remainingprocesses constituting a LDPC decoding 1826, a BCHdecoding 1828 and a de-randomizer 1830 are performedin the channel decoding cluster unit 914. The final trans-port stream packet is generated by the TSO module.[0065] FIG. 19 illustrates an analog TV standard map-ping 1900 on the software defined radio subsystem 906of FIG. 9 according to an embodiment herein. The figure1900 illustrates a mapping analog TV standard on theSDR subsystem 906 across the different clusters. A NCOand mixer 1902 followed by a carrier recovery 1904, adown-sampling and image rejection filter 1906, an adja-cent channel nyquist filter 1908 and a video low passfilter 1910 and an audio band pass filter 1912 are per-formed on the SCC unit 908. The output from the audioband pass filter 1912 is fed to an up-sampling filter 1914operating in one of the CPU’s in the SPC unit 910. Theoutput of the up-sampling filter 1914 is fed to an on-chipor off-chip SIF DAC.[0066] The output of the video low pass filter is fed tothe LMS coprocessor 1110 which performs the groupdelay equalization filtering 1916 function. The output fromthis filter is further up-sampled on another CPU in theSPC unit 910. The output of the up-sampling filter is fedto an on-chip or off-chip CVBS DAC. The outputs fromthe SPC unit 910 are bypassed to the CVBS DAC andSIF DAC outputs through the channel decoding clusterunit 914.[0067] FIG. 20 illustrates a FM and/or AM demodula-tion mapping 2000 on the software defined radio subsys-tem 906 of FIG. 9 according to an embodiment herein.The mapping 2000 illustrates how FM and AM demodu-lation on the SDR subsystem 906 of FM and AM func-tionality is partitioned. A NCO and mixer 2002 functionsfollowed by a down-sampling filter 2004 and an adjacentchannel filter 2006 are implemented on the SCC unit 908.The functions of a carrier frequency estimation 2008 andFM or AM demodulation 2010 are implemented on theSPC unit 910. The audio stream generated is bypassed

through the channel decoding cluster unit 914 to be sentto an audio DAC.[0068] FIG. 21 illustrates a DAB demodulation map-ping 2100 on the software defined radio subsystem 906of FIG. 9 according to an embodiment herein. The map-ping 2100 illustrates how the DAB demodulation on SDRsubsystem 906 of a digital audio broadcast functionalityis partitioned. A NCO and mixer 2102 functions are fol-lowed by IF to baseband conversion 2104, a down-sam-pling filter 2106, an adjacent channel filter 2108 and aninterpolation filter 2110 are implemented on the SCC unit908. The functions of a time domain synchronization2112, a fft 2114, a frequency domain synchronization2116, a channel estimation and correction 2118, a finesymbol synchronization 2120, a frame sync detection2122, a QPSK de-mapping 2124 and a time domain andfrequency domain deinterleaver 2126 are implementedon the SPC unit 910. A viterbi decoding 2128, a de-mul-tiplexing 2130 and de-randomization 2132 functions areperformed in the channel decoding cluster unit 914 togenerate audio stream.[0069] FIG. 22 illustrates the software defined radiotransmitter system 2200 that includes a software definedradio subsystem of FIG. 8 for universal TV signal mod-ulation according to an embodiment herein. The SDRtransmitter system 2200 includes (i) a Digital to AnalogConverter (DAC) 2202 and (ii) a software defined radiosubsystem 2204. The software defined radio subsystem2204 includes (i) a signal conditioning cluster 2206, (ii)a signal processing cluster 2208, (iii) a control cluster2210 and (iv) a channel encoding cluster 2212 to imple-ment a transmit path function. In such a case the channelencoding cluster 2212 performs a RS encoding, a con-volution encoding, a low-density parity-check encodingand an interleaving operation by collecting the requireddata transport stream input and produces encoded bits.The data from the channel encoding cluster 2212 ispassed to the signal processing cluster 2208 and fromsignal processing cluster 2208 to the signal conditioningcluster 2206. For instance, a Television (TV) signal trans-mitter is considered as an example.[0070] This is done by interchanging the componentsof a FIFO, a DMA and an Inter-cluster buffer as comparedto the previous (receiver) configurations across the clus-ters. Once the configuration are changed the signal pathgoes from channel encoding to signal processing andfinally to signal conditioning. The signal processing clus-ter 2208 maps the encoded bits to waveform and per-forms a framing, IFFT for OFDM based standards or per-forms a required modulation as per the broadcastingstandard. The signal processing cluster 2208 outputs amodulated baseband signal.[0071] The modulated baseband signal is transferredto the signal conditioning cluster 2206 for spectrum shap-ing and filtering. The spectrum shaped signal is transmit-ted either by optionally up-converting using a mixer andNCO combination or as is at baseband from the DFE submodule of the signal conditioning cluster 2206. The up-

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conversion can be performed externally before transmit-ting spectrum shaped signal for a baseband signal. Thisdata is passed through a digital to analog converter totransmit a baseband signal or an IF signal. In a similarmanner the transmitter path of other digital communica-tion standards can also be mapped and implementedusing the software defined radio subsystem 2200.[0072] FIG. 23 illustrates the software defined radiomodem 2300 that includes a software defined radio sub-system of FIG. 8 for universal TV signal modulation anddemodulation according to an embodiment herein.. Theusage of the SDR subsystem 800 for a universal modem2300 includes a signal processing cluster 2302A and2302B, a signal conditioning cluster 2304A and 2304B,a channel encoding cluster 2306, a channel decodingcluster 2308, a digital to analog convertor 2310, an upconvertor 2312, a transmit antenna 2314, a receive an-tenna 2316, a tuner 2318, an analog to digital convertor2320, a signal conditioning cluster 2304B, and a signalprocessing cluster 2302B. The proposed SDR subsys-tem that includes a signal processing clusters 2302A and2302B and signal conditioning clusters 2304A and 2304Bcan be used along with an additional channel encodingcluster 2306 and channel decoding clusters 2308 to im-plement a universal modulator and demodulator func-tionality. For instance, a Television (TV) signal modemis considered as an example.[0073] In this scheme, the transmit path and receivepath are shown. The transmit path includes outgoing databeing processed via a channel encoding cluster 2306,followed by the signal processing cluster 2302A and fi-nally sent out after being processed by the signal condi-tioning cluster 2304A. This outgoing signal is fed to adigital to analog convertor 2310 which is up-convertedand sent via the transmit antenna 2314. The receive pathincludes incoming signals from an antenna 2316 whichpass through the tuner 2318 to obtain Intermediate fre-quency or zero IF signals. These signals are digitizedusing an analog to digital converter 2320 to generate realor complex samples. As explained in previous sectionsthe real or complex signals are processed by the signalconditioning cluster 2304B for sample processing fol-lowed by the signal processing cluster 2302B for symbolprocessing and finally de-mapped to generate bits. Thegenerated bits are passed through a channel decodingcluster 2308 to remove errors process final data bits.[0074] FIG. 24 is a flow chart illustrating a method ofperforming universal TV signal demodulation in the SDRreceiver system of FIG. 9 according to an embodimentherein. In step 2402, a Television (TV) signal is receivedat tuner and converted into one of a zero IntermediateFrequency (IF) signal, a low IF signal or a standard IFsignal. In step 2404, the zero IF signal or low IF signalor standard IF signal is converted into a digital signal. Instep 2406, the digital signal is down converted into a com-plex baseband signal. In step 2408, a FIR filtering, an IIRfiltering, an interpolation and sample rate conversion fil-tering are performed on the complex baseband signal.

In step 2410, a demodulation, a channel estimation, achannel correction and a de-mapping are performed onthe complex baseband signal to produce decision bits.In step 2412, a viterbi decoding, a Reed Solomon (RS)decoding and a Low-Density-Parity-Check (LDPC) de-coding are performed on the decision bits and obtain adecoded data.[0075] FIG. 25 is a flow chart illustrating a method ofperforming universal TV signal modulation in the SDRtransmitter system of FIG. 22 according to an embodi-ment herein. In step 2502, a viterbi encoding, a ReedSolomon (RS) encoding, a convolution encoding and aLow-Density-Parity-Check (LDPC) encoding are per-formed on a transport stream to produce encoded bits.In step 2504, a modulation, a framing and mapping op-erations are performed on the encoded bits to producea baseband signal. In step 2506, an up-conversion anda pulse shaping is performed on the baseband signal toproduce a digital Intermediate Frequency (IF) signal. Instep 2508, the digital IF signal is converted into an analogsignal.[0076] FIG. 26 illustrates a graphical comparison 2600of an incremental cost of ownership versus a number ofTV standards supported for a system integration ap-proach, an ASIC integration approach as compared tothe proposed software defined radio platform of FIG. 9according to an embodiment herein. As the number ofstandards is increased, the incremental cost of owner-ship for the system integration approach increases rap-idly. The incremental cost of ownership for the ASIC in-tegration approach increases in a linearly. However, inthe case of the proposed software defined radio platform,the incremental cost of ownership increases only mar-ginally with an increased in the number of standards.[0077] The SDR Subsystem has the ability to interfaceto Zero-IF, Low-IF and Standard-IF signals from the RFtuner. This capability is enabled by the presence of aNumerically Controlled Oscillator (NCO) which is switch-able between the ADC subsystem and the signal condi-tioning CPU. For the case when the RF tuner generatesa zero-IF signal the NCO is switched out of the path, thusallowing the IQ ADC’s digitized samples to be directlyconsumed by the signal conditioning CPU. For the casewhen the tuner is either Low-IF or Standard-IF the NCOis switched into the path between the ADC and the signalconditioning CPU. The NCO is fed with the appropriatenumerical value which enables the frequency translationof the spectrum of the input signal to a baseband fre-quency centred about zero. The resulting signal is nowconsumed by the signal conditioning CPU for furtherprocessing steps.[0078] The combination of the various DSP Proces-sors in single of multiple instances (namely the signalconditioning CPU (SCON CPU)) is optimized for highspeed sample rate processing. The signal processingCPU (SPROC CPU) is adapted for a block based Signalprocessing. The process of optimizing the SCON CPUand the SPROC CPU enables to handle all the signal

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processing required for analog TV signal demodulationup to generation of Sound Intermediate Frequency (SIF)signal and Complex Video Baseband Signal (CVBS) andin case of digital TV standard demodulation up to de-mapper outputs. These generated bits can be subse-quently fed to an Inner and Outer Forward Error Correc-tion block to generate a Transport Stream. The ExecutionUnits of the different cores and the unique partitioning ofthe different signal processing tasks enable to achievedemodulation of TV Standards as well as Radio Stand-ards such as Amplitude Modulation (AM), FrequencyModulation (FM) and Digital Audio Broadcasting (DAB).[0079] The architecture of the SDR Subsystem alongwith the flexible memory interconnects and multiple Sig-nal Conditioning CPUs enables support of higher inputsample rates thus allowing any kind of ADC rates to besupported. In addition, multiple signal processing CPUsenables support of arbitrarily high symbol rates. Hencethis scalable architecture ensures support of all digitaland analog TV standards. The SDR subsystem’s com-ponents include the signal conditioning CPU’s. TheSCON CPU is a VLIW architecture consisting of 4 exe-cution slots namely the arithmetic slot, logic slot, filter &scalar load-store unit with broadcast capability.[0080] The SDR subsystem’s components consist ofa Least Mean Square (LMS) hardware accelerator whichis used for both adaptive and non-adaptive filtering andis tightly coupled to the SPROC CPU’s cordic unit fordata transfer. The adaptive filtering is used for time do-main equalizers in single carrier standards and long echosuppression in multicarrier standards. In case of analogTV standards this unit is used for additional FIR filteringat very high sampling rates. In combination with a channelencoder cluster which is capable of performing encodingfunction for RS, viterbi, LDPC and interleaving, the signalconditioning CPU and the signal processing CPU per-form a transmit path or modulator function. The instruc-tion set architecture of signal processing CPU makes itideal for performing any modulation functions.[0081] In addition, the Instruction set architecture ofsignal conditioning cluster makes it suitable for all kindsof filtering operations thus enabling it to perform spectralshaping and stage before the signal is transmitted. Thecombination of NCO and mixer up-converts the desiredsignal to required frequency band. Hence if the desiredsignal is passed through a digital to analog convertor, anIF or baseband output can be obtained. The SDR sub-system components of signal processing (SPROC) clus-ter and signal conditioning (SCON) Cluster can be reusedfor both transmit and receive functions to be effectivelyused for universal modulation and demodulation. Whenused in conjunction with a control CPU and channel de-coding and channel encoding cluster functions this ena-bles to build a universal modem for supporting digitalcommunication standards.[0082] The software defined radio subsystem 906 en-ables a single global TV chassis since it is able to de-modulate all digital TV and analog TV standards. The

system cost reduction for a global TV chassis is up to a20% cost reduction per chassis on a $50 bill of material.Thereby, margins are maintained through feature addi-tion. As an example, radio Standards such as FM, AMand DAB can be easily supported without any additionalcost. This reduces cost by preventing additional rede-signs or device re-spins. The software defined radio sub-system 906 allows support of future standards thus en-abling faster time to market of TV OEMs. In addition, itis designed to demodulate all the broadcast TV standardsfor different types of media and regions. The modulationcapability using these components may be further ex-tended to design a universal modem.[0083] The software-defined radio subsystem is a ra-dio communication system where components that havebeen typically implemented in hardware are instead im-plemented by means of software on a personal computeror embedded computing devices. Significant amounts ofsignal processing are handed over to the general-pur-pose processor, rather than being done in special-pur-pose hardware. Such a design produces a radio whichcan receive and transmit widely different radio protocolsbased solely on the software used.[0084] The software defined radio subsystem enablesfield upgrade of TV platforms based on region specificand terrain specific conditions, which is a not usually pos-sible using fixed hardware solution. This reduces cost bypreventing additional redesigns or device re-spins. Forexample if some channel conditions in Nordic countriesare not met or some Brazil profiles are not met, there isa better chance of supporting it on such SDR subsystemusing a software update. The SDR building blocks canbe used as a minimum of 2 instances or more multiples,consisting of combinations of transmitter and receiverSDR to implement universal modem functionality.[0085] While the foregoing description is exemplary ofthe preferred embodiments, those of ordinary skill in therelevant arts will recognize many variations, alterations,modifications, substitutions and the like as are readilypossible, especially in light of this description, the accom-panying drawings and the claims drawn hereto. The de-scription describes exemplary embodiments particularlyin relation to multiple Analog as well as Digital Television(TV) standards, however the SDR subsystem and themethods for modulation, demodulation and trans-modu-lation disclosed herein can be implemented for any othermultiple communication standards as envisaged by aperson of ordinary skill in the art. In any case, the fore-going detailed description should not be construed as alimitation, which is limited only by the claims appendedhereto.

Claims

1. A Software Defined Radio, SDR, subsystem (800)capable of supporting multiple communicationstandards, for modulation and demodulation of an

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input signal, said SDR subsystem (800) comprising:

a Signal Conditioning Cluster, SCC, unit (802)comprising a plurality of Signal Conditioning,SCON, CPUs (1012) adapted to perform a sam-ple based signal processing for said modulationand said demodulation;wherein said SCC unit (802) is adapted to:

(i) receive a baseband signal from a SignalProcessing Cluster, SPC, unit (804) of theSDR subsystem and produce a digital Inter-mediate Frequency, (IF), signal for saidmodulation, and(i) receive an IF signal from a tuner and pro-duce a complex baseband signal for saiddemodulation;

said SPC unit (804) comprising a plurality of Sig-nal Processing, SPROC, CPUs (1108) adaptedto perform a block based signal processing,wherein said SPC unit (804) is adapted to:

(i) receive encoded bits from a Channel Co-dec Cluster, CCC, unit (806) of the SDRsubsystem and produce said baseband sig-nal for said modulation, and(ii) receive said complex baseband signalfrom said SCC (802) unit and produce de-cision bits for said demodulation;

said CCC unit (806) adapted to perform a chan-nel encoding and a channel decoding, whereinsaid CCC unit (806) is adapted to:

(i) receive said input signal and producesaid encoded bits for said modulation, and(ii) receive said decision bits from said SPCunit (804) and produce a decoded data forsaid demodulation.

2. The SDR subsystem (800) of claim 1, wherein saidSCC (802) unit is adapted to:

(i) receive said baseband signal from said SPCunit (804) and produce said digital IntermediateFrequency, IF, signal based on a first commu-nication standard for a trans-modulation, and(ii) receive said IF signal from said tuner andproduce said complex baseband signal basedon a second communication standard for saidtrans-modulation.

3. The SDR subsystem (800) of claim 2, wherein saidSPC unit (804) is adapted to:

(i) receive said encoded bits from said CCC unit(806) and produce said baseband signal based

on said first communication standard for saidtrans-modulation, and(ii) receive said complex baseband signal fromsaid SCC (802) unit and produce said decisionbits based on said second communicationstandard for said trans-modulation.

4. The SDR subsystem (800) of claim 1, wherein saidmultiple communication standards comprise analogand digital communication standards, wherein saidSCC (802) unit further comprises:

a Digital Front End, DFE, unit (1002) that com-prises:

a Numerically Controlled Oscillator, NCO,(1006) adapted to operate at a sample-ratefrequency and adapted to perform a digitaldown-conversion of said IF signal into saidcomplex baseband signal;a plurality of Signal Conditioning, SCON,CPUs (1012) adapted for a sample basedsignal processing and that are adapted to:

(i) perform a pulse shaping of saidbaseband signal from said SPC unit(804) for said modulation, and(ii) perform a Finite Impulse Response,FIR, filtering, an Infinite Impulse Re-sponse, IIR, filtering, an interpolation,and a sample rate conversion filteringon said complex baseband signal fromsaid NCO (1006) for said demodula-tion; and

a memory sub system that comprises:

a store-and-forward buffer or a cut-throughbuffer for storing said complex basebandsignal or said baseband signal; anda Direct Memory Access, DMA, unit (1030)that extracts data that corresponds to saidcomplex baseband signal or said basebandsignal from said store-and-forward buffer orsaid cut -through buffer based on a pro-grammed threshold.

5. The SDR subsystem (800) of claim 1, wherein saidSPC unit (804) comprises:

a plurality of Signal Processing, SPROC, CPUs(1108) adapted for a block based signalprocessing and that are adapted to:

(i) perform a modulation, a framing and amapping on said encoded bits from saidCCC unit (806) to produce said basebandsignal for said modulation of said input sig-

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nal, and(ii) perform a demodulation, a channel esti-mation, a channel correction, and de-map-ping of symbols on said complex basebandsignal received from said SCC unit (802) toproduce said decision bits for said demod-ulation of said input signal;

a Least Mean Squares, LMS, coprocessor(1110) coupled to said plurality of SPROC CPUs(1108), wherein said LMS coprocessor (1110)is adapted to perform an adaptive feedback andfeed-forward FIR filtering, a coefficient or tap ad-aptation, and a high speed FIR filtering operationon multiple streams; anda memory subsystem that comprises:

an Inter -Cluster Buffer, ICB, (1112);a Shared Memory Subsystem, SHM, (1114)that is connected across said plurality ofSPROC CPUs (1108) wherein said SHM isused as a buffer for storing and exchangingof computed results between said pluralityof SPROC CPUs (1108); anda Direct Memory Access, DMA, unit thatprocesses a transfer of a processed data tosaid CCC unit (806).

6. The SDR subsystem (800) of claim 5, wherein saidplurality of SPROC CPUs (1108) comprises:

a complex arithmetic slot that performs at leastone of real and complex arithmetic operations,wherein said operations include N -way SingleInstruction Multiple Data, SIMD, operations,wherein said complex arithmetic slot supportsFast Fourier Transform, FFT, butterfly opera-tions; anda cordic slot that generates (i) sine and cosinevalues and (ii) magnitude and phases of com-plex signals, wherein said cordic slot is coupledto said LMS coprocessor to perform cycle effi-cient read and write operations during an equal-izer operation, wherein said cordic slot furtherperforms N-way arithmetic, logic and extract op-erations.

7. The SDR subsystem (800) of claim 1, wherein saidCCC unit (806) is adapted to:

(i) receive said input signal and perform at leastone of a viterbi encoding, a Reed Solomon, RS,encoding, and a Low -Density Parity -Check, LD-PC, to produce said encoded bits for said mod-ulation, and(ii) receive said decision bits from said SPC unit(804) and perform at least one of a viterbi de-coding, a Reed Solomon, RS, decoding, and a

Low-Density Parity-Check, LDPC, to producesaid decoded data for said demodulation.

8. A method for demodulating an input signal in soft-ware defined radio, SDR, subsystem (800) that iscapable of supporting multiple communicationstandards, said method comprising:

receiving, at a Signal Conditioning Cluster,SCC, unit (802) of said SDR subsystem (800),said input signal from a tuner and convertingsaid input signal into one of a zero IntermediateFrequency, (IF), signal, a low IF signal, and astandard IF signal, wherein said SCC unit (802)comprises a plurality of Signal ConditioningSCON, CPUs (1012) adapted for a samplebased signal processing;converting by said SCC unit (802), said one ofsaid zero IF signal, said low IF signal, and saidstandard IF signal into a digital signal;down converting by said SCC unit (802), saiddigital signal into a complex baseband signal;performing by said SCC unit (802), a FIR filter-ing, an IIR filtering, an interpolation and a samplerate conversion filtering on said complex base-band signal to produce a filtered complex base-band signal;performing by a Signal Processing Cluster,SPC, unit (804) of said SDR subsystem (800),a demodulation, a channel estimation, a channelcorrection, and a de-mapping on said filteredcomplex baseband signal based on said multi-ple communication standards to obtain decisionbits, wherein said SPC unit (804) comprises aplurality of Signal Processing, SPROC, CPUs(1108) adapted to perform a block based signalprocessing; andperforming by a Channel Codec Cluster, CCC,unit (806) of said SDR subsystem (800), at leastone of a Viterbi decoding, a Reed Solomon, RS,decoding, and a Low -Density Parity-Check, LD-PC, decoding on said decision bits to obtain de-coded data.

9. The method of claim 8, wherein said SCON CPU,(1012) comprises:

a load -store slot that performs loading and stor-ing of said complex baseband signal to enablefiltering operation;a filter slot that receives said complex basebandsignal from said load -store slot and adapted toperforms said FIR filtering, said IIR filtering, saidinterpolation and said sample rate conversionfiltering; andan arithmetic slot that adapted to performs arith-metic operations required for filtering operation.

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10. The method of claim 8, wherein said SPROC CPU(1108) comprises:

a complex arithmetic slot and a cordic slot thatadapted to perform said demodulation, saidchannel estimation, said channel correction,and said de -mapping on said filtered complexbaseband signal.

11. A method for modulating an input signal in a softwaredefined radio, SDR, subsystem (800) that is capableof supporting multiple communication standards,said method comprising:

performing by a Channel Codec Cluster, CCC,unit (806) of said SDR subsystem (800) at leastone of a viterbi encoding, a Reed Solomon, RS,encoding, convolution encoding and a Low-Density Parity-Check(LDPC) encoding on saidinput signal to produce encoded bits;performing by a Signal Processing Cluster,SPC, unit (804) of said SDR subsystem (800) amodulation, a framing, and a mapping on saidencoded bits based on said multiple communi-cation standards to obtain baseband signals,wherein said SPC unit (804) comprises a plural-ity of Signal Processing, SPROC, CPUs (1108)adapted to perform a block based signalprocessing;performing by a Signal Conditioning Cluster,SCC, unit (802) of said SDR subsystem (800)an up -conversion and a pulse shaping of saidbaseband signals to produce a digital IF signal,wherein said SCC unit (802) comprises a plu-rality of Signal Conditioning SCON, CPUs(1012) adapted for a sample based signalprocessing; andconverting by said SCC unit (802) said digital IFsignal into an analog signal.

12. The method of claim 11, wherein said SPROC CPU(1108) comprises:

a complex arithmetic slot and a cordic slot thatadapted to perform said modulation, said fram-ing and said mapping on said encoded bits.

13. The method of claim 11, further comprising perform-ing, using a load -store slot, a filter slot, and an arith-metic slot of said Signal Conditioning CPU, SCONCPU, said up-conversion and said pulse shaping ofsaid baseband signals.

Patentansprüche

1. SDR- (Software Defined Radio, softwaredefinierterFunk) Subsystem (800), das in der Lage ist, mehrere

Kommunikationsstandards zu unterstützen, für Mo-dulation und Demodulation eines Eingangssignals,wobei das SDR-Subsystem (800) umfasst:

eine SCC- (Signal Conditioning Cluster, Signal-aufbereitungscluster) Einheit (802), die eineMehrzahl von SCON- (Signal Conditioning, Si-gnalaufbereitung) CPUs (1012) umfasst, wel-che dafür ausgelegt sind, eine stichprobenge-stützte Signalverarbeitung für die Modulationbzw. Demodulation auszuführen;wobei die SCC-Einheit (802) ausgelegt ist zum:

(i) Empfangen eines Basisbandsignals voneiner SPC-(Signal Processing Cluster, Sig-nalverarbeitungscluster) Einheit (804) desSDR-Subsystems und Erzeugen eines di-gitalen IF- (Intermediate Frequency, Zwi-schenfrequenz) Signals für die Modulation,und(ii) Empfangen eines IF-Signals von einemTuner und Erzeugen eines komplexen Ba-sisbandsignals für die Demodulation;

wobei die SPC-Einheit (804) eine Mehrzahl vonSPROC-(Signal Processing, Signalverarbei-tung) CPUs (1108) umfasst, welche dafür aus-gelegt sind, eine blockbasierte Signalverarbei-tung auszuführen, wobei die SPC-Einheit (804)ausgelegt ist zum:

(i) Empfangen codierter Bits von einer CCC-(Channel Codec Cluster, Kanalcodecclus-ter) Einheit (806) des SDR-Subsystems undErzeugen des Basisbandsignals für die Mo-dulation, und(ii) Empfangen des komplexen Basisband-signals von der SCC-Einheit (802) und Er-zeugen von Entscheidungsbits für die De-modulation;

wobei die CCC-Einheit (806) dafür ausgelegt ist,eine Kanalcodierung und eine Kanaldecodie-rung auszuführen,wobei die CCC-Einheit (806) ausgelegt ist zum:

(i) Empfangen des Eingangssignals und Er-zeugen der codierten Bits für die Modulati-on, und(ii) Empfangen der Entscheidungsbits vonder SPC-Einheit (804) und Erzeugen derdecodierten Daten für die Demodulation.

2. SDR-Subsystem (800) nach Anspruch 1, wobei dieSCC-Einheit (802) ausgelegt ist zum:

(i) Empfangen des Basisbandsignals von derSPC-Einheit (804) und Erzeugen des digitalen

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IF- (Intermediate Frequency, Zwischenfre-quenz) Signals basierend auf einem erstenKommunikationsstandard für eine Transmodu-lation, und(ii) Empfangen des IF-Signals vom Tuner undErzeugen des komplexen Basisbandsignals ba-sierend auf einem zweiten Kommunikations-standard für die Transmodulation.

3. SDR-Subsystem (800) nach Anspruch 2, wobei dieSPC-Einheit (804) ausgelegt ist zum:

(i) Empfangen der codierten Bits von der CCC-Einheit (806) und Erzeugen des Basisbandsig-nals basierend auf dem ersten Kommunikati-onsstandard für die Transmodulation, und(ii) Empfangen des komplexen Basisbandsig-nals von der SCC-Einheit (802) und Erzeugender Entscheidungsbits basierend auf dem zwei-ten Kommunikationsstandard für die Transmo-dulation.

4. SDR-Subsystem (800) nach Anspruch 1, wobei diemehreren Kommunikationsstandards analoge unddigitale Kommunikationsstandards umfassen, wo-bei die SCC-Einheit (802) ferner umfasst:

eine DFE- (Digital Front End, digitales Frontend)Einheit (1002), die umfasst:

einen NCO (Numerically Controlled Oscil-lator, numerisch gesteuerter Oszillator)(1006), der dafür ausgelegt ist, mit einer Ab-tastratenfrequenz zu arbeiten, und dafürausgelegt ist, eine digitale Abwärtswand-lung des IF-Signals in das komplexe Basis-bandsignal auszuführen; eine Mehrzahlvon SCON- (Signal Conditioning, Signal-aufbereitung) CPUs (1012), die dafür aus-gelegt sind, eine stichprobengestützte Sig-nalverarbeitung auszuführen, und die aus-gelegt sind zum:

(i) Ausführen einer Impulsformung desBasisbandsignals von der SPC-Einheit(804) für die Modulation, und(ii) Ausführen einer FIR- (Finite ImpulseResponse, Finite Impulsantwort) Filte-rung, einer IIR- (Infinite Impulse Re-sponse, Infinite Impulsantwort) Filte-rung, einer Interpolation und einerAbtastratenkonvertierungsfilterungdes komplexen Basisbandsignals vomNCO (1006) für die Demodulation;

und

ein Speichersubsystem, das umfasst:

einen Store-and-Forward- (Teilstreckenü-bertragung) Puffer oder einen Cut-Th-rough- (Durchleitung) Puffer zum Spei-chern des komplexen Basisbandsignalsoder des Basisbandsignals; undeine DMA- (Direct Memory Access, Direkt-speicherzugriff) Einheit (1030), die Daten,welche dem komplexen Basisbandsignalbzw. dem Basisbandsignal entsprechen,aus dem Store-and-Forward-Puffer oderdem Cut-Through-Puffer extrahiert, basie-rend auf einem programmierten Schwell-wert.

5. SDR-Subsystem (800) nach Anspruch 1, wobei dieSPC-Einheit (804) umfasst:

eine Mehrzahl von SPROC- (Signal Processing,Signalverarbeitung) CPUs (1108), die dafürausgelegt sind, eine blockbasierte Signalverar-beitung auszuführen, und die ausgelegt sindzum:

(i) Ausführen einer Modulation, einer Rah-mung und einer Zuordnung der codiertenBits von der CCC-Einheit (806), um das Ba-sisbandsignal für die Modulation des Ein-gangssignals zu erzeugen, und(ii) Ausführen einer Demodulation, einerKanalschätzung, einer Kanalkorrektur undeiner Aufhebung der Zuordnung der Sym-bole des komplexen Basisbandsignals, dasvon der SCC-Einheit (802) empfangen wird,um die Entscheidungsbits für die Demodu-lation des Eingangssignals zu erzeugen;

einen LMS- (Least Mean Squares, kleinste mitt-lere Fehlerquadrate) Coprozessor (1110), dermit der Mehrzahl von SPROC-CPUs (1108) ge-koppelt ist, wobei der LMS-Coprozessor (1110)dafür ausgelegt ist, eine adaptive Rückkopp-lungs- und Vorwärtskopplungs-FIR-Filterung,eine Koeffizienten- oder Tap-Anpassung undeine Hochgeschwindigkeits-FIR-Filteroperationan mehreren Strömen auszuführen; undein Speichersubsystem, das umfasst:

einen ICB (Inter-Cluster Buffer, clusterüber-greifender Puffer) (1112);ein SHM- (Shared Memory, gemeinsam ge-nutzter Speicher) Subsystem (1114), dasmit der Mehrzahl von SPROC-CPUs (1108)verbunden ist, wobei das SHM als Pufferzum Speichern und Austauschen von be-rechneten Ergebnissen zwischen der Mehr-zahl von SPROC-CPUs (1108) genutztwird; undeine DMA- (Direct Memory Access, Direkt-

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speicherzugriff) Einheit, die eine Übertra-gung von verarbeiteten Daten an die CCC-Einheit (806) verarbeitet.

6. SDR-Subsystem (800) nach Anspruch 5, wobei dieMehrzahl von SPROC-CPUs (1108) umfasst:

einen Complex-Arithmetic- (komplexe Arithme-tik) Slot, der wenigstens eine von realen undkomplexen Rechenoperationen ausführt, wobeidie Operationen N-Wege-SIMD- (Single In-struction Multiple Data, eine Instruktion, mehre-re Daten) -Operationen umfassen,wobei der Complex-Arithmetic-Slot Schmetter-ling-Operationen der schnellen Fourier-Trans-formation (Fast Fourier Transform, FFT) unter-stützt; undeinen Cordic-Slot, der (i) Sinus- und Cosinus-Werte und (ii) Größe und Phasen komplexer Si-gnale erzeugt, wobei der Cordic-Slot mit demLMS-Coprozessor gekoppelt ist, um zykluseffi-ziente Lese- und Schreiboperationen währendeiner Entzerreroperation auszuführen, wobeider Cordic-Slot ferner N-Wege-Arithmetik-, -Lo-gik- und -Extraktionsoperationen ausführt.

7. SDR-Subsystem (800) nach Anspruch 1, wobei dieCCC-Einheit (806) ausgelegt ist zum:

(i) Empfangen des Eingangssignals und Aus-führen wenigstens eines von einer Viterbi-Co-dierung, einer RS-(Reed Solomon) Codierungund einer LDPC- (Low-Density Parity-Check,Paritätsprüfung mit niedriger Dichte), um die co-dierten Bits für die Modulation zu erzeugen, und(ii) Empfangen der Entscheidungsbits von derSPC-Einheit (804) und Ausführen wenigstenseines von einer Viterbi-Decodierung, einer RS-(Reed Solomon) Decodierung und einer LDPC(Low-Density Parity-Check, Paritätsprüfung mitniedriger Dichte), um die decodierten Daten fürdie Demodulation zu erzeugen.

8. Verfahren für die Demodulation eines Eingangssig-nals in einem SDR- (Software Defined Radio, soft-waredefinierter Funk) Subsystem (800), das in derLage ist, mehrere Kommunikationsstandards zu un-terstützen, wobei das Verfahren umfasst:

Empfangen, an einer SCC- (Signal ConditioningCluster, Signalaufbereitungscluster) Einheit(802) des SDR-Subsystems (800), des Ein-gangssignals von einem Tuner und Umwandelndes Eingangssignals in eines von einem Null-IF- (Intermediate Frequency, Zwischenfre-quenz) Signal, einem niedrigen IF-Signal undeinem Standard-IF-Signal, wobei die SCC-Ein-heit (802) eine Mehrzahl von SCON- (Signal

Conditioning, Signalaufbereitung) CPUs (1012)umfasst, welche für eine stichprobengestützteSignalverarbeitung ausgelegt sind;Umwandeln, durch die SCC-Einheit (802), deseinen des Null-IF-Signals, des niedrigen IF-Si-gnals und des Standard-IF-Signals in ein Digi-talsignal;Abwärtswandeln, durch die SCC-Einheit (802),des Digitalsignals in ein komplexes Basisband-signal;Ausführen, durch die SCC-Einheit (802), einerFIR-Filterung, einer IIR-Filterung, einer Interpo-lation und einer Abtastratenkonvertierungsfilte-rung des komplexen Basisbandsignals, um eingefiltertes komplexes Basisbandsignal zu er-zeugen;Ausführen, durch eine SPC- (Signal ProcessingCluster, Signalverarbeitungscluster) Einheit(804) des SDR-Subsystems (800), einer Demo-dulation, einer Kanalschätzung, einer Kanalkor-rektur und einer Aufhebung der Zuordnung derSymbole des gefilterten komplexen Basisband-signals basierend auf den mehreren Kommuni-kationsstandards, um Entscheidungsbits zu er-halten, wobei die SPC-Einheit (804) eine Mehr-zahl von SPROC- (Signal Processing, Signal-verarbeitung) CPUs (1108) umfasst, welche da-für ausgelegt sind, eine blockbasierte Signalver-arbeitung auszuführen; undAusführen, durch eine CCC- (Channel CodecCluster, Kanalcodeccluster) Einheit (806) desSDR-Subsystems (800), wenigstens eines voneiner Viterbi-Decodierung, einer RS- (Reed So-lomon) Decodierung und einer LDPC-(Low-Density Parity-Check, Paritätsprüfung mit nied-riger Dichte) Decodierung der Entscheidungs-bits, um decodierte Daten zu erhalten.

9. Verfahren nach Anspruch 8, wobei die SCON-CPU(1012) umfasst:

einen Load-Store- (Laden-Speichern-) Slot, derdas Laden und Speichern des komplexen Ba-sisbandsignals ausführt, um eine Filteroperati-on zu ermöglichen;einen Filter-Slot, der das komplexe Basisband-signal vom Load-Store-Slot empfängt und dafürausgelegt ist, die FIR-Filterung, die IIR-Filte-rung, die Interpolation unddie Abtastratenkonvertierungsfilterung auszu-führen; und einen Arithmetik-Slot, der dafür aus-gelegt ist, die für die Filterung erforderlichen Re-chenoperationen auszuführen.

10. Verfahren nach Anspruch 8, wobei die SPROC-CPU(1108) umfasst:

einen Complex-Arithmetic-Slot und einen Cor-

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dic-Slot, die dafür ausgelegt sind, die Demodu-lation, die Kanalschätzung, die Kanalkorrekturund die Aufhebung der Zuordnung des gefilter-ten komplexen Basisbandsignals auszuführen.

11. Verfahren für die Modulation eines Eingangssignalsin einem SDR- (Software Defined Radio, software-definierter Funk) Subsystem (800), das in der Lageist, mehrere Kommunikationsstandards zu unter-stützen, wobei das Verfahren umfasst:

Ausführen, durch eine CCC- (Channel CodecCluster, Kanalcodeccluster) Einheit (806) desSDR-Subsystems (800), wenigstens eines voneiner Viterbi-Codierung, einer RS- (Reed Solo-mon) Codierung, einer Faltungscodierung undeiner LDPC- (Low-Density Parity-Check, Pari-tätsprüfung mit niedriger Dichte) Codierung desEingangssignals, um codierte Bits zu erzeugen;Ausführen, durch eine SPC- (Signal ProcessingCluster, Signalverarbeitungscluster) Einheit(804) des SDR-Subsystems (800), einer Modu-lation, einer Rahmung und einer Zuordnung dercodierten Bits basierend auf den mehrerenKommunikationsstandards, um Basisbandsig-nale zu erhalten, wobei die SPC-Einheit (804)eine Mehrzahl von SPROC- (Signal Processing,Signalverarbeitung) CPUs (1108) umfasst, wel-che dafür ausgelegt sind, eine blockbasierte Si-gnalverarbeitung auszuführen;Ausführen, durch eine SCC- (Signal Conditio-ning Cluster, Signalaufbereitungscluster) Ein-heit (802) des SDR-Subsystems (800), einerAufwärtswandlung und einer Impulsformungder Basisbandsignale, um ein digitales IF-Signalzu erzeugen, wobei die SCC-Einheit (802) eineMehrzahl von SCON- (Signal Conditioning, Si-gnalaufbereitung) CPUs (1012) umfasst, wel-che für eine stichprobengestützte Signalverar-beitung ausgelegt sind; undUmwandeln, durch die SCC-Einheit (802), desdigitalen IF-Signals in ein Analogsignal.

12. Verfahren nach Anspruch 11, wobei die SPROC-CPU (1108) umfasst:

einen Complex-Arithmetic-Slot und einen Cor-dic-Slot, die dafür ausgelegt sind, die Modulati-on, Rahmung und Zuordnung der codierten Bitsauszuführen.

13. Verfahren nach Anspruch 11, ferner umfassend dasAusführen, mittels eines Load-Store-Slots, eines Fil-ter-Slots und eines Arithmetik-Slots der SCON-CPU(Signal Conditioning CPU, Signalaufbereitungs-CPU), der Aufwärtswandlung und der Impulsfor-mung der Basisbandsignale.

Revendications

1. Sous-système de radio définie par logiciel, SDR,(800) capable de prendre en charge de multiples nor-mes de communication, pour la modulation et la dé-modulation d’un signal d’entrée, ledit sous-systèmeSDR (800) comprenant :

une unité de groupe de conditionnement de si-gnal, SCC, (802) comprenant une pluralité d’uni-tés centrales de conditionnement de signal,SCON, (1012) adaptées pour exécuter un trai-tement de signal par échantillons pour ladite mo-dulation et ladite démodulation ;dans lequel ladite unité SCC (802) est adaptéepour :

(i) recevoir un signal de bande de base àpartir d’une unité de groupe de traitementde signal, SPC, (804) du sous-systèmeSDR et produire un signal de fréquence in-termédiaire (IF) numérique pour ladite mo-dulation, et(ii) recevoir un signal IF à partir d’un synto-niseur et produire un signal de bande debase complexe pour ladite démodulation ;

ladite unité SPC (804) comprenant une pluralitéd’unités centrales de traitement de signal,SPROC, (1108) adaptées pour exécuter un trai-tement de signal par blocs, dans lequel laditeunité SPC (804) est adaptée pour :

(i) recevoir des bits codés à partir d’une uni-té de groupe de codec de canal, CCC, (806)du sous-système SDR et produire ledit si-gnal de bande de base pour ladite modula-tion, et(ii) recevoir ledit signal de bande de basecomplexe à partir de ladite unité SCC (802)et produire des bits de décision pour laditedémodulation ;

ladite unité CCC (806) étant adaptée pour exé-cuter un codage de canal et un décodage decanal, ladite unité CCC (806) étant adaptéepour :

(i) recevoir ledit signal d’entrée et produirelesdits bits codés pour ladite modulation, et(ii) recevoir lesdits bits de décision à partirde ladite unité SPC (804) et produire desdonnées décodées pour ladite démodula-tion.

2. Sous-système SDR (800) selon la revendication 1,dans lequel ladite unité SCC (802) est adaptée pour :

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(i) recevoir ledit signal de bande de base à partirde ladite unité SPC (804) et produire ledit signalde fréquence intermédiaire IF numérique enfonction d’une première norme de communica-tion pour une trans-modulation, et(ii) recevoir ledit signal IF à partir dudit syntoni-seur et produire ledit signal de bande de basecomplexe en fonction d’une seconde norme decommunication pour ladite trans-modulation.

3. Sous-système SDR (800) selon la revendication 2,dans lequel ladite unité SPC (804) est adaptée pour :

(i) recevoir lesdits bits codés à partir de laditeunité CCC (806) et produire ledit signal de bandede base en fonction de ladite première normede communication pour ladite trans-modulation,et(ii) recevoir ledit signal de bande de base com-plexe à partir de ladite unité SCC (802) et pro-duire lesdits bits de décision en fonction de laditeseconde norme de communication pour laditetrans-modulation.

4. Sous-système SDR (800) selon la revendication 1,dans lequel lesdites multiples normes de communi-cation comprennent des normes de communicationanalogiques et numériques, dans lequel ladite unitéSCC (802) comprend en outre : une unité de récep-tion frontale numérique, DFE, (1002) qui comprend :

un oscillateur commandé numériquement,NCO, (1006) adapté pour fonctionner à une fré-quence d’échantillonnage et adapté pour exé-cuter une conversion numérique par abaisse-ment de fréquence dudit signal IF en ledit signalde bande de base complexe ;une pluralité d’unités centrales de conditionne-ment de signal, SCON, (1012) adaptées pourun traitement de signal par échantillons et adap-tées pour :

(i) exécuter une mise en forme d’impulsionsdudit signal de bande de base provenant deladite unité SPC (804) pour ladite modula-tion, et(ii) exécuter un filtrage à réponse impulsion-nelle finie, FIR, un filtrage à réponse impul-sionnelle infinie, IIR, une interpolation et unfiltrage par conversion de fréquenced’échantillonnage sur ledit signal de bandede base complexe provenant dudit oscilla-teur NCO (1006) pour ladite démodulation ;et

un sous-système de mémoire qui comprend :

un tampon de mémorisation et de renvoi ou

un tampon de passage direct pour mémo-riser ledit signal de bande de base comple-xe ou ledit signal de bande de base ;une unité d’accès direct à la mémoire, DMA,(1030) qui extrait les données qui corres-pondent audit signal de bande de base com-plexe ou audit signal de bande de base àpartir dudit tampon de mémorisation et deou dudit tampon de passage direct en fonc-tion d’un seuil programmé.

5. Sous-système SDR (800) selon la revendication 1,dans lequel ladite unité SPC (804) comprend :

une pluralité d’unités centrales de traitement designal, SPROC, (1108) adaptées pour un traite-ment de signal par blocs et adaptées pour :

(i) exécuter une modulation, une mise entrames et un mappage sur lesdits bits codésprovenant de ladite unité CCC (806) pourproduire ledit signal de bande de base pourladite modulation dudit signal d’entrée, et(ii) exécuter une démodulation, une estima-tion de canal, une correction de canal et undémappage de symboles sur ledit signal debande de base complexe reçu à partir deladite unité SCC (802) pour produire lesditsbits de décision pour ladite démodulationdudit signal d’entrée ;

un coprocesseur selon les moindres carrés,LMS, (1110) couplé à ladite pluralité d’unitéscentrales SPROC (1108), ledit coprocesseurLMS (1110) étant adapté pour exécuter un fil-trage FIR asservi et prédictif adaptatif, uneadaptation de coefficients ou de prises, et uneopération de filtrage FIR à grande vitesse surde multiples trains ; etun sous-système de mémoire qui comprend :

un tampon inter-groupes , ICB, (1112) ;un sous-système de mémoire partagée,SHM, (1114) qui est connecté à toute la plu-ralité d’unités centrales SPROC (1108), le-dit sous-système SHM étant utilisé commetampon pour mémoriser et échanger des ré-sultats calculés entre ladite pluralité d’uni-tés centrales SPROC (1108) ; etune unité d’accès direct à la mémoire, DMA,qui traite un transfert de données traitées àladite unité CCC (806).

6. Sous-système SDR (800) selon la revendication 5,dans lequel ladite pluralité d’unités centralesSPROC (1108) comprend :

un emplacement arithmétique complexe qui

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exécute au moins l’une d’opérations arithméti-ques réelles et complexes, dans lequel lesditesopérations comportent des opérations d’instruc-tion unique, données multiples, SIMD, à N voies,dans lequel ledit emplacement arithmétiquecomplexe prend en charge des opérations pa-pillon de transformée de Fourier rapide, FFT ; etun emplacement CORDIC qui génère (i) des va-leurs de sinus et de cosinus et (ii) une grandeuret des phases de signaux complexes, ledit em-placement CORDIC étant couplé audit copro-cesseur LMS pour exécuter des opérations cy-cliques de lecture et d’écriture efficaces durantune opération d’égaliseur, ledit emplacementCORDIC exécutant en outre des opérationsarithmétiques à N voies, des opérations logi-ques et des opérations d’extraction.

7. Sous-système SDR (800) selon la revendication 1,dans lequel ladite unité CCC (806) est adaptée pour :

(i) recevoir ledit signal d’entrée et exécuter aumoins l’un d’un codage Viterbi, d’un codageReed Solomon, RS et d’une vérification de paritéde faible densité, LDPC, pour produire lesditsbits codés pour ladite modulation, et(ii) recevoir lesdits bits de décision à partir deladite unité SPC (804) et exécuter au moins l’und’un décodage Viterbi, d’un décodage Reed So-lomon, RS et d’une vérification de parité de fai-ble densité, LDPC, pour produire lesdites don-nées décodées pour ladite démodulation.

8. Procédé de démodulation d’un signal d’entrée dansun sous-système de radio définie par logiciel, SDR,(800) capable de prendre en charge de multiples nor-mes de communication, ledit procédé comprenant :

la réception, au niveau d’une unité de groupede conditionnement de signal, SCC, (802) duditsous-système SDR (800), dudit signal d’entréedepuis un syntoniseur et la conversion dudit si-gnal d’entrée en l’un d’un signal de fréquenceintermédiaire (IF) nul, d’un signal IF de faibleniveau, et d’un signal IF normal, ladite unité SCC(802) comprenant une pluralité d’unités centra-les de conditionnement de signal SCON (1012)adaptées pour un traitement de signal paréchantillons ;la conversion par ladite unité SCC (802), duditun dudit signal IF nul, dudit signal IF de faibleniveau et dudit signal IF normal en un signalnumérique ;la conversion par abaissement de fréquence parladite unité SCC (802) dudit signal numériqueen un signal de bande de base complexe ;l’exécution par ladite unité SCC (802) d’un filtra-ge FIR, d’un filtrage IIR, d’une interpolation et

d’un filtrage par conversion de fréquenced’échantillonnage sur ledit signal de bande debase complexe pour produire un signal de ban-de de base complexe filtré ;l’exécution, par une unité de groupe de traite-ment de signal, SPC, (804) dudit sous-systèmeSDR (800) d’une démodulation, d’une estima-tion de canal, d’une correction de canal, et d’undémappage sur ledit signal de bande de basecomplexe filtré en fonction desdites multiplesnormes de communication pour obtenir des bitsde décision, ladite unité SPC (804) comprenantune pluralité d’unités centrales de traitement designal SPROC (1108) adaptées pour effectuerun traitement de signal par blocs ; etl’exécution, par une unité de groupe de codecde canal, CCC (806) dudit sous-système SDR(800), d’au moins l’un d’un décodage Viterbi,d’un décodage Reed Solomon, RS et d’une vé-rification de parité de faible densité, LDPC, surlesdits bits de décision pour obtenir des donnéesdécodées.

9. Procédé selon la revendication 8, dans lequel laditeunité centrale SCON (1012) comprend :

un emplacement de chargement-mémorisationqui effectue le chargement et la mémorisationdudit signal de bande de base complexe pourpermettre une opération de filtrage ;un emplacement de filtrage qui reçoit ledit signalde bande de base complexe à partir dudit em-placement de chargement-mémorisation etadapté pour exécuter ledit filtrage FIR, ledit fil-trage IIR, ladite interpolation et ledit filtrage parconversion de fréquence d’échantillonnage ; etun emplacement arithmétique adapté pour ef-fectuer des opérations arithmétiques nécessai-res pour une opération de filtrage.

10. Procédé selon la revendication 8, dans lequel laditeunité centrale SPROC (1108) comprend :

un emplacement arithmétique complexe et unemplacement CORDIC adaptés pour exécuterladite démodulation, ladite estimation du canal,ladite correction du canal, et ledit démappagesur ledit signal de bande de base complexe filtré.

11. Procédé de modulation d’un signal d’entrée dans unsous-système de radio définie par logiciel, SDR,(800) capable de prendre en charge de multiples nor-mes de communication, ledit procédé comprenant

l’exécution, par une unité de groupe de codecde canal, CCC (806) dudit sous-système SDR(800), d’au moins l’un d’un codage Viterbi, d’uncodage Reed Solomon, RS, d’un codage de

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convolution et d’une vérification de parité de fai-ble densité (LDPC) sur ledit signal d’entrée pourproduire des bits codés ;l’exécution, par une unité de groupe de traite-ment de signal, SPC, (804) dudit sous-systèmeSDR (800) d’une modulation, d’une mise en tra-mes et d’un mappage sur lesdits bits codés enfonction desdites multiples normes de commu-nication pour obtenir des signaux de bande debase, ladite unité SPC (804) comprenant unepluralité d’unités centrales de traitement de si-gnal SPROC (1108) adaptées pour effectuer untraitement de signal par blocs ;l’exécution, par une unité de groupe de condi-tionnement de signal, SCC, (802) dudit sous-système SDR (800) d’une conversion par élé-vation de fréquence et d’une mise en forme d’im-pulsions desdits signaux en bande de base pourproduire un signal IF numérique, ladite unitéSCC (802) comprenant une pluralité d’unitéscentrales de conditionnement de signal SCON(1012) adaptées pour un traitement de signalpar échantillons ; etla conversion par ladite unité SCC (802), duditsignal IF numérique en un signal analogique.

12. Procédé selon la revendication 11, dans lequel laditeunité centrale SPROC (1108) comprend :

un emplacement arithmétique complexe et unemplacement CORDIC adaptés pour exécuterladite modulation, ladite mise en trames et leditmappage sur lesdits bits codés.

13. Procédé selon la revendication 11,comprenant en outre l’exécution, au moyen d’un em-placement de chargement-mémorisation, d’un em-placement de filtrage, et d’un emplacement arithmé-tique de ladite unité centrale de conditionnement designal, SCON, de ladite conversion par élévation defréquence et de ladite mise en forme d’impulsionsdesdits signaux de bande de base.

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REFERENCES CITED IN THE DESCRIPTION

This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the Europeanpatent document. Even though great care has been taken in compiling the references, errors or omissions cannot beexcluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description

• US 20090274202 A [0020]