ABSTRACT A product with flip-chip package suffered from the ring-type yield loss at the wafer edge (Fig. 2(b)) and the failure analysis (FA)
Ring-type yield loss at wafer edge has been observed during flip- showed the damage sites always located at some specific layouts of chip packaging process. The failure mechanism is attributed to the the internal circuits. However, other products in the same product scrubber clean process step which generates a lot of charges. This in line didn’t suffer similar yield loss. Thus, this yield loss was sus-turn behaves like an electrostatic discharge (ESD) event and damages pected to be sensitive to the special layout. gate oxide of internal circuits. An equivalent circuit is proposed to analyze such a kind of ESD event and proves the importance of the parasitic capacitance of the interconnect metal.
I. INTRODUCTION
In this paper, the IC yield loss caused by the electrostatic static discharge (ESD) during the manufacturing process is reported. Un-like the charged device model (CDM) which occurs on a packaged chip, the damage occurred in the chips at wafer level [1]. For CDM, 3the charges are stored on the package. As one pin of the package is grounded, the charges will flow from the capacitors of the package and chip through the internal circuits to the pad. The resulting CDM current can damage the internal circuit. For this new ESD phenome-non, the charges are stored at the wafer surface. As the wafer back- side is grounded, the charges will flow from the wafer surface through the insulators, internal circuits and the substrate to the back- side of the wafer. To differentiate the difference between this new ESD event and conventional CDM, we call it as the “charged wafer surface model” (CWSM).
The mechanism of plasma process induced damage (P2ID) is well known when the wafer is exposed in the charging environment. There are some differences between P2ID and CWSM. P2ID can result in a higher gate leakage and cause long-term reliability concern due to the charges flowing through the gate oxide, but it does not lead to the catastrophic damage on a chip. In addition, P2ID needs the conduction layers such as metal and via to conduct the charges to the gate oxide. However, CWSM does not need a direct conduction layer between the charge source and the damage region. The charges can flow though the insulator to induce the catastrophic damage on the chip since the insulator can act as a capacitor during this event. It has been found that the damage can occur at the poly-insulator-poly (PIP) [2], metal-insulator-metal (MIM) or gate oxide as shown in Figure 1(a)-(c).
It is well know that P2ID issue can come from the etching or de- position processes. For CWSM, we attribute it to the scrubber clean
process. The early study had reported the non-optimized scrubber clean process could lead to the yield loss [2]. In this paper, the yield
loss caused by the scrubber clean of bump process for flip-chip pack-age is investigated to find out the sensitive layouts for CWSM effect.
We found the damage not only occurred on a real product with full processing (wafer start to passivation), but also occurred at the back-
end test pattern with daisy chain even without any front-end process if the CWSM effect is not considered carefully during the layout design, as shown in Fig. 1(d).
II. EXPERIMENT AND FAIL E ANALYSIS UR
The processes used to fabricate the devices and flip-chip package Fig. 1 (a) PIP damage, (b) MIM damage, (c) gate-oxide damage, (d)
for this product are conventional CMOS and plating bump processes. dummy metal damages below the daisy chain caused by CWSM.
In order to identify the yield loss coming from CMOS process or (CPLAT1, 2)bump process, the CP yield was checked before bump process and
after bump process, as shown in Fig. 2. After the bump process, the CP yield decreased form 98.7% to 86.4% and there was an apparent ring-type CP yield loss at the wafer edge (Fig. 2(b)). It confirmed the CP yield loss of this product was caused by the bump process. Due to only a few process steps involved in the bump process (Fig. 3), it was easy to find out which process step during the bump process could induce such kind of yield loss from the experiment. The suspected steps were processed twice to enhance their impacts on the yield loss. Table I shows that the wafers processed with de-scum and sputter twice still had yields comparable with the wafer yield before bump process. Moreover, they didn’t suffer from the ring-type yield loss at the wafer edge, as shown in Fig. 4(b) and 4(c). However, the CP yield loss increased with the process times of the scrubber clean. The Fig. 3 Bump process flow for flip-chip package CP yields were 98.7%, 86.4% and 78.5% for without scrubber clean, with one time and two times scrubber cleans, respectively. Compared Fig. 2 with Fig. 4(a), the CP yield loss was enhanced at the wafer edge by increasing the process times of the scrubber clean. From the CHARM-2 monitoring wafer [3], it can also be observed the maxi- mum surface potential was ring-shaped at the wafer edge after the scrubber cleans, as shown in Fig. 5. It implied that the electrostatic charges induced by scrubber clean at the wafer edge were more than those at any other region of the wafer. This result matched well with the CP yield maps of Fig. 2(b) and Fig. 4(a), where most of the failed dies occurred at the wafer edge. Fig. 2 CP yield map comparison (a) before the bump process, and (b) after the bump process. More serious ring-type yield loss at wafer Fig. 4 CP yield map comparison for 2 times of (a) scrubber, (b) de-edge after the bump process can be observed. scum, and (c) sputter processes. Only scrubber process could result in the ring-type yield loss at wafer edge.
PR Patterning
Scrubber
Descum
Scrubber Solder Electroplating(CPLAT1, 2)
SputterPR Patterning
Scrubber
Descum
Scrubber
Sputter
Solder Reflow
PR Stripping UBM Etching Flux Clean
Solder Reflow
PR Stripping UBM Etching Descum Flux Clean
Scrubber ScrubberSolder Reflow
PR Stripping UBM Etching Flux Clean
Solder Reflow
PR Stripping UBM Etching Descum Flux Clean
Solder Electroplating(CPLAT1, 2)
Scrubber Scrubber
PR Patterning
Scrubber
Descum
Scrubber Solder Electroplating(CPLAT1, 2)
SputterPR Patterning
Scrubber
Descum
Scrubber
Sputter
Solder Reflow
PR Stripping UBM Etching Flux Clean
Solder Reflow
PR Stripping UBM Etching Descum Flux Clean
Scrubber ScrubberSolder Reflow
PR Stripping UBM Etching Flux Clean
Solder Reflow
PR Stripping UBM Etching Descum Flux Clean
Scrubber Scrubber
(a)
(b) ring-type yield loss
(a)
(b)
(c)
ring-type yield loss
677
TABLE 1. CP YIELLD VS. TWO TIMES SCRUBBR, DESCUM, AND SPUTTER PROCESSES
Exp. 2 x scrubber 2 x de-scum 2 x sputterYield 78.5% 98.4% 97.5%
Fig. 5 Potential distribution of CHARM-2 wafer after scrubber clean
B. Failure Analysis Results
A standard FA procedure was used to find out the root cause of the yield loss for this product. The backside emission microscope (EM- Fig. 6 (a) VC (voltage contrast) image of the dummy M5 above a MI) was used to identify the failure locations and the voltage contrast circuit, (b) M5, M4, M3, contact, poly, diffusion and N-Well layouts (VC) was used to find out the damaged devices. From the EMMI results, it could be observed that all the damaged circuits had M4 as The potential distribution in Fig. 5 indicates that the electrostatic the interconnect metal and this interconnect metal crossed beneath charges are generated and accumulated on the wafer surface (Q in the top metal (M5). When the circuits serve as the receivers of anoth- surFig. 7) during the scrubber clean. It is inevitable that some of the er circuit block and are with several thousand micrometers away, it is charges remain on the dummy top metal (Q in Fig. 7) after the top inevitable to use upper metal layer for the routing and have the over- M5metal formation processes since it does not connect to any compo-lap regions between the interconnect metal and the top metal. From nent to discharge the charges generated during the metal formation the VC results, abnormal brightness could be observed at the core processes. As a result, the parasitic capacitors, e.g. C or C inverter gates, which implies oxide damage. From the circuit layout PA-Mn M5-Mn-1shown in Fig. 7, inherit the electrostatic charges. The equivalent verification, the damaged circuits could be divided into two groups. circuits of the inverters in Fig. 6 can be depicted as those in Fig. 7 In one group the interconnect metal of the inverter crossed beneath during the CWSM event, and the gate voltage of the inverter gate can the top dummy metal or dummy bump, which is a floating metal and be expressed as: is not connected to any component. In the other group the intercon-
nect metal of the inverter crossed beneath M5 power bus for IO Vdd.
B1. Circuit under a Dummy Top Metal
From the VC result shown in Fig. 6(a), it can be observed the ab-normal brightness at the gates and NMOS source/drain regions of the core inverters a1 and a2 in cell-1 and cell-2, but no brightness at the inverter a3 of cell-3. This implies that the NMOS gate oxides of the inverters a1 and a2 had been damaged, but the gate oxides of the other inverters (b1, b2, c1, c2 and a3) are not damaged. Although this circuit block is composed of the repeated cells as shown in Fig. 6(b) and the function of each inverter of the repeated cells are similar, it still has the electrical differences caused by the layouts of intercon-nect metal and dummy top metal in these inverters during the scrub-ber clean. These geometry differences will induce the different charge behaviors for these inverters during the scrubber clean. Some locations like a1 and a2 in Fig. 6 are very sensitive to the scrubber clean-induced damage, but some locations like a3, b1, b2, c1 and c2 in Fig. 6 are immune from the scrubber clean-induced damage. To explain this phenomenon, a charged wafer surface model (CWSM) is proposed as below.
CV M 5−MnQsur + CPA−M 5QM 5g= (1)
CM 5−MnCPA−M 5 + Cg (CPA−M 5 + CM 5−Mn ) Based on the layout and VC result in Fig. 6(a), it can be observed
that only the inverter, which uses M4 as the interconnection and in which this interconnect metal crosses beneath a floating top metal (a1 and a2 in Fig. 6), suffers the oxide damage issue since the inver-ter gate can be coupled to a higher voltage based on the eq. (1). It is observed that the inverter will not suffer the oxide damage issue if it uses the lower metal layer as the interconnect metal (c1 and c2 in Fig. 6) or if the interconnect metal does not cross beneath the floating top metal (a3 in Fig. 6) since the coupled voltage of the inverter gate is smaller.
It is worth noting that the inverter also does not suffer the oxide damage issue even it uses M4 as the interconnect metal and crosses beneath a floating top metal (b1 and b2 in Fig. 6) if this interconnect connects to the drain of an inverter. This implies that a core NMOS-FET can effectively protect the CWSM event. However, it is appar-ent that the antenna protection diode for P2ID is useless for the CWSM event. Otherwise the inverters a1 and a2 in Fig. 7 should not be damaged and the abnormal brightness cannot be found at the two
29.91
22.9115.908.901.89
-6.89-13.88
-20.88-27.87
32.98
81
-30.25
3.28
(0.0,0.0)
8.72
29.91
22.9115.908.901.89
-6.89-13.88
-20.88-27.87
32.98
81
-30.25
3.28
(0.0,0.0)
8.72
b1 c1 b2a1 c2a2 a3
N+/PW antenna diodes
Dummy M5
PM coO reS
c1 c2
c a1 b1 a2b2 a3NM orO e
SM3
N+/ PW antenna diodes M4M4M4 M4 M3
M3M4 M4
N+ pick-up (Vdd)
P+ pick-up (Vss)
N+ pick-up (Vdd)
P+ pick-up (Vss)
(a)cell-1 cell-2PM cell-3O
SN
MO
S
(b)
cell-1 cell-2 cell-3
678
inverters as shown in Fig. 6. It also implies that the charges to induce circuit in Fig. 7(b) does not suffer the oxide damage, but the circuit such kind damage should be the positive charge since the diode is in Fig. 7(a) suffers the oxide damage issue. Although the transceiver useful for forward mode ESD event but not effective for reverse is also an inverter drain, the large voltage difference between the mode ESD event. transceiver Vss and receiver Vss may pull up the gate voltage to be
higher than the gate oxide breakdown voltage, and then damage the receiver gate oxide when the parasitic bipolar transistor of the tran-
sceiver is turned on.
Fig. 8 (a) Layout of the inverter with interconnect metal (M4) cross-Fig. 7 Equivalent circuits of (a) a1 and a2, (b) b1 and b2, (c) c1, and ing beneath IO Vdd bus with top metal (M5), (b) VC shows the ab-(d) c2 in the cells in Fig. 6 normal brightness at the gates of NMOSFETs, (c) Equivalent circuit
of (a) during CWSM event. B2. Interconnect Metal (M4) crossing beneath Power Bus (Top Metal M5) for IO Vdd
III. FAILURE MECHANISM In addition to the circuit with interconnect metal (M4) crossing
under the dummy M5 suffering oxide damage, the circuit with inter- From TEM picture shown in Fig. 9, an apparent burn-out from the connect metal M4 crossing beneath the IO power bus also suffers poly gate through the gate oxide to the P- substrate is found at the gate oxide damage after scrubber clean as shown in Fig. 8(b). The NMOSFET. However, the gate of the inverter is not connected to the abnormal brightness can be observed at the NMOSFETs’ gate ter- wafer surface with power bus or dummy metal by any interconnect minals of the three inverters in Fig. 8(b). Similar to the mechanism metal (Fig. 7 and Fig. 8). Thus, it is inferred the charges may flow described in the previous section, some of generated electrostatic though the insulators, e.g. passivation and IMD, between the wafer charges will accumulate on the wafer surface, and some of the surfaces and interconnect metals to the gate terminal of the damaged charges will flow through the IO pad to the IO Vdd bus line and are device. The plausible damage mechanism is proposed as below. stored there during the scrubber clean. For this case, the equivalent As the wafer backside is grounded, the generated charges stored on circuit can be depicted as that in Fig. 8(c). In this chip, the damaged the wafer surface and dummy top metal can flow through passiva-circuit is thousand micrometers away from the IO ESD protection tion, IMD, under-layer components like the gate capacitor and sub-device. Due to the high parasitic resistance of P-substrate, there ex- strate to the wafer backside. This will raise the gate potential to a ists a large potential difference between the damaged circuit and the high level, based on the eq. (1). Because the gate oxide thickness of
core device is much thinner than IMD film, and the overlap area IO ESD protection device even when the ESD device turns on to sink between the interconnect metal and the floating top metal is quite the electrostatic charges from its ground Vss to the wafer backside. small, the term C ×CDuring the CWSM event, even with the IO ESD protection device be M5-Mn PA-M5 in eq. (1) can be neglected, and eq. (1) is simplified as: turned-on before core oxide breaks down, the gate voltage still can-
not be clamped below the gate oxide breakdown voltage since there is a potential difference between the core Vss and IO Vss. In addition, the turn-on threshold voltage of the parasitic bipolar transistor of the ESD device is too high to protect the core gate oxide. This is why the
C − += 5 MnQ
V M sur CPA−M 5QM 5g (2)
Cg (CPA−M 5 + CM 5−Mn )
G3 G2 G1
(a)N c (b)oM r M5 power bus NO e MS G3 G2 G1 for IO Vdd OS
co re P PM
M4
M
O O
S
M4
S
M4N-Well
Core Vdd(a)
QC sur
PA-M5
CM5-M4
antenna diode
Core Vss
QM5
Core Vdd(b)
QC sur
PA-M5
CM5-M4
antenna diode
Core Vss
QM5
(c)
QC sur
PA-M5
CM5-M3
antenna diode
QM5
(d)
Qsur
CPA-M4
antenna diode
Transceiver Transceiver
TrT ar na snsc
ce
ei
iv
ve
er
r
Vg
Vg
Vg
Vg
Cg Cg
Cg Cg
Wafer Backside Wafer Backside
Core Vdd Core Vdd
Core Vss Core VssWafer Backside
Rsub Rsub
IO Vdd
ESD
RsubRsub Rsub
Wafer Backside
Qsur
CPA-M5
CM5-M4
QM5
IO Vss
VgTransceiverCg
Pad
Wafer Backside
Core Vdd
Core VssRsub-1 Rsub-2
(c)
679
The gate voltage not only depends on the capacitance values of the capacitors CPAS-M, CMn-Mn-1 and Cg but also depends on the stored charges of the capacitors CPAS-Mn and CMn-Mn-1. Comparing the cir- cuits of Fig. 7(a) with Fig. 7(d), the only difference for the two cir-cuits is that the circuit in Fig. 7(d) doesn’t have the stored charge QM5, but the circuit in Fig. 7(a) has the stored charge QM5 on M5. Because of QM5, it will induce the higher gate voltage to the inverter in Fig. 7(a) from eq. (2) by comparing with the inverter in Fig. 7(d) without QM5. Thus we always can find the gate oxide damage at the circuit in Fig. 7(a), but no gate oxide damage at the circuit in Fig. 7(d). This result also demonstrates the importance of the interaction between dummy metal and scrubber clean. For the circuit in Fig. 7(c), it will have the smaller capacitance CM5-M3 due to thicker dielec-tric. This will decrease the first term in eq. (2) to result in the smaller gate voltage of the circuit in Fig. 7(c) compared with the circuit in Fig. 7(a). Thus, we also cannot find the oxide damage at the location with the same circuit in Fig. 7(c) in this chip. Fig. 10 IG-VG characteristic of a core NMOSFET under the TLP
Fig. 10 shows the IG-VG characteristic of a core NMOSFET under with 100nsec pulse width. the transmission-line pulse (TLP) with 100nsec pulse width and 200psec rising time. It can be observed the oxide leakage current increased gradually for the applied voltage between 6V and 8.2V, and increased dramatically if the applied voltage is higher than 8.2V. It implies the gate oxide of core NMOSFET has been degraded if the applied voltage is higher than 6V, and will be damaged if the applied voltage is higher than 8.2V. Fig. 11 shows the ID-VD characteristics of IO and core NMOSFETs with 20um width under the TLP with 100nsec pulse width. The trigger voltages for IO and core NMOS- FETs are 7.8V and 5.0V, respectively. It implies that core NMOS- FET can effectively protect the core gate oxide. Although the trigger voltage (7.8V) of IO NMOSFET is smaller than the core gate oxide breakdown voltage (8.2V) in this study, IO NMOSFET still cannot effectively protect the gate oxide of core device since the IO trigger voltage is too close to core gate oxide breakdown voltage.
The mechanism of why the NMOSFET of the transceiver cannot protect the gate oxide in Fig. 7(a) is discussed as below. Fig. 12(a) shows the test structure to evaluate the potential difference when Fig. 11 ID-VD characteristics of IO NMOSFET and core NMOSFET there is current flowing from a P-Well pick-up through the P-Well under the TLP with 100nsec pulse width. and P-substrate to the wafer backside. Because the P-substrate is with a low-doping concentration (~1E15/cm3
), the potential of the P-Well can be raised up to 2V even with a very small current (0.013mA), based on DC I-V characteristics of Fig. 12(b). For a typical ESD event, the current level will be much higher than the level with mini- ampere. It will induce the huge potential difference between the re- ceiver ground and transceiver ground as the ESD current flows from the transceiver Vss to the chip backside when the parasitic bipolar transistor of the transceiver NMOSFET is turned on. Thus, the gate voltage cannot be clamped below the gate oxide breakdown voltage. However, the turned-on parasitic bipolar transistor of NMOSFET in the second inverter in Fig. 7(b) can clamp the gate voltage below the gate oxide breakdown voltage and shunt most of the charges. There- fore, no gate oxide damage can be observed.
Fig. 12 (a) Schematic of the test pattern, and (b) DC I-V characteris-
2Fig. 9 Gate oxide damage of NMOSFET after scrubber clean tic of a P-Well pick-up to wafer backside for a 3500×3500um chip
with 12 mill
Poly Gate
Gate Oxide DamageP-substrate
Poly Gate
Gate Oxide DamageP-substrate
10-3
10-4
10-5
10-6
10-7
10-80 2 4 6 8
) A
t (nerru C
teaG
Gate Voltage ( V )
core NMOS
10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3Leakage Current ( A ) @Vdd
leakage current after each TLP
PWP+
(a).P+
Vss
12 mil’s
Chip Backside
P-Well pickup V
(b).
P-substrate
15
10
5
00.0 0.5 1.0 1.5 2.0
P-Well pickup to chip backside
)
Aμ t (nerru
C
Voltage ( V )
120
100
80
60
40
20
00 2 4 6 8
) m
At (
enrru Cn
airD
Drain Voltage ( V )
IO NMOS
core NMOS
10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3Leakage Current ( A ) @Vdd
leak. (Vd @ IO Vdd) leak. (Vd @ core Vdd)
680
V. CONCLUSIONS
In this study, we have reported yield loss during the flip-chip package process and identified the root cause as the scrubber clean induced gate oxide damage. The scrubber clean process can generate electrostatic charges on the top dummy metal strips or power bus lines. These electrostatic charges will flow through the IMD films or metal interconnects to the gate terminals of internal circuits and de-stroy the gate oxide if there is no suitable protection circuit. This phenomenon is different from the P2ID effect but behaves similarly to the ESD event. Because it happens at the wafer level, we refer to it as the charged wafer surface mode (CWSM) event. Based on the failure analysis and the mechanism exploring, it can be realized that using the low layer metals as the interconnect metals can prevent such CWSM event induced damage.
REFERENCES
[1] Peter Jacob and Giovanni Nicoletti, “Surface Electrostatic Dam-age by Microprocess Robotic Machines: Diagnosis and Reliabili-ty, Process Auditing, and Remedies,” IEEE Trans. Electron De-vices, pp. 213-220, 2006.
[2] Jian-Hsing Lee, J R shih, Chi-Lun Huang, Sunnys Hsieh, and Kenneth Wu, “Scrubber Process Induced CDM ESD-Like : CSM (Charge Surface Model) Event Caused By Dummy Patterns,” in Proc. 46nd IRPS, pp. 315-318, 2008.
[3] Wes Lukaszek, William Dixson, Michael Vella, Cleston Messick, Steve Reno, and Jay Shiiderler, “Characteristics of Wafer Charg-ing Mechanism and Oxide Survival Prediction Methodology,” in Proc. 32nd IRPS, pp. 334-338, 1994.
