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IT 251Computer Organization
and Architecture
Virtual Memory
Chia-Chi Teng
Review
Cache design choices:— Size of cache: speed v. capacity— Block size (i.e., cache aspect ratio)— Write Policy (Write through v. write back)— Associativity choice of N (direct-mapped v. set v. fully
associative)— Block replacement policy— 2nd level cache?— 3rd level cache?
Use performance model to pick between choices, depending on programs, technology, budget, ...
Regs
L2 Cache
Memory
Disk
Tape
Instr. Operands
Blocks
Pages
Files
Upper Level
Lower Level
Faster
Larger
CacheBlocks
Thus far{{Next:
VirtualMemory
Another View of the Memory Hierarchy
Memory Hierarchy Requirements
If Principle of Locality allows caches to offer (close to) speed of cache memory with size of DRAM memory, then recursively why not use at next level to give speed of DRAM memory, size of Disk memory?
While we’re at it, what other things do we need from our memory system?
Memory Hierarchy Requirements
Allow multiple processes to simultaneously occupy memory and provide protection – don’t let one program read/write memory from another
Address space – give each program the illusion that it has its own private memory— Suppose code starts at address 0x40000000. But different
processes have different code, both residing at the same address. So each program has a different view of memory.
SHARING & PROTECTION
Virtual Memory
Next level in the memory hierarchy:—Provides program with illusion of a very large main
memory:—Working set of “pages” reside in main memory - others
reside on disk.
Also allows OS to share memory, protect programs from each other
Today, more important for protection vs. just another level of memory hierarchy
Each process thinks it has all the memory to itself (Historically, it predates caches)
Virtual addresses for multiprogramming
To make it easier to manage memory of multiple processes, make processes use virtual addresses (which is not what we mean by “virtual memory” today!)— virtual addresses are independent of location in physical
memory (RAM) where referenced data lives• OS determines location in physical memory
— instructions issued by CPU reference virtual addresses• e.g., pointers, arguments to load/store instructions, PC
…— virtual addresses are translated by hardware into physical
addresses (with some setup from OS)
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The set of virtual addresses a process can reference is its address space— many different possible mechanisms for translating virtual
addresses to physical addresses• we’ll take a historical walk through them, ending up with
our current techniques
Note: We are not yet talking about paging, or virtual memory – only that the program issues addresses in a virtual address space, and these must be “adjusted” to reference physical memory (the physical address space)— for now, think of the program as having a contiguous virtual
address space that starts at 0, and a contiguous physical address space that starts somewhere else
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Virtual to Physical Address Translation
Each program operates in its own virtual address space; ~only program running
Each is protected from the other OS can decide where each goes in memory Hardware gives virtual physical mapping
virtualaddress
(inst. fetchload, store)
Programoperates inits virtualaddressspace
HWmapping physical
address(inst. fetchload, store)
Physicalmemory
(incl. caches)
0
OS
User A
User B
User C
$base
$base+$bound
• Want: •discontinuous mapping
•Process size >>mem
• Addition not enough!
use Indirection!
Enough space for User D,but discontinuous (“fragmentation problem”)
Simple Example: Base and Bound Reg
Mapping Virtual Address to Physical Address
Divide into equal sizedchunks (about 4 KB - 8 KB)
Any chunk of Virtual Memory assigned to any chuck of Physical Memory (“page”)
0
Physical Memory
Virtual Memory
Code
Static
Heap
Stack
64 MB
0
Paging Organization (assume 1 KB pages)
AddrTransMAP
Page is unit of mapping
Page also unit of transfer from disk to physical memory
page 0 1K1K
1K
01024
31744
Virtual Memory
VirtualAddress
page 1
page 31
1K2048 page 2
...... ...
page 001024
7168
PhysicalAddress
PhysicalMemory
1K1K
1K
page 1
page 7...... ...
Address translation
Translating virtual addresses— a virtual address has two parts: virtual page number &
offset— virtual page number (VPN) is index into a page table— page table entry contains page frame number (PFN)— physical address is PFN::offset
Page tables— managed by the OS— map virtual page number (VPN) to page frame number (PFN)
• VPN is simply an index into the page table— one page table entry (PTE) per page in virtual address space
• i.e., one PTE per VPN
Mechanics of address translation
pageframe 0
pageframe 1
pageframe 2
pageframe Y
…
pageframe 3
physical memory
offset
physical address
page frame #page frame #
page table
offset
virtual address
virtual page #
Example of address translation
Assume 32 bit addresses— assume page size is 4KB (4096 bytes, or 212 bytes)— VPN is 20 bits long (220 VPNs), offset is 12 bits long
Let’s translate virtual address 9000decimal
— VPN is 2, and offset is 808decimal
— assume page table entry 2 contains value 4
• page frame number is 4• VPN 2 maps to PFN 4
— physical address = PF base + offset = 4*4096 + 808 = 16384 + 808 = 17192
pageframe 0
pageframe 1
pageframe 2
pageframe Y
…
pageframe 3
physical memory
808
physical address= 4 * 4096 + 808= 17192
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page table
808virtual address 9000 = 2* 4096 + 808
2
pageframe 4
virtualpage 0
virtualpage 1
virtualpage 2
virtualpage 220-1
…
virtualpage 3
Virtual address space
virtualpage 4
0
4G-1
4096
8192
04/22/23 17
Example of address translation
How about in binary? Still assume 32 bit addresses
— assume page size is 4KB (4096 bytes, or 212 bytes)— VPN is 20 bits long (220 VPNs), offset is 12 bits long
Let’s translate virtual address 0x13325328— VPN is 0x13325, and offset is 0x328— assume page table entry 0x13325 contains value 0x03004
• page frame number is 0x03004• VPN 0x13325 maps to PFN 0x03004
— physical address = PFN::offset = 0x03004328
Exercise
Considering a simple paging system with 228 bytes of physical memory, 232 bytes of virtual address space, and page size of 4K bytes.— How many entries in the page table?
— How many bits in the virtual address used to specify the page #?
— How many bits in the physical address used to specify the frame #?
232/4K = 220 , or 4G/4K = 1M
32 – 12 = 20
28 – 12 = 16
Exercise
04/22/23 20
Virtual page # Valid Physical Frame #
0 1 10
1 1 4
2 1 2
3 0 -
• Considering the following page table.– Assume the page size is 2048 bytes, all numbers are decimal
and zero based. What is the physical address for the virtual address 2096?
VPN = 1Offset = 2096 – 2048 = 48PF = 4Physical address = 4 * 2048 + 48 = 8240
Page Table
A page table is an operating system structure which contains the mapping of virtual addresses to physical locations— There are several different ways, all up to the operating
system, to keep this data around Each process running in the operating system has its own page
table— “State” of process is PC, all registers, plus page table— OS changes page tables by changing contents of Page Table
Base Register
Requirements revisited
Remember the motivation for VM: Sharing memory with protection
— Different physical pages can be allocated to different processes (sharing)
— A process can only touch pages in its own page table (protection)
Separate address spaces— Since programs work only with virtual addresses, different
programs can have different data/code at the same address! What about the memory hierarchy?
Page Table Entries (PTEs)
PTE’s control mapping— the valid bit says whether or not the PTE can be used
• says whether or not a virtual address is valid• it is checked each time a virtual address is used
— the referenced bit says whether the page has been accessed• it is set when a page has been read or written to
— the modified bit says whether or not the page is dirty• it is set when a write to the page has occurred
— the protection bits control which operations are allowed• read, write, execute
— the page frame number determines the physical page• physical page start address = PFN
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page frame numberprotMRV
202111
Paging/Virtual Memory Multiple Processes
User B: Virtual Memory
Code
Static
Heap
Stack
0Code
Static
Heap
Stack
A PageTable
B PageTable
User A: Virtual Memory
00
Physical Memory
64 MB
Comparing the 2 levels of hierarchy
Cache version Virtual Memory version
Block or Line PageMiss Page FaultBlock Size: 32-64B Page Size: 4K-8KBPlacement: Fully Associative
Direct Mapped, N-way Set Associative
Replacement: Least Recently UsedLRU or Random (LRU)
Write Thru or Back Write Back
Notes on Page Table
Solves Fragmentation problem: all chunks same size, so all holes can be used
OS must reserve “Swap Space” on disk for each process To grow a process, ask Operating System
— If unused pages, OS uses them first— If not, OS swaps some old pages to disk— (Least Recently Used to pick pages to swap)
Each process has own Page Table Will add details, but Page Table is essence of Virtual Memory
Why would a process need to “grow”?
A program’s address space contains 4 regions:— stack: local variables, grows
downward— heap: space requested for
pointers via malloc() ; resizes dynamically, grows upward
— static data: variables declared outside main, does not grow or shrink
— code: loaded when program starts, does not change
code
static data
heap
stack
For now, OS somehowprevents accesses between stack and heap (gray hash
lines).
~ FFFF FFFFhex
~ 0hex
Virtual Memory Problem #1
For each virtual address reference: read Page Table entry (in memory) & read physical memory address = 2 physical memory accesses (SLOW!)
Observation: since locality in pages of data, there must be locality in virtual address translations of those pages
Since small is fast, why not use a small cache of virtual to physical address translations to make translation fast?
For historical reasons, cache is called a Translation Lookaside Buffer, or TLB
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Review: cache hit
When the CPU tries to read from memory, the address will be sent to a cache controller.—The lowest k bits of the address will index a block in the cache.—If the block is valid and the tag matches the upper (m - k) bits
of the m-bit address, then that data will be sent to the CPU. Here is a diagram of a 32-bit memory address and a 210-byte
cache.
0123......
10221023
Index Tag DataValidAddress (32 bits)
=
To CPU
Hit
1022
Index
Tag
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Review: cache mapping
10
012...
512...
10221023
Index Tag DataValid
Address (32 bits)
=
Hit
1020
Tag
2 bits
Mux
Data
8 8 8 8
8
0000 .... 0001 1000000000
Block IndexTag
Block Offset
2
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Review: cache associativity
By now you may have noticed the 1-way set associative cache is the same as a direct-mapped cache.
Similarly, if a cache has 2k blocks, a 2k-way set associative cache would be the same as a fully-associative cache.
01234567
Set
0
1
2
3
Set
0
1
Set
1-way8 sets,
1 block each
2-way4 sets,
2 blocks each
4-way2 sets,
4 blocks each
0
Set
8-way1 set,
8 blocks
direct mapped fully associative
From virtual address to memory location
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CPU
Virtual address
TLB
Physical address
hit
cache
Main memory
(page table)
miss
hit
miss
• TLB is a special cache just for the page table.• Usually fully associative.
TLB
Virtual to Physical translations are cached in a Translation Lookaside Buffer (TLB).
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Valid Tag Data
Page offset
Page offset
Virtual page number
Virtual address
Physical page numberValid
1220
20
16 14
Cache index
32
Cache
DataCache hit
2
Byteoffset
Dirty Tag
TLB hit
Physical page number
Physical address tag
TLB
Physical address
31 30 29 15 14 13 12 11 10 9 8 3 2 1 0
What about a TLB miss?
If we miss in the TLB, we need to “walk the page table”— In MIPS, an exception is raised and software fills the TLB— In x86, a “hardware page table walker” fills the TLB
What if the page is not in memory?— This situation is called a page fault.— The operating system will have to request the page from disk.— It will need to select a page to replace.
• The O/S tries to approximate LRU (IT344)— The replaced page will need to be written back if dirty.
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CAMERA EXERCISE
Peer Instruction
A. Locality is important yet different for cache and virtual memory (VM): temporal locality for caches but spatial locality for VM
B. Cache management is done by hardware (HW), page table management by the operating system (OS), but TLB management is either by HW or OS
C. VM helps both with security and cost
ABC0: FFF1: FFT2: FTF3: FTT4: TFF5: TFT6: TTF7: TTT
A. Locality is important yet different for cache and virtual memory (VM): temporal locality for caches but spatial locality for VM
B. Cache management is done by hardware (HW), page table management by the operating system (OS), but TLB management is either by HW or OS
C. VM helps both with security and cost
T R U EF A L S E
A. No. Both for VM and cache
B. Yes. TLB SW (MIPS) or HW ($ HW, Page table OS)C. Yes. Protection and
a bit smaller memory
T R U E ABC0: FFF1: FFT2: FTF3: FTT4: TFF5: TFT6: TTF7: TTT
Peer Instruction Answer
And in conclusion…
Manage memory to disk? Treat as cache— Included protection as bonus, now critical— Use Page Table of mappings for each user
vs. tag/data in cache— TLB is cache of Virtual -> Physical address translation
Virtual Memory allows protected sharing of memory between processes
Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well
TLB Management TLBs are organized as caches
— If small, can be fully associative— Current trend: larger (about 128 entries); separate TLB’s for
instruction and data; Some part of the TLB reserved for system— TLBs are write-back. The only thing that can change is dirty bit
+ any other information needed for page replacement algorithm (cf. CSE 451)
MIPS 3000 TLB (old)— 64 entries: fully associative. “Random” replacement; 8 entries
used by system— On TLB miss, we have a trap; software takes over but no
context-switch
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TLB management (continued) At context-switch, the virtual page translations in the TLB are not
valid for the new task— Invalidate the TLB (set all valid bits to 0) — Or append a Process ID (PID) number to the tag in the TLB.
When a new task takes over, the O.S. creates a new PID.— PID are recycled and entries corresponding to “old PID” are
invalidated.
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Paging systems Hardware/software interactions
Page tables— Managed by the O.S.— Address of the start of the page table for a given process is
found in a special register which is part of the state of the process
— The O.S. has its own page table— The O.S. knows where the pages are stored on disk
Page fault— When a program attempts to access a location which is part of
a page that is not in main memory, we have a page fault
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Page fault detection (simplified)
Page fault is an exception Detected by the hardware (invalid bit in PTE either in TLB or
page table) To resolve a page fault takes millions of cycles (disk I/O)
— The program that has a page fault must be interrupted A page fault occurs in the middle of an instruction
— In order to restart the program later, the state of the program must be saved and instructions must be restartable (precise exceptions)
State consists of all registers, including PC and special registers (such as the one giving the start of the page table address)
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Page fault handler (simplified) Page fault exceptions are cleared by an O.S. routine called the
page fault handler which will— Grab a physical frame from a free list maintained by the O.S.— Find out where the faulting page resides on disk— Initiate a read for that page (DMA)— Choose a frame to free (if needed), i.e., run a replacement
algorithm— If the replaced frame is dirty, initiate a write of that frame to
disk— Context-switch, i.e., give the CPU to a task ready to proceed
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Completion of page fault When the faulting page has been read from disk (a few ms later)
— The disk controller will raise an interrupt (another form of exception)
— The O.S. will take over (context-switch) and modify the PTE (in particular, make it valid)
— The program that had the page fault is put on the queue of tasks ready to be run
— Context-switch to the program that was running before the interrupt occurred
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Two extremes in the memory hierarchy
PARAMETER L1 PAGING SYSTEM
block (page) size 16-64 bytes 4K-8K (also 64K)
miss (fault) time 10-100 cycles (20-1000 ns)
Millions of cycles (3-20 ms)
miss (fault) rate 1-10% 0.00001-0.001%
memory size 4K-64K Bytes (impl. depend.)
Gigabytes (depends on ISA)
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Other extreme differences
Mapping: Restricted (L1) vs. General (Paging)— Hardware assist for virtual address translation (TLB)
Miss handler— Hardware only for caches— Software only for paging system (context-switch)— Hardware and/or software for TLB
Replacement algorithm— Not that important for caches— Very important for paging system
Write policy— Always write back for paging systems
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Some optimizations Speed-up of the most common case (TLB hit + L1 Cache hit)
— Do TLB look-up and cache look-up in parallel• possible if cache index independent of virtual address
translation (good only for small caches)— Have cache indexed by virtual addresses but with physical
tags— Have cache indexed by virtual addresses but with virtual tags
• these last two solutions have additional problems referred to as synonyms
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