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Mid-term Presentation
Implementation of generic interface To electronic components
via USB2 Connection
SupervisorDaniel Alkalay
System architecturesRoee CohenRami May
Technion – Israel Institute of TechnologyDepartment of Electrical Engineering
High-Speed Digital Systems Lab
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AGENDA
• Project Goals• System Architecture • Semester #1 - Summery• Target semester #1 – Transferring a word• System Micro- Architecture FPGA • Future targets• Schedule
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Project GoalDevelopment and implementation of generic interface system between PC via USB2 and electronic components
Software/hardware integration has never been so easy
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System Architecture
Computer
Group
Server
FPGA
D/A (T.I)
Analog signal
Analog signal
USB2
100Mhz
A/D (T.I)
Electronic component
PCB card
Function generator
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System Micro-Architecture
FPGA
50Mhz
Computer
Group
Server
GUI
The major elements that will be design & implemented
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Semester #1 - Summery• Programs that we
studied:• VHDL• ISE • HDL designer
• Keil uvision2
• Subject that we studied:
• FPGA.
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Semester #1 - SummerySpecification that we read:
– SPARTAN 3E - spec– Cypress – micro-controller– USB – book– A/D converter
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• Micro-Architecture- HARDWARE
• Block diagram
• HDL blocks
• State machine
• movie
Transferring a word
FROM: PC =>TO: FPGA
FPGA
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System Micro-Architecture- HARDWAREFPGA
TX
RXREGISTERS
FPGA
Board
SPI
CYPRESS
VHDLentity Fa_unit is port ( A, B, Carry_in : in std_logic; F, Carry_out : out std_logic);end Fa_unit;
User design Modules
User designOur HDL Modules
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USB_IF
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Generic USB Block
USBinterface
I/O to Cypress
Registers
0_27General
28_52Channel1 Read
53_77Channel1 Write
78_102Channel2 Read
103_127Channel2 Write
IN_FIFO
OUT_FIFO
Bur
st D
AT
A P
orts
INCh1
OUTCh2
Channel1 Full
Write Channel1
Channel1 Data
Read Channel2
Channel2 empty
Channel2 Data
RegCh1
RegCh2
Ch1_enCh2_en
Ch1 Reg Write
Ch1 Reg Data OutCh1 Reg Data In
Ch2 Reg Read
Ch1 Reg Addr
Ch2 Reg Data OutCh2 Reg Data In
Ch2 Reg Write
Ch2 Reg Addr
Reg
iste
rs P
orts
System Micro-Architecture- HARDWARE
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PC => FPGA
PC: GUI EZUSB –PortAddressPacket:•opcode•Data
Board:FPGA:
CYPRESS
• receive a packet
• activate signal “not_empty”
• holds the data until readed by FPGA
Interface
•Get packet from cypress
•Parse the packet values
Registers:
Holds the parsed data
output:
•Plotting the word
•Light the LED’s & digits segments
Block Diagram – Transferring a word
FPGA
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Creating a *.HEX file
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FPGA - VHDL design:• Host interface:
• Receive & transfer data from CYPRESS• Checking packets correctness• Parsing packets to data•Transfer clean data to registers
•Other blocks• performs operation according to opcodes• operate the relevant state machine• take status and information from peripherals
FPGA
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Transferring a word INTERFACE STATE MACHINE
FPGA
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IDLE
WAIT FOR COMMAND
TAKE COMMAND
FROM CYPRESS
TRANSFER DATA FROM A/D ->FIFO
GET DATA FROM
CYPRESS
WRITE DATA TO REGISTERS
PARSED PROTOCOLDECIDE R/W
READ DATA FROM
REGISTERS
WRITE DATA TO CYPRESS
IF (A2D FIFO NOT EMPTY
IF (COMMAND ==READ)
IF (COMMAND ==WRITE)