FET BiasingFET Biasing
CHAPTER 6CHAPTER 6
IntroductionIntroduction
For the JFET, the relationship between input and output For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in quantities is nonlinear due to the squared term in Shockley’s equation.Shockley’s equation.
Nonlinear functions results in curves as obtained for Nonlinear functions results in curves as obtained for transfer characteristic of a JFET.transfer characteristic of a JFET.
Graphical approach will be used to examine the dc Graphical approach will be used to examine the dc analysis for FET because it is most popularly used rather analysis for FET because it is most popularly used rather than mathematical approachthan mathematical approach
The input of BJT and FET controlling variables are the The input of BJT and FET controlling variables are the current and the voltage levels respectivelycurrent and the voltage levels respectively
JFETs differ from BJTs:
Nonlinear relationship between input (VGS) and output (ID) JFETs are voltage controlled devices, whereas BJTs are
current controlled
IntroductionIntroduction
Common FET Biasing Circuits• JFET
– Fixed – Bias – Self-Bias – Voltage-Divider Bias
• Depletion-Type MOSFET– Self-Bias– Voltage-Divider Bias
• Enhancement-Type MOSFET– Feedback Configuration– Voltage-Divider Bias
IntroductionIntroduction
General Relationships For all FETs:
For JFETs and Depletion-Type MOSFETs:
For Enhancement-Type MOSFETs:
AIG 0
SD II
2
P
GSDSSD )
V
V(1II
2)( TGSD VVkI
Fixed-Bias Configuration The configuration includes the ac levels Vi and Vo and The configuration includes the ac levels Vi and Vo and
the coupling capacitors.the coupling capacitors. The resistor is present to ensure that Vi appears at the The resistor is present to ensure that Vi appears at the
input to the FET amplifier for the AC analysis.input to the FET amplifier for the AC analysis.
Fixed-Bias Configuration For the DC analysis,For the DC analysis,
Capacitors are open circuitsCapacitors are open circuits and and
The zero-volt drop across RThe zero-volt drop across RGG permits replacing R permits replacing RGG by a short-circuit by a short-circuit
AIG 0 VRARIV GGGRG 0)0(
Fixed-Bias Configuration
Investigating the input loopInvestigating the input loop
IIGG=0A, therefore=0A, therefore
VVRGRG=I=IGGRRGG=0V=0V
Applying KVL for the input loop,Applying KVL for the input loop,
-V-VGGGG-V-VGSGS=0=0
VVGGGG= -V= -VGSGS
It is called It is called fixed-bias configurationfixed-bias configuration due to V due to VGGGG is a fixed is a fixed
power supply so Vpower supply so VGSGS is fixed is fixed
The resulting current,The resulting current,
2)1(P
GSDSSD V
VII
Investigating the graphical approach.Investigating the graphical approach. Using below tables, we Using below tables, we can draw the graphcan draw the graph
VVGSGS IIDD
00 IIDSSDSS
0.3V0.3VPP IIDSSDSS/2/2
0.50.5 IIDSSDSS/4/4
VVPP 0mA0mA
The fixed level of VThe fixed level of VGSGS has been superimposed as a has been superimposed as a
vertical line at vertical line at
At any point on the vertical line, the level of VAt any point on the vertical line, the level of VGG is -V is -VGGGG--- ---
the level of Ithe level of IDD must simply be determined on this vertical must simply be determined on this vertical
line.line.
The point where the two curves intersect is the common The point where the two curves intersect is the common
solution to the configuration – commonly referrers to as solution to the configuration – commonly referrers to as
the the quiescent quiescent or operating point.or operating point.
The quiescent level of IThe quiescent level of IDD is determine by drawing a is determine by drawing a
horizontal line from the Q-point to the vertical Ihorizontal line from the Q-point to the vertical IDD axis. axis.
GGGS VV
Output loopOutput loop
DDDDDS RIVV
VVS 0
SDDS VVV
SDSD VVV 0SV
DSD VV
SGGS VVV
SGSG VVV 0SV
GSG VV
ExampleExample
Determine VDetermine VGSGSQQ, I, IDDQQ, V, VDSDS, V, VDD, V, VGG, V, VSS
ExerciseExercise
Determine IDetermine IDDQQ, V, VGSGSQQ, V, VDSDS, V, VDD, V, VGG and V and VSS
Self Bias ConfigurationSelf Bias Configuration The self-bias configuration eliminates the need for two The self-bias configuration eliminates the need for two
dc supplies.dc supplies. The controlling VThe controlling VGSGS is now determined by the voltage is now determined by the voltage
across the resistor Racross the resistor RSS
For the indicated input loop:
Mathematical approach:
rearrange and solve.
SDGS RIV
2
2
1
1
P
SDDSSD
P
GSDSSD
V
RIII
V
VII
Graphical approachGraphical approach Draw the device transfer characteristicDraw the device transfer characteristic Draw the network load lineDraw the network load line
UseUse to draw straight line. to draw straight line. First point,First point, Second point, any point from ISecond point, any point from IDD = 0 to I = 0 to IDD = I = IDSSDSS. Choose. Choose
the quiescent point obtained at the intersection of the the quiescent point obtained at the intersection of the straight line plot and the device characteristic curve.straight line plot and the device characteristic curve.
The quiescent value for IThe quiescent value for IDD and V and VGS GS can then be can then be determined and used to find the other quantities of determined and used to find the other quantities of interest.interest.
SDGS RIV 0,0 GSD VI
2
2
SDSSGS
DSSD
RIV
thenI
I
For output loopFor output loopApply KVL of output loopApply KVL of output loopUse IUse IDD = I = ISS
RDDDSDSD
SDS
DSDDDDS
VVVVV
RIV
RRIVV
)(
ExampleExampleDetermine VDetermine VGSGSQQ, I, IDDQQ,V,VDSDS,V,VSS,V,VGG and V and VDD..
ExampleExampleDetermine VDetermine VGSGSQQ, I, IDDQQ, V, VDD,V,VGG,V,VSS and V and VDSDS..
Voltage-Divider BiasVoltage-Divider Bias The arrangement is the same as BJT but the DC analysis is The arrangement is the same as BJT but the DC analysis is
differentdifferent In BJT, IIn BJT, IBB provide link to input and output circuit, in FET V provide link to input and output circuit, in FET VGSGS does does
the samethe same
Voltage-Divider Bias The source VThe source VDD DD was separated into two equivalent sources to permit was separated into two equivalent sources to permit
a further separation of the input and output regions of the network.a further separation of the input and output regions of the network.
IIG G = 0A ,Kirchoff’s current law requires that I= 0A ,Kirchoff’s current law requires that IR1R1= I= IR2R2 and the series and the series
equivalent circuit appearing to the left of the figure can be used to equivalent circuit appearing to the left of the figure can be used to find the level of Vfind the level of VGG. .
21
DD2G
RR
VRV
SDGGS
RSGSG
RIVV
VVV
0
Voltage-Divider Bias
VVG G can be found using the voltage divider rule : can be found using the voltage divider rule :
Using Kirchoff’s Law on the input loop: Using Kirchoff’s Law on the input loop:
Rearranging and using ID =IS: Rearranging and using ID =IS:
Again the Q point needs to be established by Again the Q point needs to be established by
plotting a line that intersects the transfer curve.plotting a line that intersects the transfer curve.
Procedures for plottingProcedures for plotting
1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0, ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q point for the circuit.
Once the quiescent values of IOnce the quiescent values of IDQDQ and V and VGSQGSQ are determined, the are determined, the
remaining network analysis can be found.remaining network analysis can be found.
Output loop:Output loop:
2121 RR
VII DDRR
)( SDDDDDDS RIRIVV
DDDDD RIVV
SDS RIV
Effect of increasing values of REffect of increasing values of RSS
ExampleExampleDetermine IDetermine IDDQQ, V, VGSGSQQ, V, VDD, V, VSS, V, VDS DS and Vand VDGDG..
ExampleExampleDetermine IDetermine IDDQQ, V, VGSGSQQ, V, VDS, DS, VVDD and V and VSS
Depletion-type MOSFET bias circuits are similar to JFETs. The only difference is that the depletion-Type MOSFETs can operate with positive values of VGS and with ID values that exceed IDSS.
Depletion-Type MOSFETs
The DC AnalysisThe DC Analysis Same as the FET calculationsSame as the FET calculations
Plotting the transfer characteristics of the devicePlotting the transfer characteristics of the device Plotting the at a point that VPlotting the at a point that VGSGS exceeds the 0V or more positive values exceeds the 0V or more positive values Plotting point when VPlotting point when VGSGS=0V=0V andand IIDD=0A=0A The intersection between Shockley characteristics and linear The intersection between Shockley characteristics and linear
characteristics defined the Q-point of the MOSFETcharacteristics defined the Q-point of the MOSFET
The problem is that how long does the transfer characteristics have to The problem is that how long does the transfer characteristics have to be draw?be draw? We have to analyze the input loop parameter relationship.We have to analyze the input loop parameter relationship. As RAs RSS become smaller, the linear characteristics will be in narrow slope become smaller, the linear characteristics will be in narrow slope
therefore needs to consider the extend of transfer characteristics for therefore needs to consider the extend of transfer characteristics for example of voltage divider MOSFET,example of voltage divider MOSFET,
The bigger values of VThe bigger values of VPP the more positive values we should draw for the the more positive values we should draw for the transfer characteristicstransfer characteristics
SDGGS
RSGSG
RIVV
VVV
0
Depletion-Type MOSFETs
Analyzing the MOSFET circuit for DC Analyzing the MOSFET circuit for DC analysisanalysis
How to analyze dc How to analyze dc analysis for the shown analysis for the shown network?network? It is a …. Type networkIt is a …. Type network Find VFind VG G or V or VGSGS
Draw the linear Draw the linear characteristicscharacteristics
Draw the transfer Draw the transfer characteristicscharacteristics
Obtain VObtain VGSQGSQ and I and IDQDQ from from
the graph intersectionthe graph intersection
1. Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q-point.Use the ID at the Q-point to solve for the other variables in the voltage-divider bias
circuit. These are the same calculations as used by a JFET circuit.
When RS change…the linear characteristics will change..
1. Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q-point.
Use the ID at the Q-point to solve for the other variables in the voltage-divider bias
circuit. These are the same calculations as used by a JFET circuit.
The transfer characteristic for the enhancement-type MOSFET is very different from that of a simple JFET or the depletion-typeMOSFET.
Enhancement-Type MOSFET
Transfer characteristic for E-MOSFETTransfer characteristic for E-MOSFET
andand
2)( )( ThGSGSD VVkI
2)()(
)(
)( ThGSonGS
onD
VV
Ik
Feedback Biasing Arrangement
IG =0A, therefore VRG = 0V
Therefore: VDS = VGS
Which makes DDDDGS RIVV
1. Plot the line using VGS = VDD, ID = 0 and ID = VDD / RD and VGS = 0
2. Plot the transfer curve using VGSTh , ID = 0 and VGS(on), ID(on); all given in the
specification sheet.3. Where the line and the transfer curve intersect is the Q-Point.4. Using the value of ID at the Q-point, solve for the other variables in the bias
circuit.
Feedback Biasing Q-Point
DC analysis step for Feedback Biasing DC analysis step for Feedback Biasing Enhancement type MOSFETEnhancement type MOSFET
Find k using the datasheet or specification given;Find k using the datasheet or specification given;
ex: Vex: VGS(ON)GS(ON),V,VGS(TH)GS(TH)
Plot transfer characteristics using the formula Plot transfer characteristics using the formula
IIDD=k(V=k(VGSGS – V – VTT))22. Three point already defined that is I. Three point already defined that is ID(ON)D(ON), ,
VVGS(ON)GS(ON) and V and VGS(TH)GS(TH)
Plot a point that is slightly greater than VPlot a point that is slightly greater than VGSGS Plot the linear characteristics (network bias line)Plot the linear characteristics (network bias line) The intersection defines the Q-pointThe intersection defines the Q-point
ExampleExampleDetermine IDetermine IDDQQ and V and VDSDSQQ for network below for network below
Again plot the line and the transfer curve to find the Q-point.Using the following equations:
21
DD2G
RR
VRV
)( DSDDDDS
SDGGS
RRIVV
RIVV
Input loop :
Output loop :
Voltage-Divider Biasing
1. Plot the line using VGS = VG = (R2VDD)/(R1 + R2), ID = 0 and ID = VG/RS
and VGS = 0
2. Find k
3. Plot the transfer curve using VGSTh, ID = 0 and VGS(on), ID(on); all given in the specification sheet.
4. Where the line and the transfer curve intersect is the Q-Point.
5. Using the value of ID at the Q-point, solve for the other variables in the bias circuit.
Voltage-Divider Bias Q-Point
ExampleExampleDetermine IDetermine IDDQQ and V and VGSGSQQ and V and VDS DS for for
network belownetwork below
== -
-
=-=
- + )(
=
= -+
= - )( +
==
-)( ++ -
==
=-==
= -
= -= -
=+-=
= - +( )
== -
=
=+-
TroubleshootingTroubleshooting
N-channel VN-channel VGSQGSQ will be 0V or negative if properly checked will be 0V or negative if properly checked
Level of VLevel of VDSDS is ranging from 25%~75% of V is ranging from 25%~75% of VDDDD. If 0V . If 0V
indicated, there’s problemindicated, there’s problem Check with the calculation between each terminal and Check with the calculation between each terminal and
ground. There must be a reading, Rground. There must be a reading, RGG will be excluded will be excluded
For p-channel FETs the same calculations and graphs are used, except that the voltage polarities and current directions are the opposite. The graphs will be mirrors of the n-channel graphs.
P-Channel FETs
• Voltage-Controlled Resistor
• JFET Voltmeter
• Timer Network
• Fiber Optic Circuitry
• MOSFET Relay Driver
Practical Applications