CONFIDENTIAL
The Enab le r o f Low-Power Sys tems-on -Ch ip !
A secured way to design uLP ASIC/SoC
LUCILLE ENGELS – OPERATION MANAGER
SILICON TO SYSTEM – IMEC – 23 NOVEMBER 2016
CONFIDENTIAL
OVERVIEW
• Design an ASIC/SoC
• Application Context
• Ultra low-power ASIC/SoC design challenges
• Methodology for rigorous construction of a SoC
• Fabric IP to make the hard easy
• Verification methodology and EDA Solution for safe TTM
• Proven on silicon through a demochip
• Robustness of the IP offering and LP methodology in 55uLPeF
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CONFIDENTIAL
DESIGN AN ASIC/SOC
• Which gains compared to an FPGA?
➙ More functions in a smaller area/package
➙ Larger choice of IPs
➙ Lower power consumption
➙ Higher speed
➙ More robust
v IP protection
• What is needed?
➙ A set of technologies and silicon IPs
➙ Mastery of the design flows
v To be right on first silicon
➙ A Supply Chain
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APPLICATION CONTEXT
• IoT and wearable devices are battery powered
• Need to reduce the static power consumption
➙ For efficient sleeping
v Battery powered devices sleeping 99 % and active 1 %
➙ For efficient idling
v Wall plug powered household devices waiting for user input
v Wall plug powered network devices waiting for network traffic
• Need to optimize the dynamic power consumption
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THE WAY TO LOW POWER ASIC/SOC
• Similar to saving power in your house
• Saving power consumption in your ASIC requires
➙ not only architectural and integration rules and guidelines to be followed
➙ but also electrical verifications with VDD/VSS lines
• How to keep it easy?
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BE AWARE OF CHALLENGES IN LOW-POWER DESIGN
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Low-power architecture & Power management network selection
ü SoC Power consumption efficiency (FoM)
ü Number of power domains VS functionality
ü Type & number of voltage regulators VS performances
A
SoC implementation compliant with power intent
ü UPF – Unified Power Format
ü Power hierarchy VS functional hierarchy
B
Dft insertion
C
Physical implementation choice impact on the power consumption
ü Low power optimization through the physical implementation
D
Power management network control of: o power domains o power sources o clock generators
ü Transition check for functionality
ü Power control during the test
ü Check the startup state
E
In-rush current and transition times
ü Pairing VS in-rush current when turning on power domains
ü Transition Time check
F
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Identification of SoC functional blocks
Assemble the system or data bus for interactions between functions
A RIGOROUS METHODOLOGY TO DEFINE LOW-POWER SOC ARCHITECTURE
1 Identification of operating frequencies & voltages
Determine frequency constraints of each block to distribute clocks
2 Definition of the Voltage Regulator Network
Group functions into power domains and assemble the power supply network depending on power and clock domains
FoM computation and selection of the best solution
3 Identification of the control network & definition of mode change sequences
Handle mode transitions of power domains and control voltage regulators
4 Process & input voltages
Targeted performances Ø Main challenges Ø Noise sensitivities
Identification of SoC power modes for partitioning in power domains Ø Power state table & activity
scenario
Specification of the Activity Control Unit Ø Transition time requirements
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Identification of Application Schematics 5
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FROM A FUNCTIONAL BLOCK DIAGRAM …
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Interconnect
eFLASH
Memories MCU Cache Controller
Flash Controller Peripherals:
Wta GPIO DAC
Power Management
Unit
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Voice Activity Detector
WhisperTrigger
Logic island
Sesame libraries
SpRAM with embedded power
switch
RHEA-ERS
Micro controller
RISC-351 Zephyr
Cache controller
R-Stratus-LP
TSMC eFlash memory IOs
Audio DAC
sDACa-MT1
…TO A NETWORK OF POWERED ISLANDS
Digital Mic Speaker
TRC TRC TRC
• TRC – Transition Ramp Cell: control of the start-up of power sequence
Control Bus
ICU
System Bus
Maestro
12 MHz 200 MHz 100 MHz 24 MHz
1.2 V – 0.9 V – 0.75 V
1.2 V – 0.9 V – 0.55 V 1.8 V 1.2 V CLKmaestro
CLKmaestro CLKmaestro CLKmaestro
CLKmaestro CLKmaestro CLKmaestro CLKmaestro CLKmaestro 1MHz
CLKmaestro
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Retention Alternating Regulator
Switching Regulator
Linear Regulator
Retention Alternating Regulator
Switching Regulator
Linear Regulator
Retention Alternating Regulator
Switching Regulator
Linear Regulator
qLR-Aubrey POR
Mae
stro
Mae
stro
Mae
stro
Maestro Maestro
Maestro Maestro Maestro
Control Bus
Maestro
Maestro Maestro
Mae
stro
Maestro modules Always-on domain
3.3 V
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USING FABRIC IPS TO MAKE THIS NETWORK EASY
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Battery management
Power source selection
Power gating
AON Load #1 Load #2
• Battery charger
• Battery source selector
DELTA library: • Switching regulators • High drop-out Linear regulators • Low drop-out Linear regulators • Ultra-low quiescent regulators • Composite regulators
• Load Supply Selector
• CLICK universal power gating
Battery Charger
uLDO DC/DC
TRC TRC
mux
mux
Voltage Regulators
Power domain interfaces
• Level shifters • Isolation cells • ESD pro-
tection
• Level shifters • Isolation cells • ESD pro-
tection
Activity Control Logic
MaestroTM modules
Depend. Mediator Unit
Wake-up Interrupt Unit
Shift Control Unit
Domain Link Connector
Mode Switching Program
Island Control Unit
Main source Back-up source
Monitoring
• Comparators
• POR-BOR monitor
• BOR Battery monitor
• BOR Regulator monitor
• Voltage triggers
• Voice triggers
• Current flow trigger
Up to 5.5 V
Clocks
Save silicon area and BoM costs
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USING DEDICATED EDA FOR BUDGETING AND CHECKING POWER
• A budget-based approach
➙ To achieve lowest power with best area
➙ Track design performances up to tape-out
• Early decisions at architectural level
➙ Assess trade‐offs at early design stages
➙ Save time, area and power with mastery of noise issues
• Required Verifications
➙ For noise channel assessment
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0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Architectural RTL design Synthesis Place and Route
Power optimisation impact
Power Ga)ng
Analog sensi)vity
In Rush Current
Clock Ga)ng
Power States
Safe Time-to-Market
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PowerVision™ EDA Platform Mastering Noise on Power Supplies from early design stage
Dynamic verifications to secure tape-out:
• Mode Transition Checks (MTC) • Noise Propagation Checks (NPC)
CONFIDENTIAL
THROUGH A COMPLETE MASTERY OF ULP ASIC/SOC DESIGN FLOW
• By optimizing the number of power domains
• By selecting the best Power Regulation Network
• By making easy the power gating implementation
• By simplifying the control of power domains
• By enabling functional and electrical verifications (Noise and Mode Transition Checks)
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Demonstrated with TAISHAN
Demochip
Fabric IPs Missing EDA
links
Design effort
Power consumption
Minimize power Consumption
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UPF
SoC Specification
SoC architecture
Write the UPF
Synthesis
Write the SoC RTL assembly
Verification (functional and power)
P&R
Sign-off (STA, DRC/LVS, IR Drop)
Final GDSII
DOLPHIN’S OVERALL LOW-POWER FLOW AND CHALLENGE POSITIONING
SoC Specification
Definition of the power architecture through
Power Vision
SoC Architecture driven by the power consumption requirements (FoM)
Power Network Sizing IRDrop budgeting
List of verifications
A Low-power architecture
Write the UPF Write the SoC RTL assembly
B Power intent compliance
C DfT insertion
D Low-power physical implementation
Verification (functional and power)
Verification (functional and power)
E
F
Power management network control
In-rush current
Sign-off (STA, DRC/LVS, IR Drop)
CONFIDENTIAL
TAISHAN DEMOCHIP 12 MM² TSMC 55 NM ULP-EFLASH
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CONFIDENTIAL
SILICON CORRELATION OF WAKE-UP
• Wake-up the system from a sleep mode (extinction or retention) to an active mode without a transition impact
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1,E+02
1,E+03
1,E+04
1,E+05
1,E+06
1,E+07
1,E+08 RUN_M RUN_COOL RETENTION POFF RUN_HIGH CKOFF
IVD
DD
cu
rren
t p
ow
er c
on
sum
pti
on
(n
A)
Power modes
Current Power Consumption on TAISHAN VDDD_CORE per power mode
die 1
die 2
die 3
die 4
die 5
Divided by a factor > 1000
CONFIDENTIAL
KEY BENEFITS OF DOLPHIN SOLUTIONS
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55 nm ULP/ULP-eFlash Ultra low-power technology platform
+ Reference Design Flows
PPA & Low-Power
Silicon IP Low-power & High-density
Foundation IPs Feature IPs Fabric IPs
EDA Solutions and methodology Bridging the EDA gaps
Noise Propagation Checks Mode Transition Checks
Low-power Design Methodology Architectural Guidelines
Integration Guidelines and Rules
Foundry sponsorship +
Taishan demochip +
Dolphin’s complements
Design Services SoC integration of uLP SoCs
Technology and
Know-how safe construct
of an ultra-low power
SoC
COMPLETE OFFERING AND EXPERTISE FOR LOW-POWER SOC DESIGN
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QUESTIONS AND ANSWERS
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