802.3ab
A TutorialPresentation
802.3ab
1000BASE-T Tutorial Structure
• Introduction, Market & History– Colin Mick, The Mick Group
• Cabling– Chris DiMinico, Cabletron
• Channel and Overall Architecture– Sreen Raghavan, ComCore Semiconductor
• Technical Details– Sailesh Rao, Level One Communications
• Detailed VLSI Implementation– Mehdi Hatamian, Broadcom Corporation
802.3ab
One New Design Task for 1000BASE-T
• 5 Level Signaling costs 6dB in SNR– Get back with Forward Error Correction (FEC)
• Everything else has been done in:– 100Base-TX
– 125Msps
– DSP works– 100Base-T4
– Transmit/Receive on 4 channels– 100Base-T2
– ECHO and NEXT canceling
802.3ab
Where Does 802.3ab Fit?
Media Access Control (MAC)Full Duplex / Half Duplex
1000BASE-TEncoder / Decoder
1000BASE-X 8b/10bEncoder / Decoder
1000BASE-SXTransceiver
1000BASE-CXTransceiver
1000BASE-TTransceiver
Gigabit Media Independent Interface (GMII)
MAC
PHY
Fiber Channel Based Technology
1000BASE-LXTransceiver
|——————————802.3z——————————| |——802.3ab——|
802.3ab
Target Market
• 70% of installed UTP is CAT 5
• CAT 5 installed footage is growing 30% annually
0
10
20
30
40
50
60
70
80
90
100
1991 1992 1993 1994 1995 1996 1997
VoiceFiber OpticCoaxialSTPUTP
802.3ab
Market Applications
• Server Farms
• High performance work groups
• Graphic-based applications
• Network computers
• Shared gigabit networks
802.3ab
Objectives
• Comply with specifications for GMII of 802.3z.• Provide line transmission which supports full and half duplex
operation.• Provide FCC Class A/CISPR or better operation• Support operation over 100 meters of Category 5 balanced
cabling• Achieve bit Error Rate better than to 10-10
• Support Auto-Negotiation (Clause 28)• Meet susceptibility requirements• Support the objectives of 802.3z of Nov. 13, 1996
802.3ab
Foundations
• 100BASE-TX demonstrates sending a 3-level symbol streamover Category 5 cable at 125 Mbaud is possible and practical.
− 100BASE-TX DSP Based Phys now available• 100BASE-T4 demonstrates techniques for sending multi-level
coded symbols over four pairs.• 100BASE-T2 demonstrates the use of digital signal processing
(DSP), five-level coding, and simultaneous two-way datastreams while dealing with alien signals in adjacent pairs
802.3ab
Timeline
Milestone 802.3z 802.3abWork starts November 95 November 95
PAR received March 96 March 97
1st draft January 97 November 97
WG ballot July 97 March 98*
LMSC ballot November 97 July 98*
Ready for std June 98* December 98*
802.3ab
Status
• Now reviewing D2-0
• Task force doing final tuning on D2-0 during this Plenary.
• On-track to request permission to go to working groupballot at this Plenary
802.3ab
Cabling
• Topology
• Cabling Specifications
• Cabling standards
802.3ab
Channel Cabling Topology
building Cablecross-connectionequipmentcable
work areacable
connecting hardware
transition point
telecommunicationsoutlet/connectorequipment
TIA/EIA - 568-A Channel (w/o transition Point) = ISO 11801 Channel
Cross-Connect Topology
802.3ab
Installed Cabling
• Minimizes connections• Minimizes crosstalk, both near-end and far-end• Minimizes return loss and insertion loss
building Cable
interconnection
equipmentcable work area
cable
connecting hardwaretelecommunicationsoutlet/connector
equipment
Recommended Interconnect Topology
802.3ab
Cabling Performance Specifications
Based on Category 5 Installed Cabling
• Project Authorization Request (PAR) for the 1000BASE-T project specificallyrequires operation on four pair 100 ohm Category 5 balanced copper cabling asdefined by TIA/EIA-568-A, or its equivalent as built from material specified byISO/IEC 11801: 1995 that meets the channel performance parameters specifiedin TIA/EIA-568-A ANNEX E.
Additional cabling specifications: Draft Addendum to ANSI/TIA/EIA-568-A:
• Additional specifications for FEXT (ELFEXT) and return loss, not currentlyspecified by TIA/EIA-568-A, are being developed developed to characterizethe vast majority of the installed base of Category 5 cabling built to TIA/EIA-568-A and/or ISO/IEC 11801clauses 6, 8 & 9.
• An addendum to ANSI/TIA/EIA-568-A will include the additional transmissionperformance specifications and field test parameters for FEXT (ELFEXT) andreturn loss.
802.3ab
Field Testing
A verification of the installed cabling performance perthe field test specification of ANSI/TIA/EIA-TSB-67-"Transmission Performance Specifications for FieldTesting of Twisted Pair Cabling System" with theadditional test parameters for FEXT (ELFEXT) andreturn loss (to be released as an addendum to TIA/EIA-568-A) will be recommended.
802.3ab
Cabling Specifications
Frequency(MHz) Return Loss(dB) 1<=f<20 15 20<=f<100 15 - 10*LOG(f/20)
• 40.8.2.1 Insertion Loss
.4/ff*2.1loss(f)Insertion_ 0.529 +<
• 40.8.2.3 Return Loss
802.3ab
Channel Return Loss
C h a n n e l C o n f ig u r a t io n R e tu r n L o ss
- 7 0
- 6 0
- 5 0
- 4 0
- 3 0
- 2 0
- 1 0
0
0 2 0 4 0 6 0 8 0 1 0 0
M H z
dB
m a n u f 1 - O r a n g e p a ir 2 0 m
m a n u f 1 - B r o w n p a ir 2 0 m
m a n u f 1 - B r o w n p a ir 5 0 m
m a n u f 1 - B r o w n p a ir 9 0 m
1 5 - 1 0 *L O G ( f / 2 0 )
1 7 - 1 0 *L O G ( f / 2 0 )
m a n u f 2 - 2 0 m
802.3ab
Channel Insertion Loss
Insertion Loss Model - Category 5 100 Meter Measured Link, Measured Link Scaled & EIA-568-A Annex E Insertion Loss Limit
0
2
4
6
8
10
12
14
16
18
20
22
24
26
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79 82 85 88 91 94 97 10 0
Frequency (MHz)
Inse
rtio
n L
oss
(d
B)
Measured Link
Measured Link Scaled
EIA-568-A Annex E Limit
802.3ab
Coupling Parameters (Crosstalk)
• 40.8.3.1 Differential Near-End Crosstalk (NEXT) LossThe NEXT loss between all duplex channels of a link segment shall begreater than 27.1 - 16.8Log10 (f/100).
• 40.8.3.2 Equal Level Far-End Crosstalk (ELFEXT) Loss The worst pair ELFEXT loss between a duplex channel shall be greater than 17 - 20Log 10 (f/100) dB
• 40.8.3.2.1 Multiple Disturber Far-end Crosstalk (ELFEXT) Loss1. 17.0 - 20Log 10 (f/100) dB.2. 19.5 - 20Log 10 (f/100) dB.3. 23.0 - 20Log 10 (f/100) dB.
PSELFEXT loss is 14.4-20*log(f/100)
802.3ab
Channel Next
Channel NEXT
-140
-120
-100
-80
-60
-40
-20
0
0 20 40 60 80 100
MHz
dB
NEXT Model 2 (Lucent)
NEXT Model 3 (Lucent)
NEXT Model 4 (Lucent)
TIA/EIA-Channel Limit
802.3ab
Channel and Overall Architecture
• Design Tasks
• Design Approach
• Receiver Startup
802.3ab
Gigabit Over CAT-5 Copper Cable
• Topology -- Link segment of a 4-Pair Cat-5 Cable. Each pair a fullduplex channel supporting effective data rate of 250Mbp/s in bothdirections simultaneously
– ECHO, SELF NEXT and FEXT• Hybrid to cancel most of the NEAR END ECHO• Adaptive cancellers to reduce remaining ECHO and SELF NEXT
• Signal to Noise Ratio (SNR) 6dB Less Than 100Base-TX due to5-level signaling– Provide 6dB coding gain in the form of a 4-D Trellis code
• Channel Impairments– 20dB signal attenuation at 62MHz at 100 meters
• Incorporate decision feedback channel equalization– External Noise
• FCC imposed limits on transmit levels– Limit transmit spectrum above 30MHz
• Partial Response spectral shaping at the transmitter (3/4 + 1/4Z-1)
802.3ab
Major Receiver Design Tasks
• A/D conversion– 125 Mega samples per second Conversion
• Frequency Locking and Timing Recovery– Low Jitter Phase Locked Loop for clock recovery
• FEC – 4D-8 State Trellis Code– Design of critical timing path involving Trellis
decoder and decision feeback equalizer
802.3ab
<--------Insertion Loss
NEXT_41
FEXT_31
FEXT_21
FEXT_41
NEXT_31
NEXT_21
250Mb/S
250Mb/S
250Mb/S
250Mb/S
250Mb/S
250Mb/S
250Mb/S
250Mb/S
T
T
T
T
R
R
R
R
HYBRID
HYBRID
HYBRID
HYBRID
T
T
T
T
R
R
R
R
HYBRID
HYBRID
HYBRID
HYBRID
Near ECHOFar Echo
Gigabit Ethernet over CAT-5 Cable
(using 4 wire pairs)
802.3ab
MLT-3 and PAM-5 Signal Levels
Recover the 6dB of SNR -- Add Forward Error Correction (FEC)
Time (in ns)
Eye pattern of PAM-5 signaling
Time (in ns)
Eye pattern of MLT-3 signaling
1 volt
.5 volt
802.3ab
Transmitter
GMII PCS
DAC
DAC
DAC
DAC
Tx1
Tx2
Tx3
Tx4
125 MBaud5-PAM
14/14/3 −+ z
14/14/3 −+ z
14/14/3 −+ z
14/14/3 −+ z
Similar to 100Base-TX New DSP forGigabit
New Analogfor Gigabit
802.3ab
DSP Based Receiver Block Diagram
Hybrid
AnalogFront Endincl. A/D
Converter
DSP Based Receiver FECCAT-5Cable
Transmitted Data This Channel
To EchoCanceller
ClockRecovery
Recoveredand
CorrectedData
Transmitted Data --Other Channels
To NEXTCancellers
Added FECfor
Gigabit
802.3ab
Typical 100TX DSP Based Receiver
Feed ForwardEqualization
Slicer(comparators)
OutputData
RemovePrecursor
ISI
Reconstruction ofTransmitted Data
+
DFE
A/DAnalog
Input
Recovered
Clock
Ideal sliceddataError
AdjustsCoefficients
ErrorAdjusts
CoefficientsError is the differencebetween Ideal Sliced Data andReconstruction ofTransmitted Data Remove Post-
Cursor ISI
AnalogFrontEnd
(AFE)
802.3ab
Detail of DFE Based Equalizer{ Xk } T T T
X
+
mk
T T T
{Zk} +
X X X
+
c0ff c1ffcnff
-
b0fbb1fbbnfb
{ Dk }
X X
+
Feed Forward Equalizer
Feedback EqualizerFBE
Slicer
The error signal used to setthe coefficients (c0ff - cnff andb0fb - bnfb) is the differencebetween mk (the actual inputto the slicer) and xk (theoutput of the slicer -- theideal signal level)
++ -
802.3ab
Gigabit Receiver With FEC
NEXTCanceller
Feed ForwardEqualization
ViterbiDecoder
DFE #1
DFE #N
ECHOCanceller
NEXTCanceller
NEXTCanceller
+ ReceiveData
TX output channel 1
TX output channel 2
TX output channel 3
TX output channel 4
Removes PostCursor ISI(both from
channel andPR shaping)
RemovePrecursor
ISI
Provides 6dBcoding gain
Decision FeedbackEqualizers.
.
Input Samples to Viterbi
+
-
8
From Other Channels
A/Dconv
AFE
Recovered Clock
ReceiveSignal
802.3ab
PHY Start-up
• 1000BASE-T Start-up protocol provides for two differentstart-up procedures for maximum robustness while
preserving complete interoperability:
- Blind Start-up: where all adaptive filter blocks converge without sequencing. If the PHYs at the two ends of the link bothimplement this procedure (which is determined during the autonegotiation), the sequenced start-up is bypassed.
- Sequenced Start-up: where the convergence of various adaptive blocks are separated in a 3 step sequence.
802.3ab
Eye Diagrams (master sequenced start-up)
802.3ab
100BASE-TX Receiver 1000BASE-T Receiver
A/D Conversion 5.5 bit ideal at 125MSamples/sec 7 bit ideal at 125MSamples/sec
DFE 10 Taps 14 Taps/Channel
FFE 8 Taps 12 Taps/Channel
NEXT Cancellers 0 75 Taps/Channel
ECHO Canceller 0 60 Taps
Critical Path 3 Input Add
+ 3 Input Select
+ 1 Slicer
4 Input Add-Compare Select
+ 3 Input Add
+ 5 Input Select
+ Branch Metric Compute
Normalized Gate Complexity 1 8
Receiver Design Parameter Comparison
802.3ab
Technical Details of 1000BASE-T
• 1000BASE-T Topology
• Operation of 1000BASE-T
• Signaling
• Trellis Coded Modulation
• Performance Evaluations
802.3ab
1000BASE-T Topology
Link Segments
1000BASE-TMaster PHY
1000BASE-TSlave PHY
Externaltiming
Tx
Rx
Tx
Rx
Tx
Rx
Tx
Rx Recovered
timingTx
Rx
Tx
Rx
Tx
Rx
Tx
Rx
802.3ab
Block Diagram of Transceiver
HybridRECEIVER_B
Analog
HybridN EXT
Canceller
ECHO
Canceller
VGA
Cable
TRANSMITTER_A
RECEIVER_A
Gain, Timing
TRANSMITTER_B
+
1000 Mb/s
D ig ital Transmit
A nalogReceiveFilter
D igital LinearFeedForwardEqualizer
TransmitFilterFilter
Pair A
Pair B
G
I
I
Control
Side-StreamScrambler
SymbolEncoder
Side-StreamDescrambler
ViterbiDeco der
Escape + Controls
&
&
Escape + Controls
A/D
D /A
M
N EXT
Canceller
N EXT
Canceller
HybridRECEIVER_C
TRANSMITTER_C
HybridRECEIVER_D
TRANSMITTER_D
Pair C
Pair D
DFE +
802.3ab
Transmitter
Transmit Spectrum of 1000BASE-T
Pulse TemplateExample Implementation of Transmitter
D
0.250.75
SLOPE
DAC
Digital Transmit Filter
An
BI_DA
CONTROLLED
802.3ab
Signaling Features
• Forward Error Correction (FEC) coded symbol mapping fordata
• Algorithmic mapping and inverse mapping from octet data to aquartet of quinary symbols and back
• Uncorrelated symbols in the transmitted symbol stream• No correlation between symbol streams traveling both directions
on any pair combination• No correlation between symbol streams on pairs A, B, C and D• Ternary symbol mapping in idle and training modes to ease
blind startup and retraining
802.3ab
Signaling Features (cont.)
• Ability to rapidly or immediately determine if a symbolstream represents data, idle or carrier extension
• Robust delimiters for SSD, ESD, and other control signals
• Ability to signal the status of the local receiver to the remote PHY to indicate that the local receiver is not operating reliably and requires retraining
• Ability to automatically detect and correct for pair swapping and unexpected cross-over connections
• Ability to automatically detect and correct for incorrectpolarity in the connections
• Ability to automatically correct for differential delay variations across the wire-pairs
802.3ab
Side Stream Scrambler
• Side Stream Scrambler employed by Master PHY
• Side Stream Scrambler employed by Slave PHY
802.3ab
Random Bits for Octet Scrambling
Scrn-1
[0]
T
Scrn-1 [12] Scrn-1
[13] Scrn-1
[32]
T T T TT T T T T T
Scr_Bn-1 [0]
T T T T T T T T
Scr_Cn-1[0]
T T T T T T T T
Scr_Dn-1
[0]
T T T T T T T T
Syn[2]
Sxn[2]
Sgn[2]
Syn[1]
Sxn[1]
Sgn[1]
Syn[0]
Sxn[0]
Sgn[0]
Syn[3]
Sxn[3]
Sgn[3]
802.3ab
Symbol Mapping Reference Diagram
Odd/EvenCoding
Scrambling &
EncodingConvolutional
SymbolMapping
SignEncoding
SnAn
SnBn
SnCn
SnDn
tx_enablen
tx_enablen tx_errorn
Tx_Dn[0:7]
Sxn[0:3]
Syn[0:3]
Sgn[0:3]
Scn[0:7] Sdn[0:8]
TAn
TBn
TCn
TDn
An
Bn
Cn
Dn
tx_enablen
802.3ab
Trellis Coded Modulation
Purpose: To match the robustness of 3-level 100BASE-TX signaling with 5-level 1000BASE-T signaling
• Implemented as a two-step approach:- Convolutional Encoding to convert scrambled octet data to 9-bit word.- Mapping by Set Partitioning to get 6dB noise immunity gain.
Scrambler
Tx_D n[0:7]
Scn[0:7]
(Bitwise XOR)
T T T
Sdn[0]Sd
n[1]
Sdn[2]
Sdn[3]Sdn[4]Sdn[5]Sd
n[6]
Sdn[7]
Sdn[8]
Subset
PointsinSubset
Index
coding_enable
802.3ab
Subset Mapping
• Partition 5-levels into 2 1-D subsets:X={-1,+1}, Y={-2,0,+2}.
• Squared distance between elements in 1D subset is 4.
802.3ab
Trellis Diagram
Convolutional Encoder Bits at time n
Convolutional Encoder Bits at time n+1
D0 D2 D4 D6
D1 D3 D5 D7
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
D2 D0 D6 D4
D3 D1 D7 D5
D4 D6 D0 D2
D5 D7 D1 D3
D6 D4 D2 D0
D7 D5 D3 D1
D0 D2 D4 D6
D2 D0 D6 D4
D4 D6 D0 D2
D6 D4 D2 D0
D1 D3 D5 D7
D3 D1 D7 D5
D5 D7 D1 D3
D7 D5 D3 D1
802.3ab
Sequential Decoding
• Squared distance between valid paths is also 4.D2
D1
D6
D3
802.3ab
Packetizing the Trellis Code
• Idle/Carrier Extension use 3-level signaling i.e. D0 subset
• Data uses Trellis Coding• Reset convolutional encoder states to zero using two
symbol periods at End of Packet
Data Packet => Any State
Idle => State 000 Idle => State 000
CsresetSSD
ESD
802.3ab
1000BASE-T Frame Structure
tx_enablen
SSDn
ESDn
TXD[7:0]
Data stream
An
IDLE IDLEESDDATASSDBn
csresetn
csreset
IDLE IDLEESDDATASSD csreset
IDLE IDLEESDDATASSD csreset
IDLE IDLEESDDATASSD csreset
Cn
Dn
802.3ab
Performance Evaluations
• Worst Case 100m UTP-5 Channel characteristics.
• Design Point - 10dB• Design Point Simulations• Matlab Code Published
802.3ab
Worst Case 100m UTP-5 Channel
802.3ab
Design Point - 10dB
• D/A: 17 levels at 125MHZ• Launch Level: 2V P-P• Analog Transmit Filter: Single pole RC• Analog Receive Filter: BW2@100MHz• A/D: 6.5bits ideal at 125MHz
2.2 Volts p-p (prob. of clipping 1E-25)• Baseline Wander Correction: Digital• FFE - #taps: 16 taps at 125MHz• DFE - #taps: 12 taps at 125MHz• NEXT Cancellers - #taps: 72 taps at 125MHz• Echo Canceller - #taps: 120 taps at 125MHz• Viterbi Decoder: 12-stage• Total worst-case latency: 31BT < 40BT• Uniform Jitter Tolerance for 0dB margin: 1.5ns P-P [>10ns P-P Gaussian]• Worst-Case noise immunity: Crane Test: 140mV P-P• Est. Gate Count/Power Consumption: 330K/4W• Margin without FEXT: 10.5dB• Margin with Worst-Case FEXT: 5.7dB
802.3ab
Design Results - 10dB
802.3ab
Design Results - 10dB
802.3ab
Detailed VLSI Implementation
• DSP Requirements
• Technology Background
• Power requirements
• Size and Layout
802.3ab
Transceiver Block Diagram
Blocks common between a Quad 100Base- TX and a 1000BASE-Ttransceiver. NEXT and Echo cancellers are the major blockscontributing to the added complexity over a Fully digital Quad-TX.
802.3ab
DSP Requirements
• 4 Equalizers (FFE/ FBE), 4 echo cancellers, 12 NEXT cancellers running at 125 MHz clock rate which is also theBaud rate
• The bulk of the computation is in the adaptive Finite ImpulseResponse (FIR) filters
• The regularity of the filter structures makes the design taskquite manageable
802.3ab
Direct Form FIR Filter
802.3ab
Adaptive FIR
In an adaptive filter, in general, the output of the filter, y(n), is comparedagainst a desired reference r(n) which produces a measure to be used in analgorithm for modifying the filter coefficients (a time varying system). Thefilter coefficients are modified in a way to minimize the measure and bringthe filter output close to the desired output. In an important class of adaptivefilters, adaptation of the coefficients take place without any reference input.This is called blind adaptation.
The most widely used adaptation algorithm is the Least Mean Square(LMS) method where e (n) = r (n) - y (n) and the update is chosen tominimize e2.
802.3ab
Linear Equalizer with LMS Update
The equalizers, NEXT cancellers and echo cancellers in a 1000Base- Ttransceiver are all variations of this filter structure.
802.3ab
Echo Canceller Tap
802.3ab
Power Consumption
• Corresponds to about 400,000 gates
• Comparing to Quad-TX:
Fully digital Quad-TX, 3.3V, 0.50 µ CMOS 2.2W
1000BASE-T, 2.5V, 0.25 µ CMOS 3.1W
• A worst case DSP complexity providing a very high margin ofoperation:
802.3ab
1000BASE-T Copper Transceiver Layout
• 0.25mm CMOS, 5 layer metal
• Based on actual layout from a 0.25mm CMOS library
• 4mm X 4mm active area (65% - 75% of the area of most existing 10/100 PHYs)
• 160 pins
802.3ab
3 Steps From 100Base-TX to 1000BASE-T
• Start with a 100Base-TX DSP Based PHY
• Use all four channels full duplex– 400 MBps in both directions– Requires ECHO and NEXT canceling– Requires Master/Slave Clocking
• Remove 4B/5B Encoding– 500 MBps in both directions
• 5 Level Signaling - 2 Bits/Symbol– 1000 MBps in both directions– Requires FEC to get back the 6dB SNR
• The major task was adding FEC