a module solution provider
AAAL115JS-C1
AP module solution
Datasheet
Revision D01
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History change AAAL115JS-C1:A5-LGA97 SIP module
Revision Date Description D01 2016/05/13 Initial version
BO1NA1411B-E0:A5-LGA97 EVM Board
Revision Date Description D03 2016/05/13 Initial version
BO1NA1411B-S0:A5-LGA97 N5600 Barcode Scanner Board
Revision Date Description D01 2015/09/17 Initial version
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Table of Contents
1. Feature Summary ................................................................................................... 1 1.1. Overview Main Part MPU (SAMA5D3) in SIP module ................................ 1 1.2. AAAL115JS-C1 module Specification Table ................................................ 2 1.3. Software Support ....................................................................................... 3
1.3.1. Atmel Linux .................................................................................... 3 1.3.2. Jorjin Software Package ................................................................. 3 1.3.3. HoneywellSensor Driver Package ................................................... 3
2. Package and Pinout ................................................................................................ 4 2.1. 97-Pin LFLGA Package (18x14x1 mm, Pitch=0.65mm) ............................... 4 2.2. 97-Pin LFLGA Package Pinout ..................................................................... 5 2.3. Input/ Output Description ......................................................................... 8
3. Power Considerations ............................................................................................ 9 3.1. Power Supplies ........................................................................................... 9 3.2. Power-Up Considerations ........................................................................ 10 3.3. Power-Down Considerations ................................................................... 11 3.4. AAAL115JS-C1 module for SIP Technology .............................................. 11
4. Block Diagram and Interfaces .............................................................................. 12 4.1. Block Diagram .......................................................................................... 12 4.2. ISI (Image Sensor Interface) ..................................................................... 13 4.3. USB Device High Speed Port (UDPHS) ..................................................... 14
4.3.1. UDPHS Embedded Characteristics ............................................... 14 4.3.2. USB Device Port Typical Connection ............................................ 14 4.3.3. UDPHS Power Management ........................................................ 14 4.3.4. UDPHS Interrupt Sources ............................................................. 14
4.4. USB Host High Speed Port (UHPHS) ......................................................... 15 4.4.1. UHPHS Embedded Characteristics ............................................... 15 4.4.2. USB Host Port Typical Connection ............................................... 15
4.5. USB Host Port-A Shared with UDPHS Functional Description ................. 15 4.5.1. UTMI Transceivers Sharing ........................................................... 15
4.6. High Speed Multimedia Card Interface (HSMCI) ..................................... 16 4.6.1. HSMCI Application Block Diagram ............................................... 16 4.6.2. HSMCI Power Management ......................................................... 16 4.6.3. HSMCI Interrupt Sources.............................................................. 16
4.7. Serial Peripheral Interface (SPI) ............................................................... 17 4.7.1. SPI Application Block Diagram ..................................................... 17 4.7.2. SPI Power Management ............................................................... 17 4.7.3. SPI Interrupt Sources ................................................................... 17
4.8. Two-wire Interface (TWI ) ........................................................................ 18 4.8.1. TWI I/O Lines Description ............................................................ 18 4.8.2. TWI Power Management ............................................................. 18 4.8.3. TWI Interrupt Sources .................................................................. 18
4.9. Debug Unit (DBGU) .................................................................................. 19 4.9.1. DBGU Embedded Characteristics ................................................. 19 4.9.2. DBGU I/O Lines Description ......................................................... 19
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4.9.3. DBGU Power Management .......................................................... 19 4.10. Universal Synchronous Asynchronous Receiver Transceiver (USART) . 19
4.10.1. USART I/O Lines Description ........................................................ 19 4.10.2. USART Power Management ......................................................... 19
5. Electrical Characteristic ........................................................................................ 20 5.1. Absolute Maximum Rating ....................................................................... 20 5.2. DC Characteristics .................................................................................... 21 5.3. 12 MHz RC Oscillator Characteristics ....................................................... 22 5.4. 32 kHz RC Oscillator Characteristics ......................................................... 22 5.5. Power Consumption ................................................................................. 23
5.5.1. Static Current ............................................................................... 23 5.5.2. Active Mode ................................................................................. 23 5.5.3. Low-power Modes ....................................................................... 23
6. Mechanicals ......................................................................................................... 25 6.1. AAAL115JS-C1 module Size for Bottom View .......................................... 25 6.2. AAAL115JS-C1 module Signal Description List ......................................... 27 Table 24. AAAL115JS-C1 Module Signal Description List ..................................... 27
7. Design Guidelines ................................................................................................. 28 7.1. General Rules and Constraints ................................................................. 28 7.2. PCB Layout Recommendations ................................................................ 28
7.2.1. MMC Power Signals ..................................................................... 28 7.2.2. MMC Signals ................................................................................ 28 7.2.3. Parallel Display Signals ................................................................. 29 7.2.4. USB signals ................................................................................... 29
7.3. Reliability Compliance .............................................................................. 30 8. BO1NA1411B-E0 EVM Board ............................................................................... 31
8.1. BO1NA1411B-E0 EVM Board Function Block .......................................... 31 8.2. BO1NA1411B-E0 EVB Board Specification ............................................... 32 8.3. BO1NA1411B-E0 EVB Board Test Report ................................................. 32
9. Appendix_A:BO1NA1411B-E0 Component Location ........................................ 33 10. Appendix_A:BO1NA1411B-E0 Schematics........................................................ 34 11. Appendix_A:BO1NA1411B-S0 Component Location ........................................ 40 12. Appendix_A:BO1NA1411B-S0 Schematics ........................................................ 41
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List of Table Table 1. AAAL115JS-C1 module Specification Table ......................... 2 Table 2. AAAL115JS-C1 module Pinout for LFLGA-97 Package ....... 5 Table 3. SAMA5D3 I/O Type Description ........................................... 8 Table 4. SAMA5D3 I/O Type Assignment and Frequency ................. 8 Table 5. AAAL115JS-C1 module Power Supplies .............................. 9 Table 6. Power-Up Timing Specification .......................................... 10 Table 7. Power-Up Timing Specification .......................................... 11 Table 8. ISI I/O Lines ....................................................................... 13 Table 9. UDPHS Peripheral ID ......................................................... 14 Table 10. HSMCI1 I/O Lines for 4-bit Configuration ......................... 16 Table 11. HSMCI Peripheral ID ........................................................ 16 Table 12. SPI0 I/O Lines .................................................................. 17 Table 13. Peripheral IDs .................................................................. 17 Table 14. Atmel TWI Compatibility with I2C Standard ..................... 18 Table 15. TWI I/O Lines Description ................................................ 18 Table 16. Peripheral IDs .................................................................. 18 Table 17. Debug Unit Pin Description .............................................. 19 Table 18. USART I/O Lines Description ........................................... 19 Table 19. Absolute Maximum Rating ............................................... 20 Table 20. DC Characteristics ........................................................... 21 Table 21. 12 MHz RC Oscillator Characteristics .............................. 22 Table 22. 32 kHz RC Oscillator Characteristics ............................... 22 Table 23. Low-power Mode Configuration Summary ....................... 24 Table 24. AAAL115JS-C1 Module Signal Description List ............... 27 Table 25 BO1NA1411B-E0 EVM Board Specification Table ............ 32
List of Figure Figure 1. 97-Pin LFLGA Pin Map ....................................................... 4 Figure 2. Recommended Power-Up Sequence ............................... 10 Figure 3. Recommended Power-Up Sequence ............................... 11 Figure 4. AAAL115JS-C1 Block Diagram ......................................... 12 Figure 5. USB Device Port Board schematic ................................... 14 Figure 6. USB Host Port Board schematic ....................................... 15 Figure 7. USB Selection .................................................................. 15 Figure 8. HSMCI Application Block Diagram ................................... 16 Figure 9. SPI Application Block Diagram ......................................... 17 Figure 10. AAAL115JS-C1 module Size for Bottom View ................ 25 Figure 11. AAAL115JS-C1 module Pin define for Top View ............. 26 Figure 12 Reflow Profile (1) ............................................................. 30 Figure 13 Reflow Profile (2) ............................................................. 30 Figure 14. BO1NA1411B-E0 EVM Board Function Block ................ 31
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1. Feature Summary Jorjin’s AAAL115JS-C1 is a feature-rich Application Processor module specifically designed for Barcode Scanning applications. With proper MPU and barcode decoding library, customers can leverage AAAL115JS-C1 to build a wide range of devices, ranging from a handheld scanner to a full-featured Smart Terminal with highly accurate scanning performance. AAAL115JS-C1 integrates a Atmel SAMA5D3 ARM Cortex-A5 (up to 536GHz)、LPDDR2 1Gbit (32M x 32bit)、NAND Flash 1Gbit (128M x 8bit) . AAAL115JS-C1 provides High Speed USB2.0 interface and RS232, allowing faster barcode data transmission and beyond BO1NA1411B offers exceptional scanning performances on 1D and 2D barcodes and is ideal for scan intensive applications where productivity is a key with power manager. SAMA5D3-LFLGA97 size is the 18 mm (W) x 14 mm (D) x 1mm (H), matching very tight design constraints. You can choose the hardware configuration that best suits your design.
1.1. Overview Main Part MPU (SAMA5D3) in SIP module
The SAMA5D3 MPUs using a 65nm low-power process technology to deliver up to 850DMIPS at 536MHz while offering 1328MB/s at 166MHz bus speed. The floating point unit (FPU) also provides additional high-precision processing power for image, audio and sensor data. The SAMA5D3 series delivers market-leading low-power consumption under 200mW in active mode at maximum speed and below 0.5mW in low-power mode when retaining context and offering fast wake-up. All these features make the SAMA5D3 series ideal for high-performance industrial applications requiring high-precision computing and low power, including interfaces, programmable logic controllers, barcode scanners or printers, terminals and battery-operated applications. NOTE: This architecture is configured with different sets of features in different devices. This technical reference manual details all of the features available in current and future SAMA5D3 devices. Some features may not be available or supported in your particular device. For more information, see SAMA5D3 datasheet and Application Notes and your device-specific data manual.
The architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: • Streaming video • 2D/3D gaming • Video conferencing • High-resolution still image The architecture of AAAL115JS-C1 module is designed to provide maximum flexibility in a wide range of end applications including but not limited to: • Portable Data Terminals • Navigation • Auto Infotainment
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• Gaming • Medical imaging • Home Automation • Human Interface • Industrial Control • Test and Measurement • Single board Computers
1.2. AAAL115JS-C1 module Specification Table
Table 1. AAAL115JS-C1 module Specification Table
AAAL115JS-C1 module Specification
Processor
Atmel SAMA5D31 ARM Cortex-A5 processor with ARM v7-A Thumb2 Instruction set core frequency up to 536MHz
System running up to 166 MHz – Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and RTC – Boot Mode Select Option, Remap Command – Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillator – Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
Low Power Management – Shut Down Controller – Battery Backup Registers – Clock Generator and Power Management Controller – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
SDRAM (Design in SIP module)
LPDDR2 1Gbit (32Mx32bit, 1066 Mbps, VDD1 = 1.8V, VDD2/VDDQ = 1.2V)
FLASH (Design in SIP module)
NAND Flash 1Gbit (128Mx8bit, VCC = 2.7V~3.3V)
Interface
Image Sensor Interface ( ISI ) – ITU-R BT. 601/656 8-bit mode compliant sensors
– Supports up to 12-bit Grayscale CMOS Sensors – Supports Barcode Scanner module support Honeywell N5600 – Supported CMOS Sensor:OV2640 , OV2643 , OV5640 , OV7740 and OV9740
1 x USB 2.0 High Speed Host or Device Port – USB High Speed Device Port Compliant with the USB V2.0 High Speed device Specification. – USB High Speed Host Port Compliant with USB V2.0 HS(480Mbps)/ FS(12Mbps)/
LS(1.5Mbps) Specification
1 x 4bit SDIO SD Port (HSMCI1, High Speed Memory Card Interface 1) – Compatible with Multi Media Card (MMC) Specification V4.3 – Compatible with SD Memory Card Specification V2.0 – Compatible with SDIO specification V2.0 – Compatible with CE-ATA Specification V1.1
1 x Serial Port (USART1 with RTS/CTS handshake)
1 x I2C Port (TW1, Two-Wire 1 Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS)
1 x SPI Port (SPI0, Serial Peripheral Interface 0)
1 x DBGU Port
Package Type LFLGA-97Pin
Module Size (L x W x H mm)
18 x 14 x 1 mm
OS Linux or RTOS-less
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1.3. Software Support
1.3.1. Atmel Linux
Jorjin has created our BSP base on Atmel’s release and modify for our SIP’s feature. BSP
information as below,
• Uboot(2013.07).
• Bootstrap(3.6.2).
• dtb(for sama5d3-ek).
• kernel(3.10).
• rootfile system.
• compile tool.
1.3.2. Jorjin Software Package Coming soon.
1.3.3. HoneywellSensor Driver Package Please contact Jorjin’s sales.
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2. Package and Pinout Figure 1 show the Pin map of the AAAL115JS-C1 (LFLGA-97 Pin Package).
2.1. 97-Pin LFLGA Package (18x14x1 mm, Pitch=0.65mm)
Figure 1. 97-Pin LFLGA Pin Map
Bottom View
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2.2. 97-Pin LFLGA Package Pinout
Table 2. AAAL115JS-C1 module Pinout for LFLGA-97 Package
*Page-5. JJA5D3 module Pin number is total 35 pin.
Jorjin Atmel
Power Rail I/O Type
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State
LFLGA-97-Pin LFBGA-324-ball
Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir
Signal, Dir, PU,
PD, HiZ, ST Pin Pin Name Ball
51 ISI_D0_PA16 H3 VDDIOP0 GPIO PA16 I/O — — LCDDAT16 O — — ISI_D0 I PIO, I, PU, ST
47 ISI_D1_PA17 H6 VDDIOP0 GPIO PA17 I/O — — LCDDAT17 O — — ISI_D1 I PIO, I, PU, ST
54 ISI_D2_PA18 H4 VDDIOP0 GPIO PA18 I/O — — LCDDAT18 O TWD2 I/O ISI_D2 I PIO, I, PU, ST
48 ISI_D3_PA19 H7 VDDIOP0 GPIO PA19 I/O — — LCDDAT19 O TWCK2 O ISI_D3 I PIO, I, PU, ST
53 ISI_D4_PA20 H2 VDDIOP0 GPIO PA20 I/O — — LCDDAT20 O PWMH0 O ISI_D4 I PIO, I, PU, ST
49 ISI_D5_PA21 J6 VDDIOP0 GPIO PA21 I/O — — LCDDAT21 O PWML0 O ISI_D5 I PIO, I, PU, ST
52 ISI_D6_PA22 G2 VDDIOP0 GPIO PA22 I/O — — LCDDAT22 O PWMH1 O ISI_D6 I PIO, I, PU, ST
50 ISI_D7_PA23 J5 VDDIOP0 GPIO PA23 I/O — — LCDDAT23 O PWML1 O ISI_D7 I PIO, I, PU, ST
56 ISI_VSYNC_PA30 H1 VDDIOP0 GPIO PA30 I/O — — TWD0 I/O URXD1 I ISI_VSYNC I PIO, I, PU, ST
55 ISI_HSYNC_PA31 K3 VDDIOP0 GPIO PA31 I/O — — TWCK0 O UTXD1 O ISI_HSYNC I PIO, I, PU, ST
60 MCI1_CDA_PB19 T6 VDDIOP1 GMAC PB19 I/O — — MCI1_CDA I/O GTX4 O — — PIO, I, PU, ST
61 MCI1_DA0_PB20 N8 VDDIOP1 GMAC PB20 I/O — — MCI1_DA0 I/O GTX5 O — — PIO, I, PU, ST
62 MCI1_DA1_PB21 U4 VDDIOP1 GMAC PB21 I/O — — MCI1_DA1 I/O GTX6 O — — PIO, I, PU, ST
63 MCI1_DA2_PB22 M7 VDDIOP1 GMAC PB22 I/O — — MCI1_DA2 I/O GTX7 O — — PIO, I, PU, ST
64 MCI1_DA3_PB23 U5 VDDIOP1 GMAC PB23 I/O — — MCI1_DA3 I/O GRX4 I — — PIO, I, PU, ST
65 MCI1_CK_PB24 M8 VDDIOP1 GMAC PB24 I/O — — MCI1_CK I/O GRX5 I — — PIO, I, PU, ST
71 CTS1_PB26 N9 VDDIOP1 GMAC PB26 I/O — — CTS1 I GRX7 I — — PIO, I, PU, ST
74 RTS1_PB27 V4 VDDIOP1 GPIO PB27 I/O — — RTS1 O G125CKO O — — PIO, I, PU, ST
72 RXD1_PB28 M9 VDDIOP1 GPIO PB28 I/O — — RXD1 I — — — — PIO, I, PU, ST
73 TXD1_PB29 P8 VDDIOP1 GPIO PB29 I/O — — TXD1 O — — — — PIO, I, PU, ST
33 DRXD_PB30 M10 VDDIOP0 GPIO PB30 I/O — — DRXD I — — — — PIO, I, PU, ST
32 DTXD_PB31 R9 VDDIOP0 GPIO PB31 I/O — — DTXD O — — — — PIO, I, PU, ST
43 TWD1_PC26 H9 VDDIOP0 GPIO PC26 I/O — — SPI1_NPCS1 O TWD1 I/O ISI_D11 I PIO, I, PU, ST
44 TWCK1_PC27 D4 VDDIOP0 GPIO PC27 I/O — — SPI1_NPCS2 O TWCK1 I/O ISI_D10 I PIO, I, PU, ST
46 ISI_PCK_PC30 D3 VDDIOP0 GPIO PC30 I/O — — UTXD0 O — — ISI_PCK I PIO, I, PU, ST
45 FIQ_PC31 E4 VDDIOP0 GPIO PC31 I/O — — FIQ I PWMFI1 I — — PIO, I, PU, ST
68 SPI0_MISO_PD10 K9 VDDIOP1 GPIO PD10 I/O — — SPI0_MISO I/O — — — — PIO, I, PU, ST
69 SPI0_MOSI_PD11 M5 VDDIOP1 GPIO PD11 I/O — — SPI0_MOSI I/O — — — — PIO, I, PU, ST
67 SPI0_SPCK_PD12 K10 VDDIOP1 GPIO_CLK PD12 I/O — — SPI0_SPCK I/O — — — — PIO, I, PU, ST
70 SPI0_NPCS0_PD13 N4 VDDIOP1 GPIO PD13 I/O — — SPI0_NPCS0 I/O — — — — PIO, I, PU, ST
57 PD18_MCI1_CD M6 VDDIOP1 GPIO PD18 I/O — — TXD0 O — — — — PIO, I, PU, ST
37 PD20_MCI1_PWC N2 VDDANA GPIO_ANA PD20 I/O — — AD0 I — — — — PIO, I, PU, ST
36 PD21_USBA_OVCUR M3 VDDANA GPIO_ANA PD21 I/O — — AD1 I — — — — PIO, I, PU, ST
38 PD25_USBA_EN5V N1 VDDANA GPIO_ANA PD25 I/O — — AD5 I — — — — PIO, I, PU, ST
39 PD29_USBA_VSENSOR K2 VDDANA GPIO_ANA PD29 I/O — — AD9 I — — — — PIO, I, PU, ST
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Table 2. AAAL115JS-C1 module Pinout for LFLGA-97 Package (continued)
*Page-6. JJA5D3 module Pin number is total 27 pin.
Jorjin Atmel
Power Rail I/O Type
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State
LFLGA-97-Pin LFBGA-324-ball
Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir
Signal, Dir, PU,
PD, HiZ, ST Pin Pin Name Ball
41 PCK1_PD31 J2 VDDANA GPIO_ANA PD31 I/O — — AD11 I PCK1 O — — PIO, I, PU, ST
24 PE23_PWR_ENA M13 VDDIOM EBI PE23 I/O — — A23 O CTS2 I — — A,I, PD, ST
18 PE24_ENG_RST M16 VDDIOM EBI PE24 I/O — — A24 O RTS2 O — — A,I, PD, ST
9 PE25_AIM_ON N12 VDDIOM EBI PE25 I/O — — A25 O RXD2 I — — A,I, PD, ST
19 PE26_ILL_ON M14 VDDIOM EBI PE26 I/O — — NCS0 O TXD2 O — — PIO,I, PU, ST
20 PE29_Buzzer L15 VDDIOM EBI PE29 I/O — — NWR1/NBS1 O TCLK2 I — — PIO,I, PU, ST
21 IRQ_PE31 L16 VDDIOM EBI PE31 I/O — — IRQ I PWML1 O — — PIO,I, PU, ST
13 TST U15 VDDBU SYSC TST I — — — — — — — — I, PD,
79 BMS U9 VDDIOP0 SYSC BMS I — — — — — — — — I
84 XIN U8 VDDIOP0 CLOCK XIN I — — — — — — — — I
83 XOUT V8 VDDIOP0 CLOCK XOUT O — — — — — — — — O
16 XIN32 U16 VDDBU CLOCK XIN32 I — — — — — — — — I
17 XOUT32 V16 VDDBU CLOCK XOUT32 O — — — — — — — — O
15 SHDN T12 VDDBU SYSC SHDN O — — — — — — — — O
12 WKUP T10 VDDBU SYSC WKUP I — — — — — — — — I, ST
82 NRST V9 VDDIOP0 RSTJTAG NRST I/O — — — — — — — — I, PU, ST
81 NTRST P11 VDDIOP0 RSTJTAG NTRST I — — — — — — — — I, PU, ST
78 TDI R8 VDDIOP0 RSTJTAG TDI I — — — — — — — — I, ST
76 TDO M11 VDDIOP0 RSTJTAG TDO O — — — — — — — — O
77 TMS N10 VDDIOP0 RSTJTAG TMS I SWDIO I/O — — — — — — I, ST
80 TCK P9 VDDIOP0 RSTJTAG TCK I SWCLK I — — — — — — I, ST
14 JTAGSEL T9 VDDBU SYSC JTAGSEL I — — — — — — — — I, PD
10 NCS3 L12 VDDIOM EBI NCS3/NANDCS O — — — — — — — — O, PU
31 DDR_CALN C12 VDDIODDR DDR_IO DDR_CALN I — — — — — — — — O
30 DDR_CALP E13 VDDIODDR DDR_IO DDR_CALP I — — — — — — — — O
2 HHSDPA U10 VDDUTMII USBHS HHSDPA I/O DHSDP — — — — — — — O, PD
3 HHSDMA V10 VDDUTMII USBHS HHSDMA I/O DHSDM — — — — — — — O, PD
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Table 2. AAAL115JS-C1 module Pinout for LFLGA-97 Package (end)
*Page-7. JJA5D3 module Pin number is total 35 pin. Notes: (1). VDDIOM_3V3:NAND FLASH DC Supply Voltage and MPU_VDDIOM DC Supply Voltage connected together. (2). VDDIODDR_1V2:LPDDR2_VDD2&VDDQ and MPU_VDDIODDR DC Supply Voltage connected together. (3). LD2_VDD1_1V8:LPDDR2 memory VDD1 DC Supply Voltage. (4). LD2_VREFCA:LPDDR2 VREFCA Reference Voltage and MPU_DDR_VREF Reference Voltage connected together. (5). LD2_VREFDQ:LPDDR2_VREFDQ Reference Voltage. (6). NF_NCE:NAND Flash_CE#(chip enable).
Jorjin Atmel
Power Rail I/O Type
Primary Alternate PIO Peripheral A PIO
Peripheral B
PIO
Peripheral C Reset State
LFLGA-97-Pin LFBGA-324-ball
Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir
Signal, Dir, PU,
PD, HiZ, ST Pin Pin Name Ball
87 VBG R11 VBG VBG VBG I — — — — — — — — I
11 VDDBU V15 VDDBU power supply VDDBU I — — — — — — — — I
6,7,8 VDDCORE_1V2 C5, C7,
D14, T15,
T7, U17, V7
VDDCORE power supply VDDCORE I — — — — — — — — I
22 VDDIOM_3V3(1) P12, T16 VDDIOM power supply VDDIOM I — — — — — — — — I
58 VDDIOP0 G7, V11 VDDIOP0 power supply VDDIOP0 I — — — — — — — — I
66 VDDIOP1 L11, M4 VDDIOP1 power supply VDDIOP1 I — — — — — — — — I
1 VDDUTMIC_1V2 V13 VDDUTMIC Power supply VDDUTMIC I — — — — — — — — I
88 VDDUTMII_3V3 U13 VDDUTMII Power supply VDDUTMII I — — — — — — — — I
85 VDDPLLA_1V2 R10 VDDPLLA Power supply VDDPLLA I — — — — — — — — I
86 VDDOSC_3V3 U11 VDDOSC Power supply VDDOSC I — — — — — — — — I
59 VDDANA_3V3 L6 VDDANA Power supply VDDANA I — — — — — — — — I
35 ADVREF L5 VDDANA Power supply ADVREF I — — — — — — — — I
34 VDDFUSE R3 VDDFUSE Power supply VDDFUSE I — — — — — — — — I
4 GNDUTMI R12 GNDUTMI Ground GNDUTMI I — — — — — — — — I
5,25,42,
75,89~97
GND A16,C9,N13,
T14,T8,V17,
E14,F10,F13,
F15,H14,J11,
T17,E5,J7,
N11,U7,P10,
T11,L4,R3
GNDANA Ground GNDANA I — — — — — — — — I
26,27 VDDIODDR_1V2(2) DNP (No Define) VDDIODDR Power supply — I — — — — — — — — I
23 LD2_VDD1_1V8(3) DNP (No Define) LPDDR2 Power supply — I — — — — — — — — I
29 LD2_VREFCA(4) DNP (No Define)
LPDDR2 Reference
voltage
— I — — — — — — — — I
28 LD2_VREFDQ(5) DNP (No Define) Reference
voltage
— I — — — — — — — — I
40 NF_NCE(6) DNP (No Define) VDDIOM NAND Flash NF_NCE I — — — — — — — — I, PU
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2.3. Input/ Output Description
(1). Pin/Ball:Pin/Ball number(s) on the bottom side associated with each signal(s) on the bottom. (2). Pin Name:Names of signals multiplexed on each Pin/ball (3). Power Rail:The voltage supply that powers the terminal’s I/O buffers. (4). Signal:The voltage supply that powers the terminal’s I/O buffers. (5). Dir:The Signal direction is I(Input)、O(Output)、I/O(Bidirectional). (6). Power Rail:The voltage supply that powers the terminal’s I/O buffers. (7). PU/PD:Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can
be enabled or disabled via software.. (8). I/O TYPE: Table 3. SAMA5D3 I/O Type Description
I/O Type Voltage Range AnalogPull-up Pull-down Schmitt
Trigger(2)Type(1) Typ Value (Ω) Type Typ Value (Ω)
GPIO 1.65–3.6V — Switchable -1 Switchable -1 SwitchableGPIO_CLK 1.65–3.6V — Switchable -1 Switchable -1 SwitchableGPIO_ANA 3.0–3.6V I Switchable -1 — — Switchable
EBI 1.65–1.95V, 3.0–3.6V — Switchable 100K Switchable 100K —
RSTJTAG 1.65–3.6V — Reset State 100K Reset State 100K Reset State
SYSC 1.65–3.6V — — — Reset State 15K Reset State
USBHS 3.0–3.6V I/O — — — — — CLOCK 1.65–3.6V I/O — — — — —
Notes:(1). Refer to Section 5 “DC Characteristics”. (2). When “Reset State” is indicated, the configuration is defined by the “Reset State” column of the Pin description
table (see Table 4-1 on page 11 and Table 4-2 on page 20). Table 4. SAMA5D3 I/O Type Assignment and Frequency
I/O Type
Max I/O Frequency
(MHz) Load (pF) Fan-out Drive Control Signal Name
GPIO 33 40 — High/Medium/Low All PIO lines except the lines indicated further on in this table
MCI_CLK 52 20 — High/Medium/Low MCI1CK GPIO_CLK 66 20 — High/Medium/Low SPI0CK GPIO_ANA 25 20 16 mA,
40 mA (peak)Fixed to Medium ADx
EBI 66 50 — High/Medium/Low 1.8V/3.3V
All EBI signals
DDR_IO 166 20 — High/Medium/Low All DDR signals RST 3 10 — Fixed to Low NRST, NTRST, BMS JTAG 10 10 — Fixed to Medium TCK, TDI, TMS, TDO SYSC 0.25 10 — No WKUP, SHDN, JTAGSEL, TST, SHDNVBG 0.25 10 — No VBG
USBHS 480 20 — No HHSDPA/DHSDP, HHSDMA/DHSDM
CLOCK 50 50 — No XIN, XOUT, XIN32, XOUT32
9
3. Power Considerations 3.1. Power Supplies
Table 5. AAAL115JS-C1 module Power Supplies
Name Voltage Range, Nominal Associated
Ground Items Powered
VDDCORE_1V2 1.1–1.32V, 1.2V GND Core, including the processor, the embedded memories and the peripherals
VDDIODDR_1V2 1.14–1.30, 1.2V GND LPDDR2_VDD2&VDDQ and MPU_LPDDR2 Interface I/O lines
VDDIOM_3V3 3.0–3.6V, 3.3V GND NAND Flash and HSMC Interface I/O lines
VDDIOP0 1.65–3.6V GND Peripheral IOP0 I/O lines
VDDIOP1 1.65–3.6V GND Peripheral IOP1 I/O lines
VDDBU 1.65–3.6V GND Slow Clock Oscillator, the internal 32 kHz RC Oscillator and a part of the System Controller
VDDUTMIC_1V2 1.1–1.32V, 1.2V GNDUTMI USB device and host UTMI+ core
VDDUTMII_3V3 3.0–3.6V, 3.3V GNDUTMI USB device and host UTMI+ interface
VDDPLLA_1V2 1.1–1.32V, 1.2V GND PLLA cell
VDDOSC_3V3 1.65–3.6V GND Main Oscillator Cell and PLL UTMI. If PLL UTMI or USB is used, the range is to be 3.0–3.6V.
VDDANA_3v3 2.4–3.6V, 3.3V GND Analog-to-Digital Converter
VDDFUSE 2.25–2.75V, 2.5V GND Fuse box for programming It can be tied to ground with a 100 Ω resistor for fuse reading only. It
must be powered for Fuse programming and to switch in Secure Mode.
10
3.2. Power-Up Considerations
From a power-up supply sequencing perspective, Atmel SAMA5D3x power supply inputs are
categorized into two groups:
Group 1, the core group, containing VDDCORE, VDDUTMIC and VDDPLLA
Group 2, the periphery group, containing all other power supply inputs.
Figure-1 gives the recommended power-up sequence with the following precisions:
VDDBU, when supplied from a battery is an always-on supply input and is therefore not part
of the power supply sequencing. When no backup battery is present in the application,
VDDBU is part of Group 2.
VDDFUSE is the only power supply that may be left un-powered during operation. This is
possible if and only if the application does not access the fuse box in write mode. VDDFUSE
must be applied when programming the fuse box.
VDDIODDR may be nominally supplied at 1.2V when the SAMA5D3x is equipped with an
LPDDR2 memory. In this case, VDDIODDR can be considered as part of Group 1.
Figure 2. Recommended Power-Up Sequence
Table 6. Power-Up Timing Specification
Symbol Parameter Conditions Min Max Unit
t1 Group 2 to Group 1 delay Delay from the last Group 2 established(1) supply to the first Group 1 supply turn-on
1 – ms
t2 Group 1 delay(2) Delay from the first group 1 established supply to the last Group 1 established supply
– 1
tRSTPU Reset Delay at Power-Up From the last Group 1 established supply to NRST high 1 –
Notes: 1. In the whole table, an “established” supply refers to a power supply established to 90% of its final value. 2. Also applies to VDDIODDR when considered as part of Group 1.
11
3.3. Power-Down Considerations
Figure 3 gives the SAMA5D3x power down sequence that starts by asserting the NRST line to 0. Once NRST is asserted, the supply inputs can be immediately shut down without any specific timing or order. VDDBU may not be shutdown if the application uses a backup battery on this supply input. Figure 3. Recommended Power-Up Sequence
Table 7. Power-Up Timing Specification
Symbol Parameter Conditions Min Max Unit
tRSTPD Reset Delay at Power-Down From NRST low to the first supply turn-off 0 – ms
3.4. AAAL115JS-C1 module for SIP Technology
The AAAL115JS-C1 module is use MCP (Multi-chip Package) for SIP (System in Package) technologys, the module contains NAND Flash-1Gb and LPDDR2-1Gb memory. AAAL115JS-C1 module as blew. • SAMA5D3 processor + 1Gb(128Mbx8) NAND Flash + 1Gb(32Mbx32) mobile LPDDR2
12
4. Block Diagram and Interfaces 4.1. Block Diagram
Figure 4. AAAL115JS-C1 Block Diagram
13
4.2. ISI (Image Sensor Interface)
The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats.
Several input formats such as preprocessed RGB or YCbCr are supported through the data bus interface. The ISI supports two modes of synchronization: Hardware with ISI_VSYNC and ISI_HSYNC signals International Telecommunication Union Recommendation ITU-R BT.656-4 Start-of-Active-Video (SAV)
and End-of-Active-Video (EAV) synchronization sequence Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC not used). The polarity of the synchronization pulse is programmable to comply with the sensor signals. Table 8. ISI I/O Lines
Signal Direction Description Direction I/O Line Peripheral
ISI_VSYNC Input Vertical Synchronization Input PA30 C
ISI_HSYNC Input Horizontal Synchronization Input PC30 C
ISI_DATA0 Input Sensor Pixel Data 0 Input PA16 C
ISI_DATA1 Input Sensor Pixel Data 1 Input PA17 C
ISI_DATA2 Input Sensor Pixel Data 2 Input PA18 C
ISI_DATA3 Input Sensor Pixel Data 3 Input PA19 C
ISI_DATA4 Input Sensor Pixel Data 4 Input PA20 C
ISI_DATA5 Input Sensor Pixel Data 5 Input PA21 C
ISI_DATA6 Input Sensor Pixel Data 6 Input PA22 C
ISI_DATA7 Input Sensor Pixel Data 7 Input PA23 C
ISI_PCK Input Pixel Clock Provided by the Image Sensor
Input PC30 C
SI_MCK Output
Master Clock Provided to the Image Sensor
Output
14
4.3. USB Device High Speed Port (UDPHS) 4.3.1. UDPHS Embedded Characteristics
1 Device High Speed 1 UTMI transceiver shared between Host and Device USB v2.0 High Speed Compliant, 480 Mbit/s 16 Endpoints up to 1024 bytes Embedded Dual-port RAM for Endpoints Suspend/Resume Logic (Command of UTMI) Up to Three Memory Banks for Endpoints (Not for Control Endpoint) 8 Kbytes of DPRAM
4.3.2. USB Device Port Typical Connection
Figure 5. USB Device Port Board schematic
Note: The values shown on the 22 kΩ and 15 kΩresistors are only valid with 3V3 supplied PIOs.
4.3.3. UDPHS Power Management
The UDPHS is not continuously clocked. For using the UDPHS, the programmer must first enable the UDPHS Clock in the Power Management
Controller Peripheral Clock Enable Register (PMC_PCER). Then enable the PLL in the PMC UTMI Clock Configuration Register (CKGR_UCKR).
Finally, enable BIAS in CKGR_UCKR. However, if the application does not require UDPHS operations, the UDPHS clock can be stopped when not needed and restarted later.
4.3.4. UDPHS Interrupt Sources
The UDPHS interrupt line is connected on one of the internal sources of the interrupt controller. Using the UDPHS interrupt requires the interrupt controller to be programmed first.
Table 9. UDPHS Peripheral ID
Instance ID
UDPHS 33
15
4.4. USB Host High Speed Port (UHPHS) 4.4.1. UHPHS Embedded Characteristics
1 Device High Speed Compliant with Enhanced HCI Rev 1.0 Specification
– Compliant with USB V2.0 High-speed – Supports High-speed 480 Mbps
Compliant with OpenHCI Rev 1.0 Specification – Compliant with USB V2.0 Full-speed and Low-speed Specification – Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices
Root Hub Integrated with 3 Downstream USB HS Ports Embedded USB Transceivers Supports Power Management 3 Hosts (A, B, and C) High Speed (EHCI), Port A shared with UDPHS
Note:Hosts Port-B and Port-B is non-use.
4.4.2. USB Host Port Typical Connection
Figure 6. USB Host Port Board schematic
4.5. USB Host Port-A Shared with UDPHS Functional Description 4.5.1. UTMI Transceivers Sharing
The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second UTMI transceiver. The selection between Host Port A and USB device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL register.
Figure 7. USB Selection
16
4.6. High Speed Multimedia Card Interface (HSMCI) 4.6.1. HSMCI Application Block Diagram
Figure 8. HSMCI Application Block Diagram
Table 10. HSMCI1 I/O Lines for 4-bit Configuration
Instance I/O Line Pin Name Pin Description Type(1) Comments Peripheral
HSMCI1 PB19 MCI1_CDA command/response I/O/PP/OD CMD of an MMC or SD Card/SDIO
A
HSMCI1 PB24 MCI1_CK MCI1_CK I/O CLK of an MMC or SD Card/SDIO
A
HSMCI1 PB20 MCI1_DA0 MCI1_DA0 I/O/PP DAT0 of an MMC or DAT0 of an SD Card/SDIO
A
HSMCI1 PB21 MCI1_DA1 MCI1_DA1 I/O/PP DAT1 of an MMC or DAT1 of an SD Card/SDIO
A
HSMCI1 PB22 MCI1_DA2 MCI1_DA2 I/O/PP DAT2 of an MMC or DAT2 of an SD Card/SDIO
A
HSMCI1 PB23 MCI1_DA3 MCI1_DA3 I/O/PP DAT3 of an MMC or DAT3 of an SD Card/SDIO
A
Note:I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
4.6.2. HSMCI Power Management The HSMCI is clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the HSMCI clock.
4.6.3. HSMCI Interrupt Sources The HSMCI has an interrupt line connected to the interrupt controller. Handling the HSMCI interrupt requires programming the interrupt controller before configuring the HSMCI.
Table 11. HSMCI Peripheral ID
Instance ID
HSMCI1 22
17
4.7. Serial Peripheral Interface (SPI) 4.7.1. SPI Application Block Diagram
Figure 9. SPI Application Block Diagram
Table 12. SPI0 I/O Lines
Instance Signal I/O Line Peripheral
SPI0 SPI0_MISO PD10 A
SPI0 SPI0_MOSI PD11 A
SPI0 SPI0_NPCS0 PD13 A
4.7.2. SPI Power Management
The SPI can be clocked through the Power Management Controller (PMC), thus the programmer must First configure the PMC to enable the SPI clock.
4.7.3. SPI Interrupt Sources
The SPI interface has an interrupt line connected to the interrupt controller. Handling the SPI interrupt requires programming the interrupt controller before configuring the SPI Table 13. Peripheral IDs
Instance ID
SPI0 24
BO1NA1411B module SPI1 and SPI2 is non-use
18
4.8. Two-wire Interface (TWI )
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. Table 14 lists the compatibility level of the Atmel Two-wire Interface in Master mode and a full I2C Compatible device.
Table 14. Atmel TWI Compatibility with I2C Standard
I2C Standard Atmel TWI Standard Mode Speed (100 kHz) Supported Fast Mode Speed (400 kHz) Supported 7- or 10-bit Slave Addressing Supported START byte(1) Not Supported Repeated Start (Sr) Condition Supported ACK and NACK Management Supported Slope Control and Input Filtering (Fast mode) Not Supported Clock Stretching/Synchronization Supported Multi Master Capability Supported
Note: 1. START + b000000001 + Ack + Sr
4.8.1. TWI I/O Lines Description Table 15. TWI I/O Lines Description
Instance I/O Line Pin Name Description Type Peripheral
TWI1 PC27 TWCK1 Two-wire Serial Data (SDA) Input/Output B
TWI1 PC26 TWD1 Two-wire Serial Clock (SCL) Input/Output B
4.8.2. TWI Power Management The TWI may be clocked through the Power Management Controller (PMC), thus the user must first configure the PMC to enable the TWI clock
4.8.3. TWI Interrupt Sources Table 16. Peripheral IDs
Instance ID
TWI0 18
TWI1 19
19
4.9. Debug Unit (DBGU)
The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication.
Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via the In-circuit Emulator. This permits protection of the code, stored in
ROM.
4.9.1. DBGU Embedded Characteristics
• System Peripheral to Facilitate Debug of Atmel® ARM®-based Systems • Composed of Four Functions - Two-pin UART - Debug Communication Channel (DCC) Support - Chip ID Registers - ICE Access Prevention
4.9.2. DBGU I/O Lines Description
Table 17. Debug Unit Pin Description
Instance I/O Line Pin Name Description Type Peripheral
DBGU PB30 DRXD Debug Receive Data Input A DBGU PB31 DTXD Debug Transmit Data Output A
4.9.3. DBGU Power Management
Depending on product integration, the Debug Unit clock may be controllable through the Power Managerment Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.
4.10. Universal Synchronous Asynchronous Receiver Transceiver (USART)
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link.
The USART features three test modes: Remote loopback, Local loopback and Automatic echo. The hardware handshaking feature enables an out-of-band flow control by automatic management
of the pins RTS and CTS. The USART supports the connection to the DMA Controller, which enables data transfers to the
transmitter and from the receiver. The DMAC provides chained buffer management without any intervention of the processor.
4.10.1. USART I/O Lines Description
Table 18. USART I/O Lines Description
Instance I/O Line Pin Name Description Type Peripheral
USART1
PB29 TXD1 Transmit Serial Data I/O A PB28 RXD1 Receive Serial Data Input A PB26 CTS1 Clear to Send Input A PB27 RTS1 Request to Send Output A
4.10.2. USART Power Management
The USART is not continuously clocked. The programmer must first enable the USART clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off.
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5. Electrical Characteristic 5.1. Absolute Maximum Rating
Table 19. Absolute Maximum Rating
Parameter Test Conditions Min Typ Max Unit
Junction Temperature 125
Storage Temperature -60 150
Voltage on Input Pins with Respect to
Ground
-0.3 VDDIO+0.3 4 V
VDDCORE, VDDPLLA, VDDUTMIC Maximum Operating Voltage 1.5 V
VDDIODDR 2.0 V
VDDIOM, VDDIOPx, VDDUTMII,
VDDOSC, VDDANA and VDDBU 4.0 V
VDDFUSE 3.3 V
Total DC Output Current on all I/O lines 350 mA Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
21
5.2. DC Characteristics
Table 20. DC Characteristics
Symbol Parameter Conditions Min Typ Max Unit
TA Operating Temperature — -40
105 °C
VDDCORE_1V2 Core DC Supply Voltage — 1.08 1.2 1.32 V
VDDUTMIC_1V2 UDPHS and UHPHS UTMI+ Core DC Supply Voltage
— 1.08 1.2 1.32 V
VDDUTMII_3V3 UDPHS and UHPHS UTMI+ Interface DC Supply Voltage
— 3 3.3 3.6 V
VDDBU Backup DC Supply Voltage — 1.65 — 3.6 V
VDDPLLA_1V2 PLLA DC Supply Voltage — 1.08 1.2 1.32 V
VDDOSC_3V3 Oscillator and PLL UTMI DC Supply Voltage
If PLL UTMI or USB is used, the VDDIO range is to be 3.0V to 3.6V
1.65 — 3.6 V
VDDIOM_3V3 EBI I/Os DC Supply Voltage — 3.0 3.3 3.6 V
VDDIODDR_1V2 SDRAM I/Os DC Supply Voltage and LPDDR2
LP-DDR2 usage 1.14 1.2 1.3 V
VDDIOP0 Peripheral I/Os DC Supply Voltage — 1.65 — 3.6 V
VDDIOP1 Peripheral I/Os DC Supply Voltage — 1.65 — 3.6 V
VDDFUSE Fuse Box DC Supply Voltage For FUSE programming only 2.25 2.5 2.75 V
IVDDFUSE VDDFUSE Current During FUSE programming — — 40 mA
VDDANA_3V3 Analog DC Supply Voltage — 3 3.3 3.6 V
ADVREF ADC Reference Voltage 2.4V ﹣ 3.6V V
VBG Bias Voltage Reference for USB 0.9V ﹣ 1.1V V
LD2_VREFCA LPDDR2 VREFCA and VREF Voltage 0.588V ﹣ 0.612V V
LD2_VREFDQ LPDDR2 VREFDQ Voltage 0.588V ﹣ 0.612V V
VIL Input Low-level Voltage VDDIO in 3.3V range -0.3 — 0.8 V
VDDIO in 1.8V range -0.3 — 0.3 × VDDIO
VIH Input High-level Voltage VDDIO in 3.3V range 2 — VDDIO + 0.3 V
VDDIO in 1.8V range 0.7 × VDDIO — VDDIO + 0.3
Vhys Schmitt trigger Hysteresis All PIO lines VDDIOx in 3.3V range 0.34 — — V
All PIO lines VDDIOx in 1.8V range 0.21 — —
VOL Output Low-level Voltage IO Max — — 0.4 V
VOH Output High-level Voltage IO Max VDDIO - 0.4 — — V
RPULL Pull-up/Pull-down Resistance All PIO lines VDDIOx in 1.8V range 100 160 310
kΩ All PIO lines NTRST and NRST VDDIOx in 3.3V range
45 70 130
22
5.3. 12 MHz RC Oscillator Characteristics
Table 21. 12 MHz RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit F0nom Nominal Frequency — 11.4 12 12.6 MHz Duty Duty Cycle — 45 50 55 % IDD_ON Power Consumption Oscillation — — 220 — µA tSTART Startup time — — — 10 µS
IDD(standby) Standby consumption — — — 22 µA NOTE:Main Oscillator Characteristics please refer SAMA5D3 datasheet.
5.4. 32 kHz RC Oscillator Characteristics
Table 22. 32 kHz RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit 1/(tCPRCz) Crystal Oscillator Frequency — 30.4 32 33.6 kHz
— Duty Cycle — 45 — 55 % tSTART Startup Time — — 290 500 µS IDD_ON Power Consumption Oscillation After startup time — 1.1 2.1 µA
IDD(standby) Standby consumption — — — 0.2 µA NOTE:32 kHz Oscillator Characteristics please refer SAMA5D3 datasheet.
23
5.5. Power Consumption
• Typical power consumption of PLLs, slow clock and main oscillator • Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup • Power consumption by peripheral: calculated as the difference in current measurement after having
enabled then disabled the corresponding clock • Software used for power consumption measurements: DHRYSTONE • Instruction and data caches are enabled. The Memory Management Unit (MMU) is enabled.
5.5.1. Static Current
Static current, or leakage current, is measured when the system has no activity at all. Static current is very sensitive to process and operating temperatures and the value may fluctuate considerably between two
different devices, and vary according to the operating temperature. Figures are given in Table 11. This variation explains the differences between two measurements done on different devices or at d
different temperatures.
5.5.2. Active Mode
Active Mode is the normal running mode with the core clock running from a PLL. The power management controller can be used to adapt the frequency and to disable the peripheral clocks. Note: Active power consumption may vary by ±5% depending on the compiler used and the process.
5.5.3. Low-power Modes
5.5.3.1. Backup Mode
Backup mode achieves the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time. The Zero-power Power-on Reset, RTC, Backup registers and 32 kHz oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The core supply is off. The system can be awakened from this mode through the WKUP0 pin or an RTC wake-up event. Backup mode is entered with the help of the Shutdown Controller that asserts the SHDN output pin. The
SHDN pin is to be connected to the enable pin of the VDDCORE regulator. Exit from Backup mode happens if one of the following enable wake-up events occurs:
WKUP0 pin (level transition, configurable debouncing) RTC alarm
The system will restart as for a reset event.
5.5.3.2. Idle Mode
Idle mode optimizes power consumption of the device versus response time. In Idle mode, only the core clock is stopped. The peripheral clocks, including the DDR Controller clock, can be enabled. The current consumption in this mode is application dependent. Idle mode is entered via the Wait for Interrupt (WFI) instruction and PCK disabling. The processor can be awakened from an interrupt. The system will resume where it was before entering in
WFI mode. Note: The power consumption includes the static current.
24
5.5.3.3. Ultra Low-power Mode
Ultra low-power mode reduces the power consumption of the device to a minimum without disconnecting VDDCORE power supply. It is a combination of very low frequency operations and Idle mode. Ultra low-power mode is entered via the following steps: 1. Set the DDR to Self Refresh mode. 2. Reduce the system clock (PCK and MCK) to a minimum with the help of the PMC: - PCK and MCK configuration is to be defined regarding the expected power consumption and wake-up time. Please refer to Table 23 for details - PLLs are disabled. CKGR_PLLAR (if applicable, CKGR_PLLBR) is set to 0x3F00. CKGR_UCKR is set to 0. - Main oscillator is disabled. MOSCXTEN is set to 0 in CKGR_MOR. - Eventually 12 MHz RC oscillator is disabled. MOSCRCEN is set to 0 in CKGR_MOR. 3. Enter Wait for Interrupt (WFI) mode and disable the PCK clock. The processor can be awakened from an interrupt. Once revived, the system must reprogram the system clocks (OSC, PLL, PCK, MCK, DDRCK) to
recover the previous state. Data is maintained in the external memory.
5.5.3.4. Low-power Mode Summary Table
Backup, Idle and Ultra low-power modes are the main low-power modes. Each part can be set to on or off separately, and wake-up sources can be individually configured. Table 23 shows a summary of the configurations of the low-power modes. Table 23. Low-power Mode Configuration Summary
Mode
32K RC, 12 MHz RC, 32 kHz Osc.,
RTC, GPBR, POR (Backup Region)
VDDCORE External Regulator
Core Memory Peripherals
Mode Entry Potential Wake-up
Sources Core at Wake-up
PIO State while inLow-power Mode
PIO State at Wake-up
Consumption(2) Wake-up Time(1)
Backup ON OFF OFF
(not powered) SHDWC
WKUP0 pin RTC alarm
Reset Reset Inputs with
pull-ups 1.2 μA typ(3) Start-up time
Idle ON ON Powered
(not clocked) WFI Any interrupt
Clocked back at full speed
Previous state saved Unchanged See Table 55-7 10 mA
for each PLL(4) 285 ns @ 132 MHz
Ultra Low-power ON ON Powered
(not clocked)
DDR in Self-refresh PMC
WFI Any interrupt
Clocked back at previous one
Previous state saved Unchanged See Table 55-8 See Table 55-8
25
6. Mechanicals 6.1. AAAL115JS-C1 module Size for Bottom View
Figure 10. AAAL115JS-C1 module Size for Bottom View
Unit:mm Total:97 Pins
Bottom View
26
Figure 11. AAAL115JS-C1 module Pin define for Top View
Top View
27
6.2. AAAL115JS-C1 module Signal Description List
Table 24. AAAL115JS-C1 Module Signal Description List
Pin No Function Pin Name Description Dir
84 Clocks, Oscillators and PLLs XIN Main Oscillator Input I 83 XOUT Main Oscillator Output O 16 XIN32 Slow Clock Oscillator Input I 17 XOUT32 Slow Clock Oscillator Output O 41 PCK1_PD31 Programmable Clock Output O
15 Shutdown, Wake-up Logic SHDN Shut-Down Control O 12 WKUP Wake-Up Input I
80 ICE and JTAG TCK Test Clock/Serial Wire Clock I 78 TDI Test Data In I 76 TDO Test Data Out O 77 TMS Test Mode Select/Serial Wire Input/Output. I/O 14 JTAGSEL JTAG Selection I
82 Reset/Test NRST Microcontroller Reset I/O 81 NTRST Test Reset Signal I 13 TST Test Mode Select I 79 BMS Test Mode Select I
33 Debug Unit (DBGU) DRXD_PB30 Debug Receive Data I 32 DTXD_PB31 Debug Transmit Data O 21 Advanced Interrupt Controller – AIC IRQ_PE31 External Interrupt for N5600 Push-button Input. I 45 FIQ_PC31 Fast Interrupt Input I
10 Static Memory Controller - HSMC NCS3 Static Memory Controller Chip Select Lines O
40 NAND Flash Control Pins NF_NCE Internal Nand Flash CHIP ENABLE The CE# input is the device selection control. When the device is in the Busy state, CE# high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE# control during read operation, refer to ’Page read’ section of Device operation.
I
30 LPDDR2 Controller DDR_CALP Positive Calibration Reference I 31 DDR_CALN Negative Calibration Reference I
2 USB Host High Speed Port-A (UHPHS) or USB Device High Speed Port(UDPHS)
HHSDPA/DHSDP USB Host Port A High Speed Data + / USB Device High Speed Data + Analog 3 HHSDMA/DHSDM USB Host Port A High Speed Data - / USB Device High Speed Data - Analog
71 Universal Synchronous Asynchronous Receiver Transmitter - USART1
CTS1_PB26 USART1 Clear To Send I 74 RTS1_PB27 USART1 Request To Send O 72 RXD1_PB28 USART1 Receive Data I 73 TXD1_PB29 USART1 Transmit Data O
44 Two-Wire Interface - TW2 (I2C) TWCK1_PC27 Two-wire Serial Clock I/O 43 TWD1_PC26 Two-wire Serial Data I/O
68 Serial Peripheral Interface – SPI0 SPI0 MISO PD10 SPI0 Master In Slave Out I/O
69 SPI0 MOSI PD11 SPI0 Master Out Slave In I/O
67 SPI0 SPCK PD12 SPI0 Serial Clock I/O
70 SPI0 NPCS0 PD13 SPI0 Peripheral Chip Select 0 I/O
51 ISI interface ISI_D0_PA16 Image Sensor Data D0 I
47 ISI_D1_PA17 Image Sensor Data D1 I
44 ISI_D2_PA18 Image Sensor Data D2 I
48 ISI_D3_PA19 Image Sensor Data D3 I
53 ISI_D4_PA20 Image Sensor Data D4 I
49 ISI_D5_PA21 Image Sensor Data D5 I
52 ISI_D6_PA22 Image Sensor Data D6 I
50 ISI_D7_PA23 Image Sensor Data D7 I
56 ISI_HSYNC_PA31 Image Sensor Horizontal Synchro I
55 ISI_VSYNC_PA30 Image Sensor Vertical Synchro I
46 ISI_PCK_PC30 Image Sensor Data clock I
60 High Speed Multimedia Card Interface - HSMCI1 Micro SD (MCI1)
MCI1_CDA_PB19 Multimedia 1 Card Command I/O
61 MCI1_DA0_PB20 Multimedia 1 Card Data 0 I/O
62 MCI1_DA1_PB21 Multimedia 1 Card Data 1 I/O
63 MCI1_DA2_PB22 Multimedia 1 Card Data 2 I/O
64 MCI1_DA3_PB23 Multimedia 1 Card Data 3 I/O
65 MCI1_CK_PB24 Multimedia Card 1 Clock I/O
24 Other GPIO PE23_PWR_ENA N5600 module Power Enable O
18 PE24_ENG_RST N5600 module Reset Pin O 9 PE25_AIM_ON N5600 module Aiming beam control O 19 PE26_ILL_ON N5600 barcode illumination control O 20 PE29_Buzzer N5600 module buzzer control O
57 PD18_MCI1_CD Multimedia 1 Card Command O
24 PD20_MCI1 PWR MCI1 PWR control O
36 PD21_USBA_OVCUR USB VBUS Over current detect I
38 PD25_USBA_EN5V USB VBUS Power control O
39 PD29_USBA_VSENSOR USB VBUS detect I
28
Table 24. AAAL115JS-C1 module Signal Description List (continued)
Pin No Symbol Power Signal (Parameter) DC Characteristics
Powers Description TypeMin Type Max
6,7,8 VDDCORE_1V2 Core DC Supply Voltage 1.08V 1.2V 1.32V The core, including the processor, the embedded memories and the peripherals
P
1 VDDUTMIC_1V2 UDPHS and UHPHS UTMI+ Core DC Supply Voltage
1.08V 1.2V 1.32V The USB device and host UTMI+ core P
88 VDDUTMII_3V3 UDPHS and UHPHS UTMI+ Interface DC Supply Voltage
3.0V 3.3V 3.6V The USB device and host UTMI+ interface P
11 VDDBU Backup DC Supply Voltage 1.65V ﹣ 3.6V The Slow Clock Oscillator, the internal 32 kHz RC Oscillator and a part of the System Controller
P
85 VDDPLLA_1V2 PLLA DC Supply Voltage 1.08V 1.2V 1.32V The PLLA cell P
86 VDDOSC_3V3 Oscillator and PLL UTMI DC Supply Voltage 1.65V ﹣ 3.6V Main Oscillator Cell and PLL UTMI. If PLL UTMI or USB is used, the range is to be 3.0V to 3.6V.
P
22 VDDIOM_3V3 NAND Flash VDD and MPU-VDDIOM EBI I/Os DC Supply Voltage is connected together.
3.0V 3.3V 3.6V NAND and HSMC Interface I/O lines P
26,27 VDDIODDR_1V2 LPDDR2-VDD2&VDDQ and MPU-VDDIODDR DC Supply Voltage
1.14V 1.2V 1.30V LPDDR2_VDD2&VDDQ and CPU SDRAM I/Os DC Supply Voltage Note : LPDDR2 VDD2&VDDQ Pin and VDDIODDR Pin is connected together in the SIP module inside.
P
23 LD2-VDD1_1V8 LPDDR2_VDD1 DC Supply Voltage 1.65V 1.8V 1.95V LPDDR2_VDD1 DC Supply Voltage (for LPDDR2-1Gb module use)
P
58 VDDIOP0 Peripheral I/Os DC Supply Voltage 1.65V ﹣ 3.6V Peripheral I/O lines P
66 VDDIOP1 Peripheral I/Os DC Supply Voltage 1.65V ﹣ 3.6V Peripheral I/O lines P
34 VDDFUSE FUSE Box DC Supply Voltage 2.25V 2.5V 2.75V Fuse box for programming. It can be tied to ground with a 100 Ω resistor for fuse reading only.
P
IVDDFUSE VDDFUSE current ﹣ ﹣ 40mA
59 VDDANA_3V3 Analog DC Supply Voltage 3.0V 3.3V 3.6V Analog-to-Digital Converter P
35 ADVREF ADVREF 2.4V ﹣ 3.6V ADC Reference P
87 VBG VBG 0.9V ﹣ 1.1V Bias Voltage Reference for USB P
29 LD2_VREFCA LPDDR2-VREFCA and MPU-DDR_VREF is connected together.
0.588V ﹣ 0.612V LPDDR2 VREFCA is reference for command/address input buffers Reference Voltage. Note : MPU_VREF and LPDDR2 VREFCA is connected together in the SIP module inside.
P
28 LD2_VREFDQ LPDDR2-VREFDQ Reference Voltage 0.588V ﹣ 0.612V LPDDR2 VREFDQ is reference for DQ input buffers Reference Voltage. P
5,25,42,75, 89~97
GND MPU_GND ﹣ ﹣ ﹣ System ground P
4 GNDUTMI MPU_GNDUTMI ﹣ ﹣ ﹣ UDPHS and UHPHS UTMI+ Core and interface ground P
29
7. Design Guidelines This section provides general design guidelines for the AP module.
7.1. General Rules and Constraints
Place the SD card, ISI parts as a second-level priority. Place components of the same function circuit close together, and keep a clearance from other circuits. Place the decoupling capacitors (0.1 μF or smaller) as close as possible to each IC power pin, and place the
bulk capacitors (1 μF or larger) properly on the PCB to charge the decoupling capacitors. As far as possible, avoid splitting ground planes, and avoid routing signals above the splits in ground planes,
as that is a major source of Electro-Magnetic Interference (EMI).
7.2. PCB Layout Recommendations
The ground slugs in the center of AP module should have good contact on the host PCB integrated ground area, and amount of the ground via on the host should be enough to allow effective heat dissipation. Because the bubbles may accrue during surface mounting process between AP module and host PCB, we
strongly suggested that customers DON’T place vias on AP module pads for good contact.
7.2.1. MMC Power Signals
The power trace on host PCB should consider the rating of each power domain. Customer can refer Table19 to design the minimum trace width on host PCB. The general rule is that the trace of 40mil width is sufficient 1A current.
7.2.2. MMC Signals
When using MMC1 as external SD card interface, trace impedance should be 50ohm. We strongly recommend customers should add 33ohm resisters between SD card connector and AP module, and place 33ohm nearly AP module.
7.2.3. Parallel Display Signals
The AP module provides a 24 bit parallel Display Subsystem (DSS) interface. These high speed trace should not be routed cross analog signals and critical signals, and the clock should protected by ground. The number of vias/layer transitions should be minimized.
7.2.4. USB signals
The USB ports in SAMA5D3 devices are compliant with USB v2.0 High-speed Specification. Layout recommendations are:
The USB DM and DP signals should be routed as differential traces and be perfectly parallel to each other. The reference plane should be continuous If a routing layer must be changed, then the DM and DP signals should be transferred together to the other
layer. The impedance of the differential traces should be 90 ±10% Ohm.
30
Solder Paste and Reflow Profile To minimize signal problems with quality, use the following general routing and placement guidelines for laying out the US • It is important to provide a solder reflow profile that matches the solder paste supplier’s recommendations. Some fluxes need a long dwell time below the temperature of 200°C. LGA product need a enough pre-heat for flux volatilized in order to restrain the void. So how to set your profile with enough preheat time base on supplier’s recommendations is a key point. • JORJIN has found a good profile for SENJU paste of M705-GRN360 K2-VL (SAC 305) in Figure 9 and 10, It has good performance in void prevention.
Figure 12 Reflow Profile (1)
Figure 13 Reflow Profile (2) NOTE: All temperatures refer to bottom side of the module measured in the package bottom surface"
7.3. Reliability Compliance
31
8. BO1NA1411B-E0 EVM Board 8.1. BO1NA1411B-E0 EVM Board Function Block
Figure 14. BO1NA1411B-E0 EVM Board Function Block
32
8.2. BO1NA1411B-E0 EVB Board Specification
Table 25 BO1NA1411B-E0 EVM Board Specification Table
BO1NA1411B-E0 EVM Board Specification
Processor AAAL115JS-C1 module (Include Atmel SAMA5D31 ARM Cortex-A5 processor + Nand Flash 1Gbit + LPDDR2 1Gbit)
Clock Speed Up to 536 MHz PCK, up to 166 MHz MCK
Power Management Unit PMU Chip:ACT8865QI305 ( Active-Semi )
Input Voltage
CN1,DC Jack:5V/1A or CN2, Micro USB Connector:5V/500mA (for USB Device Port application) Note:When CN1 and CN2 connector are plug-in, the power provided by the CN1 connector.
Interface
J4, ISI 34Pin Female Header (2x17/1.27mm/34Pin Female Header) – Supports ISI Interface – Supports BO1NA1411B-S0 Board (Honeywell-N5600 Barcode Scanner Board) Note:The I2C Port (TW1, Two-Wire 1 Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS)
CN2, Micro USB Connector – Supports USB 2.0 High Speed Host or Device Port – USB High Speed Device Port Compliant with the USB V2.0 High Speed device Specification.– USB High Speed Host Port Compliant with USB V2.0 HS(480Mbps)/ FS(12Mbps)/
LS(1.5Mbps) Specification
CN5, Micro USB Connector ( for DBGU Port) – DBGU(Debug Unit, Support two-pin UART) via UART to USB chip. – USB 2.0 Full Speed compatible. – SAM-BA Boot Assistant supports
CN3, D-SUB male 9-Pin connector – Support USART1 with RTS/CTS handshake
CN4, Micro SD Card connector – Support HSMCI1 4 bit SDIO
J3, JTAG 20-Pin Pin Header (2x10/2.54mm/Male 20-Pin Header) – IEEE1149.1 JTAG Boundary-scan on All Digital Pins
Support 32M bit Serial Flash Note:Use SPI0(Serial Peripheral Interface 0) connector Serial Flash
Dimensions BO1NA1411B-E0 ( EVM Board):100 x 100 x 1.6 mm BO1NA1411B-S0 (N5600 Scanner Board):30 x 30 x 1.6 mm
8.3. BO1NA1411B-E0 EVB Board Test Report
Please contact Jorjin’s sales. Please see Page.33-34
`
33
9. Appendix_A:BO1NA1411B-E0 Component Location
(Top View) (Bottom View)
34
10. Appendix_A:BO1NA1411B-E0 Schematics
2. Sensor Interface Connector(J4) add JP25,JP26,JP27 Jump for Power measurement.BO1NA1411B-E0-D03 2016/03/14 1. Power connector to Jump change to "discrete" connector to Jump.
Size
APPROVED By
Date: Sheet
PCB NAMENAME Rev Rev
/
ECN NO. REMARK
CHECKED By DESIGNED By
JorJin Technologies Inc.MODEL NAME SCHEMATIC NAME
NAME
TITLE
BO1NA1411B-E0-PCB D03
01_Title&Changes Notes
B 1 6Friday , May 13, 2016
D03BO1NA1411B-E0-DSNBO1NA1411B-E0
2015/12/11 1. Add Jump JP21,JP22 (for F/W control)BO1NA1411B-E0-D02
1
2
3
01_Title&Changes Notes
03_Power(PMU-ACT8865)
CONTENTS
4
5
6
04_JJA5D36 PWR Unit_JTAG Port
06_ISI_SPI0_ADC_USB2.0 Port
05_DBGU_USART1_4bit SDIO Port
PAGE NO
TABLE OF CONTENTS
02_BLOCK DIAGRAM
VERSION HISTORYDESCRIPTION OF CHANGES
2015/09/01
DATEJorJin REV#
Design reference data for SAMA5D36 datasheet & SAMA5D3 Xplained EVB & SAMA5D3 EK Kits.BO1NA1411B-E0-D01
35
Size
APPROVED By
Date: Sheet
PCB NAMENAME Rev Rev
/
ECN NO. REMARK
CHECKED By DESIGNED By
JorJin Technologies Inc.MODEL NAME SCHEMATIC NAME
NAME
TITLE
BO1NA1411B-E0-PCB D03
02_BLOCK DIAGRAM
A3 2 6Friday , May 13, 2016
D03BO1NA1411B-E0-DSNBO1NA1411B-E0
SK1
Socket_LGA97P_18x14SA_JJA5D3-LGA97_D01
P65H34-11
P65H34-22
P65H34-33
P65H34-44
D01-55
D01-66
D01-77
36
C11
10uF/16VC0805
C13
10uF/16VC0805
C14
10uF/16VC0805
L3 2.2uH/1.65AIND-3X3
GND
GND
GND
AC/DC Adapter5V/2A Power Input
Micro-USB_AB ReceptacleCN2 : USB 5V Power Input
R3 0RR0402
C12
100nF/25VC0402
C15
100nF/25VC0402
C23
2.2uF/16VC0603
Power Input
C22
2.2uF/16VC0603
C21
2.2uF/16VC0603
C20
100nF/25VC0402
R11
100KR0402
GND
C19 100nF/25VC0402
R1
1R/1%R0603
NRST4
Q3IRLML2502SOT23-3_NM
3
12
GND
GND
JP22
JP-254mmHDR_1X2_254MM
1
2
BP1
BP2
Place TP3&TP4 to Bottom
TP4TP_1mm
TP3TP_1mm
For S/W Control
GND
R53
4.7KR0402
R45
4.7KR0402
JP17 DNP(254mm)
1 2
R50 DNP(4.7K)R0402
TP5TP_1mm
GS DQ4
STS3415SOT23_MOS-P195
3
1
2
U3
NCP349DFN6
IN1
GND2
FLAG3
OUT-44
OUT-55
EN6
IN-7
7
1 2
OJ17 DNP(254mm)
CN1
CDS-210BDCJACK_2A
1
23
GND
5V_INPUT
GND
C62
100nF/25VC0402
C61
1uF/25VC0603
JP24 JP-254mmHDR_1X2_254MM1 2
JP1JP-254mm
1 2
1 2OJ1OJ-254mm
PMIC_1V2
PMIC_1V8
PMIC_3V3
PB1
IT-1102SA9SW_TACT_4MM5
1 243
PMIC_2V5
TWD1_PC265TWCK1_PC275
C24
2.2uF/16VC0603
U1
ACT8865QI305TQFN-32-0.4
OUT11
GN
DA
2
OUT43
OUT54
INL455
INL676
OUT67
OUT78
nPBIN9
PWRHLD10
nRSTO11
nIRQ12
nPBSTAT13
GN
DP
314
SW315
VP316
PWREN17
NC118
OUT319
VSEL20
SCL21
SDA22
VDDREF23
OUT224
NC225
VP226
SW227
GN
DP
228
GN
DP
129
SW130
VP131
REFBP32
EX
PA
D33
C1647nF/16VC0402
NRST
L5 2.2uH/1.65AIND-3X3
R447KR0402
PMIC_ACT8865 Power Circuit
VIN_5V
VCC_1V8
FIQ_PC314WKUP4
SHDN4
R47 1KR0402
Q2BSS138SOT23_MOS-P130
3
12
C9
100nF/25VC0402
FIQ_PC31
C1
4.7uF/25VC0805
VCC_5V
VCC_1V2
C18
10nF/25VC0402
C4
1uF/25VC0603
C5
1uF/25VC0603
PWRHLD
RESET
VCC_3V3
VCC_3V3
WAKUP orForce Power ON
L4 2.2uH/1.65AIND-3X3
WKUP
DVDD_3V3
FUSE_2V5Auto PWRON(option)
R210KR0402
C7
10uF/16VC0805
Q1BSS138SOT23_MOS-P130
3
12
USB-A_5V
GND
C65
10uF/16VC0805
GND
GND
R649.9K/±1%R0402
R7 49.9K/±1%R0402
R8 0RR0402
R10 0RR0402
BP
2
Size
APPROVED By
Date: Sheet
PCB NAMENAME Rev Rev
/
ECN NO. REMARK
CHECKED By DESIGNED By
JorJin Technologies Inc.MODEL NAME SCHEMATIC NAME
NAME
TITLE
BO1NA1411B-E0-PCB D03
03_Pow er(PMU-ACT8865)
B 3 6Friday , May 13, 2016
D03BO1NA1411B-E0-DSNBO1NA1411B-E0
TP1TP_1mm
TP2TP_1mm
BP
1
C3
4.7uF/25VC0805
GND
1 2OJ24 OJ-254mm
C17
4.7uF/25VC0805
GND GND GND
JP20JP-254mmHDR_1X2_254MM1 2
1 2OJ20
OJ-254mm
JP19JP-254mmHDR_1X2_254MM1 2
R9 1KR0402
1 2OJ19
OJ-254mm
JP14JP-254mmHDR_1X2_254MM1 2
1 2OJ14
OJ-254mm
JP5 JP-254mmHDR_1X2_254MM1 2
1 2OJ5 OJ-254mm
R5 100KR0402
GND
GND
C6
1uF/25VC0603
GND
GND
PB2
IT-1102SA9SW_TACT_4MM5
1 243
VIN_5V
GND
VDDREF
C8
10uF/16VC0805
C10
10uF/16VC0805
37
JP2
JP-254mmHDR_1X2_254MM
1 2
1 2OJ2
OJ-254mm
GND GND
L6 10uH/0.3AL0603
L13 10uH/0.6R/0.3AL0603
VDDIODDR_1V2
VREFCA
Power Supply for LPDDR2 VREF
C194
4.7uF/25VC0805
VDDIODDR_1V2
VREFDQ
C39
4.7uF/25VC0805
R115 0RR0603
R116 0RR0603
R117 0RR0603
R2310KR0402
JP6JP-254mmHDR_1X2_254MM1 2
C42
4.7uF/25VC0805
1 2OJ6
OJ-254mm
JP8JP-254mmHDR_1X2_254MM1 2
1 2OJ8
OJ-254mm
JP11JP-254mmHDR_1X2_254MM1 2
1 2OJ11
OJ-254mm
GND
TDO_1V8
NTRST_1V8
TDI_1V8
NRST_1V8
TCK_1V8TMS_1V8
VDDIOP0
VDDIOP0
GND
GND
GND
L19 10uH/0.3AL0603
GND
C45
4.7uF/25VC0805
L11 Bead/180R/1.5AL0603
R21
1RR0603
C100
4.7uF/25VC0805
C46
10nF/25VC0402
C51
100nF/25VC0402
L1 Bead/180R/1.5AL0603
VDDIOM
GND
L7 Bead/120R/2.5AL0603
R41
1R/1%R0603
JP12JP-254mmHDR_1X2_254MM1 2
1 2OJ12
OJ-254mm
R48
1R/1%R0603
[O]CLOCK , VDDBU
PWR:1.8V
SYSC , VDDBU
RSTJTAG , VDDIOP0
[O]
[I]
[I]
[I/O]
[I]
[I]
[I]
PWR:1.2V
[O]
[O]
PWR:3.3V
CLOCK , VDDIOP0
[I]
[I]
PWR:3.3V
[I]
[I]
PWR:1.8V or 3.3V
PWR:2.5V
DDR_IO , VDDIODDR
SYS , VDDIOP0
( for Analog )
(C4,C5 not "GND" Pin)
[I]
[I]
[I]
DNP(LD2_ZQ)
LPDDR1/LPDDR2 VREF voltage
DNP(NF_NWP)DNP(NF_R/NB)
[I]
[I][O]NAND Flash , VDDIOM
AP1A
A5-LGA97_LD2-1G-D01
GN
D-1
5
GN
D-2
25
GN
D-3
42
GN
D-4
75
GN
D-5
89
GN
D-6
90
VDDBU11
LD2-VDD1_1V823
VDDIODDR_1V2-227 VDDIODDR_1V2-126
VDDCORE_1V2-16
VDDCORE_1V2-27
VDDPLLA_1V285
VDDUTMIC_1V21
VDDIOP166
VDDIOM_3V322
VDDUTMII_3V388
VDDOSC_3V386
VDDIOP058
VDDFUSE_2V534
VDDANA_3V359
ADVREF35
LD2_VREFCA29
LD2_VREFDQ28
JTAGSEL14
WKUP12
SHDN15
NTRST81
TDO76
TMS77
TCK80
TDI78
NRST82
BMS79
TST13
NCS3_NANDCS10
NF_NCE40
XIN84
XOUT83
XIN3216
XOUT3217
DDR_CALP30
DDR_CALN31
GN
D-7
91
GN
D-8
92
GN
D-9
93
GN
D-1
094
GN
D-1
195
GN
D-1
296
GN
D-1
397
VDDCORE_1V2-38
VDDIOP0
C57
100nF/25VC0402
C59
100nF/25VC0402
C60
100nF/25VC0402
R17
1R/1%R0603
R111
1R/1%R0603
C64
100nF/25VC0402
1 2OJ16 OJ-254mm
JP9JP-254mmHDR_1X2_254MM1 2
1 2OJ9
OJ-254mm
C41
100nF/25VC0402
C43
100nF/25VC0402
C44
100nF/25VC0402
C47
100nF/25VC0402
C48
100nF/25VC0402
VDDUTMIC_1V2
C49
100nF/25VC0402
C50
100nF/25VC0402
C54
100nF/25VC0402
C55
100nF/25VC0402
C56
100nF/25VC0402
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDPLLA_1V2
JP18JP-254mmHDR_1X2_254MM1 2
LD2-VDD1_1V8
VDDIOP0_MPU
VDDIOP1_3V3
1 2OJ18
OJ-254mm
VDDIOM_3V3
VDDOSC_3V3
VDDUTMll_3V3
FUSE_2V5
VREFDQ
VREFCA
VDDCORE_1V2
R38
DNP(0R)R0402
GND
TDO_1V8
NTRST_1V8
TDI_1V8
NRST_1V8
TCK_1V8
TMS_1V8
C26
100nF/25VC0402
VDDIODDR_1V2
C27
100nF/25VC0402
C37
100nF/25VC0402
C33
100nF/25VC0402
C38
100nF/25VC0402
C35
100nF/25VC0402
C36
100nF/25VC0402
C40
100nF/25VC0402
VDDIODDR_1V2L20 Bead/120R/2.5A
L0603
VDDCORE_1V2
For S/W Control
VDDIODDR
JTAG connector
GND
VCC_1V8
JP16 PH_M_254mm_1x3HDR_1X3_254MM_DIP
1 2 3
VCC_3V3
L2 10uH/0.3AL0603
VDDPLLA_1V2
VCC_3V3
VCC_1V2
C28
4.7uF/25VC0805
VCC_1V8 LD2-VDD1_1V8
VDDIOP0_MPU
VDDIOM_3V3
VDDOSC_3V3
VDDUTMIC_1V2
Note : Use N5600 module, the VDDIOP0 v oltage Mmuct MUSTselector 1.8V(JP12.P1&P2).
R191.5K/1%R0402
SHDNWKUPJTAGSEL
TST
XIN
XOUT
R281.5K/1%R0402
NCS3
R401.5K/1%R0402
R461.5K/1%R0402
VDDIOP1 VDDIOP1_3V3
L12 Bead/180R/1.5AL0603
C96
100nF/25VC0402
R491.5K/1%R0402
R521.5K/1%R0402
VDDUTMll_3V3
R43 0RR0402
R51 0RR0402
VDDIOM
NF_NCE
XIN32
CS Nand flash memory
R26470KR0402
XOUT32 CL=12.5pF
C58
4.7uF/25VC0805
Y2 32.768KHzCY_3.2X1.5
12
C32 20pFC0402
C30 20pFC0402
TDI
CL=15pF
NRST
TMS
C29 20pFC0402
RTCKTDO
TCK
VCC_3V3
C25 20pFC0402Y1
12MHzCY_3.2X2.5_A
1 234
NTRST
CALN
CALP
R42 0RR0402
VDDIODDR
R44 0RR0402
R25 0RR0402
J3
JP-254mmHDR_2X10_254MM
12345678910111213151719
14161820
GND
GND
GND
GND
R13 0RR0402
GND
R12 0RR0402
GND
C8910uF/16VC0805
GND
GND
GND
U2
TXS0108EPWRTSSOP_PW(R-PDSO-G20)
A11
VCCA2
A23
A34
A45
A56
A67
A78
A89
OE10
GND11B812B713B614B515B416B317B218VCCB19B120
R29100KR0402
R30100KR0402
JP13
JP-254mmHDR_1X2_254MM
1 2
VCC_3V3
GND
R31100KR0402
1 2OJ13
OJ-254mmR32100KR0402
C52
100nF/25VC0402
R16 240R/1%R0402
R33100KR0402
VDDANA_3V3
R34100KR0402
R18 240R/1%R0402
FIQ_PC31_1V85
C63
4.7uF/25VC0805
(Boot Mode Select)
Voltage Level Translator (1.8V I/O to 3.3V I/O)
R35100KR0402
TDI
TDO
R36100KR0402
NTRST
TMS
DVDD_3V3
R37100KR0402
TCK
NRST NRST 3
FIQ_PC31 3
BMS_1V8
R24100KR0402
VCC_3V3
VCC_3V3
R27
4.7KR0402
JP3
JP-254mmHDR_1X2_254MM
1 2
1 2OJ3
OJ-254mm
VDDBU
GND
VCC_3V3Vbat
VDDBU_SOD
SHDN 3VDDBU Circuit
WKUP 3
Populate R19 if no Super CapR20 100R
R0402
D1
BAT54CSOT_23
32
1
GND GND
GND
R105DNP(100K)R0402
R22100KR0402
JP7JP-254mmHDR_1X2_254MM12
12OJ7
OJ-254mm
JP10
JP-254mmHDR_1X2_254MM
1
2
12
OJ10
OJ-254mm
C2
4.7uF/25VC0805GND
Size
APPROVED By
Date: Sheet
PCB NAMENAME Rev Rev
/
ECN NO. REMARK
CHECKED By DESIGNED By
JorJin Technologies Inc.MODEL NAME SCHEMATIC NAME
NAME
TITLE
BO1NA1411B-E0-PCB D03
04_JJA5D36 PWR Unit_JTAG Port
A3 4 6Friday , May 13, 2016
D03BO1NA1411B-E0-DSNBO1NA1411B-E0
L10 10uH/0.3AL0603
JP4JP-254mmHDR_1X2_254MM1 2
1 2OJ4
OJ-254mm
JP15
JP-254mmHDR_1X2_254MM
1 21 2OJ15
OJ-254mm
38
CTS1_PB26
TXD1_PB29RTS1_PB27
RXD1_PB28
TP11TP_1mm
R92
4.7KR0402
C79
4.7uF/25VC0805
C78
100nF/25VC0402
GND
GND
GND
C77 100nF/25VC0402
R9068K/1%R0402
R97 DNP(0R) R0402R99 DNP(0R) R0402
R100 DNP(0R) R0402
R101 DNP(0R)R0402
R94 0R R0402
VCC_3V3
VCC_3V3
VCC_3V3
VCC_3V3
CN3
SUBD9MDB9M_R
5
4
3
2
1
9
8
7
6
10 11
VDDIOP0
RXDC1
Power
CTSC1
RTSC1TXDC1
GND
USB Device for Debug Use (RS-232 to USB Device)
CN4
CST_CSD-11-A0000MSD-CSD-11-A0000
DAT21 DAT32 CMD3 VDD4 CLK5 VSS6 DAT07 DAT18 CD9
PG
110
PG211PG312PG413
H114H215
PD20_MCI1_PWC4
3V3_OUT
DRXD_PB30 R93 0R R0402
R79 0R R0402
DTXD_PB31
R85 0R R0402R87 0R R0402
R78 0R R0402R81 0R R0402
R83 0R R0402
R84 0R R0402
C84
10uF/16VC0805
U8
FT232RLSSOP28
TXD1
DTR2 RTS3
VCCIO4
RXD5
RI6
GND77
NC88
DSR9
DCD10
CTS11
SLEEP12 TXDEN13 PWREN14
USBDP15USBDM16
3V3OUT17
GND1818
RESET19
VCC20
GND2121
RXLED22 TXLED23
NC2424
AGND25TEST26
OSCI27
OSCO28
R86 0R R0402R88 0R R0402
DTR
CTS
TP8TP_1mm
TP6TP_1mm
TXLED
RXLED
LED1Red LEDLED0603
LED2Green LEDLED0603
MCI1 , VDDIOP1
GPIO [IO]GPIO [IO]
GPIO [IO]
GPIO [IO]
GPIO [IO]
GPIO [IO]GPIO [IO]
GPIO [IO]
GPIO [IO]
GPIO [IO]GPIO [IO]
CTS1 [I]
DTXD [O]
RTS1 [O]
RXD1 [I]
TXD1 [O]
MCI1_DA1 [IO]
MCI1_CDA [IO]MCI1_DA3 [IO]MCI1_CK [IO]MCI1_DA2 [IO]
MCI1_DA0 [IO]
USART1 , VDDIOP1
DBGU , VDDIOP0
( not "PB12" Pin )
TXD0 [O]GPIO [IO]
GPIO [IO] DRXD [I]AP1B
A5-LGA97_LD2-1G-D01
PD18_MCI1_CD57
DRXD_PB3033
DTXD_PB3132
RTS1_PB2774
TXD1_PB2973
CTS1_PB2671
RXD1_PB2872
MCI1_DA1_PB2162
MCI1_DA0_PB2061
MCI1_CK_PB2465
MCI1_CDA_PB1960
MCI1_DA3_PB2364
MCI1_DA2_PB2263
USB_5V
USB_DPUSB_DM
TP7TP_1mm
SHD
VBUSDMDPIDGND
CN5
MUSB_Molex_105017-0001MUSB_B_105017-0001_D01
12345
67
89
10
11
L17 Bead/220R/2AL0805
Micro-USB B Receptacle
EARTH_USB2
EARTH_RS232
L16 Bead/220R/2AL0805
USB_5V
R1090RR0603
R113DNP(0R)R0603
GND
R104 DNP(0R)R0402
R106 DNP(0R)R0402
C88100nF/25VC0402
3V3_OUT
R74
10KR0402
R95 47KR0402
R69
10KR0402
C80 100nF/25VC0402
C83 100nF/25VC0402
GND
C81 100nF/25VC0402
GND
C82 100nF/25VC0402
GND
U10
SN74AVC4T245DGVRTVSOP-N16-0.4
VCCA1
1A14
1A25
GND8
VCCB16
1B113
1B212
2nOE14
1DIR2
2DIR3
2A16
2A27
GND9
1nOE15
2B111
2B210
VCCA_3V3
C87100nF/25VC0402
C8610uF/16VC0805
GND
GND
DTXD_PB31_1V8
DRXD_PB30_1V8
DTXD_PB31
DRXD_PB30
VIN_5VVCC_3V3
R70
68K/1%R0402
TP9TP_1mm
J5
DNP(P101-SGP-060/030-06)HDR_1X6_254MM_DIP
123456
TP10TP_1mm
DRXD_PB30DTXD_PB31
R71
68K/1%R0402
R72
68K/1%R0402
R73
68K/1%R0402
GND
GS DQ6STS3415SOT23_MOS-P195
3
1
2
VDD3V3_MCI1
C85
100nF/25VC0402
PD18_MCI1_CDMCI1_DA1_PB21
MCI1_CK_PB24
MCI1_DA0_PB20
MCI1_DA3_PB23
VDD3V3_MCI1
MCI1_CDA_PB19
MCI1_DA2_PB22
Micro SD Card (Use MCI1 4bit Interface)
R78,R81,R83,R84,R86,R88 nearCN4 connector place
GND
TP12TP_1mm
R75
47KR0402
R76
47KR0402
R77
47KR0402
3V3_OUT
VCC_3V3
DRXD_PB30_1V8
DTXD_PB31_1V8
C94 100nF/25VC0402
C95100nF/25VC0402
Size
APPROVED By
Date: Sheet
PCB NAMENAME Rev Rev
/
ECN NO. REMARK
CHECKED By DESIGNED By
JorJin Technologies Inc.MODEL NAME SCHEMATIC NAME
NAME
TITLE
BO1NA1411B-E0-PCB D03
05_DBGU_USART1_4bit SDIO Port
B 5 6Friday , May 13, 2016
D03BO1NA1411B-E0-DSNBO1NA1411B-E0
R961KR0402
R80 330R R0402
R981KR0402
R8968K/1%R0402
U7
ADM3312EARUTSSOP24
VCC3
GND23
V+1
V-21
SD19
EN5
T1IN7
T2IN8
T3IN9
R1OUT10
R2OUT11
R3OUT12
C1+6
C1-20
C2+2
C2-4
C3+24
C3-22
T1OUT18
T2OUT17
T3OUT16
R1IN15
R2IN14
R3IN13
39
GNDGNDGND
GND
VBG
GND
R660RR0402R65
10KR0402
DHSDP [IO]
FIQ [I]
HHSDMA [IO]
IRQ [I]
DHSDM [IO]USB , VDDUTMII
GPIO [IO]
ADC , VDDANA
AIC , VDDIOP0
HHSDPA [IO]
EBI [IO]
IO , VDDIOM
TCLK2 [I]TXD2 [O]RTS2 [O]RXD2 [I]CTS2 [I] EBI [IO]
EBI [IO] EBI [IO] EBI [IO] EBI [IO]
AD0 [I]
AD5 [I]GPIOANA [IO]GPIOANA [IO]
GPIOANA [IO]
AD1 [I]
AD9 [I]GPIOANA [IO]
GPIO [IO]
GPIO [IO]GPIO [IO] ISI_D4 [I]
ISI_HSYNC [I]
ISI_D3 [I]ISI_D2 [I]
ISI_PCK [I]
ISI_D5 [I]GPIO [IO]
GPIO [IO]
PCK1 [O]GPIO [IO]
ISI_D0 [I]GPIO [IO]
GPIO [IO]
(ISI_MCK)
ISI_D1 [I]
ISI_D6 [I]
PLL , VDDANA
ISI_D7 [I]ISI_VSYNC [I]
GPIO [IO]GPIO [IO]
GPIO [IO]
GPIO [IO]
I2C , VDDIOP0
GPIO [IO] TWD1 [IO]GPIO [IO] TWCK1 [IO]
(I2C)
SPI-0 , VDDIOP1 ISI , VDDIOP0SPI0_MOSI [IO]SPI0_MISO [IO]SPI0_SPCK [IO] GPIO [IO]GPIO_CLK [IO]GPIO [IO]
SPI0_NPCS0 [IO] GPIO [IO]
A5-LGA97_LD2-1G-D01
AP1C
GNDUTMI4
SPI0_MOSI_PD1169
SPI0_MISO_PD1068
SPI0_SPCK_PD1267
SPI0_NPCS0_PD1370
PD20_MCI1_PWC37
PD25_USBA_EN5V38
PD21_USBA_OVCUR36
PD29_USBA_VSENSOR39
HHSDMA3
HHSDPA2
VBG87
ISI_D0_PA1651
ISI_D1_PA1747
ISI_D2_PA1854
ISI_D3_PA1948
ISI_D4_PA2053
ISI_D5_PA2149
ISI_D6_PA2252
ISI_D7_PA2350
ISI_VSYNC_PA3056
ISI_HSYNC_PA3155
ISI_PCK_PC3046
PCK1_PD3141
TWD1_PC2643
TWCK1_PC2744
FIQ_PC3145
PE23_PWR_ENA24
PE24_ENG_RST18
PE25_AIM_ON9
PE26_ILL_ON19
PE29_Buzzer20
IRQ_PE3121
C66
100nF/25VC0402
R54100KR0402
GND
SPI0_SPCK_PD12
SPI0_NPCS0_PD13
SPI0_MOSI_PD11SPI0_MISO_PD10
SPI0 Interface
VDDIOP0
GND
R61
1.5K/1%R0402
R57
1.5K/1%R0402
R59
1.5K/1%R0402
R60
1.5K/1%R0402
C70
100nF/25VC0402
VCC_3V3
C69
100nF/25VC0402
TWD1_PC26_1V85TWCK1_PC27_1V85
GND GND
VCC_3V3
R58
200KR0402
TWD1_PC26 3TWCK1_PC27 3
VCC_3V3
U6
PCA9306DP1TSSOP8_SOT505-2
GND1
VREF12
SCL13
SDA14
SDA25SCL26VREF27EN8
I2C 1.8V Translator 3.3V
R67 1KR0402
For S/W Control
R68 100KR0402
GND
JP25
JP-254mmHDR_1X2_254MM
1 2
1 2OJ25
OJ-254mm
VCC_3V3
C9210uF/16VC0805
SB_5V SB_3V3
VCC_1V8
SB_3V3
Q5LS3019NSOT-523
3
12
BUZZER
PE29_Buzzer
C9310uF/16VC0805
SB_1V8
D2
BAS316SOD-323
2
1
C74
100nF/25VC0402
C75100nF/25VC0402
Push-Bottum switch
VCC_3V3
IRQ_PE31
ISI-Image Sensor Interface
ISI_D1_PA17ISI_D3_PA19ISI_D5_PA21ISI_D7_PA23
JP23
JP-254mmHDR_1X2_254MM
1 2
ISI_PCK_PC30ISI_D0_PA16
ISI_D6_PA22ISI_D4_PA20ISI_D2_PA18
1 2OJ23
OJ-254mmTWCK1_PC27 TWD1_PC26
PCK1_PD31ISI_VSYNC_PA30ISI_HSYNC_PA31
PE29_Buzzer IRQ_PE31PE26_ILL_ONPE25_AIM_ON
PE23_PWR_ENAPE24_ENG_RST
SB_1V8
1 2OJ26
OJ-254mm
JP26
JP-254mmHDR_1X2_254MM
1 2
VCC_1V8 SB_1V8
BZ1
XCM09B-1.5GBZ-MR09-4
1
2
D3
DNPSOD-323
12
1 2OJ27
OJ-254mm
C7610uF/16VC0805
JP27
JP-254mmHDR_1X2_254MM
1 2
SB_5VVIN_5V
J4
P605-R2GN-030-17HDR_2X17_127MM
13579
111315171921232527293133
246810121416182022242628303234
SB_3V3
SB_5V
C9110uF/16VC0805
R102
5.62K±1%R0402
R39 0RR0603
C90
10pF/50VC0402
USB A HOST/DEVICE INTERFACE
EARTH_USB1
L15 Bead/220R/2AL0805
HHSDPA(USB-A_ID) VCC_3V3
HHSDMA
USB-A_5V
Micro-USB AB Receptacle
IRQ_PE31
PE29_Buzzer
PE24_ENG_RST
PE23_PWR_ENA
PE25_AIM_ON
FIQ_PC31_1V8 4
PE26_ILL_ONSHD
VBUSDMDPID
GND
CN2
MUSB_Molex_47589-0001MUSB-AB_47589-0001-V1
12345
67
89
10
11
GNDUTMIGND
R64 47KR0402
GND
JP21
JP-254mm
HDR_1X2_254MM
1
2
GND
R103 DNP(0R)R0603
PD20_MCI1_PWC5PD20
R55
249K/1%R0402
* Vbat-detect=3.7V*R55/(R55+R56) Vbat-detect=2.745V (L0-Power)* Vbat-detect=4.2V*R55/(R55+R56) Vbat-detect=3.116V (Hi-Power)
* System Detect Range : 2.745V~3.116V (0.371V) * Li-Battery Voltage Range : 3.7V~ 4.2V
Li Battery Low Power DetectR56 86.6K/1%
R0402
GND
C67
100nF/25VC0402
Vbat
R82 0RR0402
D4
DNPSOD-323
12
L14 Bead/220R/2AL0805 VIN_5V
C71
100nF/25VC0402
U5
AIC1526-1GSSOP8
ENA1
FLGA2
ENB4
OUTA8
GND6
FLGB3
IN7
OUTB5
PD21_USBA_OVCUR
USB-A HOST Control
GNDGND
PD25_USBA_EN5V
C72
10uF/16VC0805
ISI_D2_PA18
ISI_D5_PA21ISI_D6_PA22
ISI_D4_PA20
ISI_D7_PA23
C68
100nF/25VC0402
ISI_HSYNC_PA31ISI_VSYNC_PA30
ISI_D0_PA16ISI_D1_PA17
ISI_D3_PA19
PCK1_PD31
ISI_PCK_PC30
TWD1_PC26_1V8
TWCK1_PC27_1V8
R63
82KR0402
PD29_USBA_VSENSE
C73
15pF/50VC0402 GNDGND
R62 47KR0402
PB3
IT-1102SA9SW_TACT_4MM5
124 3
U4
N25Q032A13ESE40FSO8W(SOP2-8)
DQO5
DQ12
C6
S1
VCC8
W/Vpp/DQ23
HOLD/DQ37
GND4
Size
APPROVED By
Date: Sheet
PCB NAMENAME Rev Rev
/
ECN NO. REMARK
CHECKED By DESIGNED By
JorJin Technologies Inc.MODEL NAME SCHEMATIC NAME
NAME
TITLE
BO1NA1411B-E0-PCB D03
06_ISI_SPI0_ADC_USB2.0 Port
B 6 6Friday , May 13, 2016
D03BO1NA1411B-E0-DSNBO1NA1411B-E0
111. Ap
ppendix
x_A:B
(Top View
BO1NA
w)
40
A1411B
B-S0 Co
(Bottom
ompon
m View)
nent Lo
ocationn
41
12. Appendix_A:BO1NA1411B-S0 Schematics
Size
APPROVED By
Date: Sheet
PCB NAMENAME Rev Rev
/
ECN NO. REMARK
CHECKED By DESIGNED By
JorJin Technologies Inc.MODEL NAME SCHEMATIC NAME
NAME
TITLE
BO1NA1411B-S0-PCB D01
01_BLOCK DIAGRAM (N5600 Barcode board)
A3 1 2Monday , May 16, 2016
D01BO1NA1411B-S0-DSNBO1NA1411B
USB
NRSTkey
EBI
UART
JTAG
ISI
PIO A,...E
PIO B&E
PIO A&D
PIO
CONNECTOR
PIO C
VBAT
3V3 INPUT
PIO
CONNECTOR
PIO
CONNECTOR
SODIMM
CONNECTOR
ATMELARMA5 PROCESSOR SAMA5
Button
Power
ANALOG Reference
BuzzerDetec_inX
ICE
CS BootKEY
Imageconnector
Blue LED
2Gb NANDFLASH
2GbLPDDR2SDRAM
PIO A,...E
OSC26.67MHz
EBI
DIB
USB A
Imagedevice
ISI
42
C5 4.7uF/6V3C0603-E
GND
CN1
Molex_55909-0374BTB-ML-0374
HS
YN
C_O
1G
ND
42
VS
YN
C_O
3IM
G_D
5_O
4IM
G_D
4_O
5IM
G_D
6_O
6G
ND
17
IMG
_D7_
O8
EN
G_R
ES
ET
_IN
9G
ND
510
Fla
sh_O
UT
_O11
PC
LK_O
12N
/C13
GN
D6
14G
ND
215
AIM
_ON
_IN
16I2
C_S
CL
17IL
L_O
N_I
N18
IMG
_D3_
O19
PW
R_E
NA
_IN
20G
ND
321
GN
D7
22IM
G_D
2_O
23I2
C_S
DA
24IM
G_D
0_O
25V
IN_3
V3_
LED
_LA
SE
R1
26V
IN_3
V3_
IMG
R27
VIN
_3V
3_LE
D_L
AS
ER
228
IMG
_D1_
O29
GN
D8
30
SG131
SG232
SG333
SG434
GND
ISI_D1
ISI_D2
ISI_D3
ISI_D0
LED_3V3
I2C_SCL
Flash_OUT
Size
APPROVED By
Date: Sheet
PCB NAMENAME Rev Rev
/
ECN NO. REMARK
CHECKED By DESIGNED By
JorJin Technologies Inc.MODEL NAME SCHEMATIC NAME
NAME
TITLE
BO1NA1411B-S0-PCB D01
02_Honeyw ell-N5600(Undecode)
A4 2 2Monday , May 16, 2016
D01PBO1NA1411B-S0-DSNBO1NA1411BISI_D4
ISI_VSYNC
ISI_HSYNC
GND
C110uF/6V3C0603-E
VCC_5V VCC_1V8VCC_3V3
C4 4.7uF/6V3C0603-E
I2C_SDA
ILL_ON
AIM_ON
ISI_PCK
ISI_D7
ISI_D6
ISI_D5
L1 180ohm/1.5AL0603-E
R11 4.87K/1%R0402-E
R1 22RR0402-E
R3 22RR0402-E
R2 22RR0402-E
R4 22RR0402-E
R6 0RR0402-E
R5 0RR0402-E
R9 0RR0402-E
R7 0RR0402-E
R12 0RR0402-E
R13 0RR0402-E
R16 22RR0402-E
R15 22RR0402-E
R18 22RR0402-E
R17 22RR0402-E
R20 22RR0402-E
R19 22RR0402-E
R14 22RR0402-E
L2 180ohm/1.5AL0603-E
PA19_ISI_D3
PA17_ISI_D1
PA16_ISI_D0
PA18_ISI_D2
PA20_ISI_D4
PA30_ISI_VSYNC
PA31_ISI_HSYNC
PE24_ENG_RST_3V3
TP4TP_1mm
VCC_3V3
Flash_OUT_1V8
VCC_3V3
PE23_PWR_ENA_3V3
PE25_AIM_ON_3V3
PE26_ILL_ON_3V3
PA23_ISI_D7
PC30_ISI_PCK
PA21_ISI_D5
PA23_ISI_D7
PA22_ISI_D6
ISI Interface
PA21_ISI_D5PA19_ISI_D3PA17_ISI_D1 PA18_ISI_D2
PA20_ISI_D4PA22_ISI_D6
PA16_ISI_D0PC30_ISI_PCKPA31_ISI_HSYNCPA30_ISI_VSYNCPD31_ISI_MCKPC26_SDA_1V8PC27_SCL_1V8
PE24_ENG_RST_3V3PE23_PWR_ENA_3V3
PE25_AIM_ON_3V3PE26_ILL_ON_3V3PE31_BUTTONPE29_Buzzer
IMGR_3V3
VCC_1V8VCC_5V VCC_3V3J1
P605-R2GN-030/023-34PH_M90_127MM_2X17_DIP
13579
111315171921232527293133
246810121416182022242628303234
GND
GND
ENG_RST
R8 10KR0402-E
PC26_SDA_1V8
PC27_SCL_1V8
TP2TP_1mm
TP3TP_1mm
TP1TP_1mm
R10 0RR0402-E
C210uF/6V3C0603-E
C310uF/6V3C0603-E