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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Bruce Mayer, PERegistered Electrical & Mechanical Engineer
Engineering 43
FETs-3(Field Effect Transistors)
[email protected] • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx2
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Learning Goals Understand the Basic Physics of
MOSFET Operation Describe the Regions of Operation of a
MOSFET Use the Graphical LOAD-LINE method
to analyze the operation of basic MOSFET Amplifiers
Determine the Bias-Point (Q-Point) for MOSFET circuits
[email protected] • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx3
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Learning Goals Analyze the I/O relationship for
small-signal Amplifiers Determine the OutPut for Various
CMOS Logic Gates
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
“Common” – What does it mean? “Common” is an electronics term that
usually means a digital-GROUND of Some Sort.
Recall that in the small Signal Case that VDC Sources are effectively SHORTS to the Small-Signal “Common”, or GND Connection• Example: A “common-source” MOSFET
amp has the source connected to small-signal GND somehow
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Refined Small Signal Model The KCL Equation for the model
that accounts for the upward iD Slope in SAT
The Graphical Representation d
dsgsmd r
vvgi
dsv
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Common Source Amplifier A typical “CS” Amp Circuit
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Common Source Amplifier Analyze,
Qualitatively the CS Amp Circuit
Recall for Caps• SHORTS to fast AC• OPENS to DC
C1 and C2 are “Coupling” capacitors• C1 couples the input
to the MOSFET gate• C2 couple the Output
to the Load, RL
CS connects the FET Source-Connection to GND (or Common)
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Common Source Amplifier Analyze,
Qualitatively the CS Amp Circuit
Resistors R1, R2, RD, and RS form the Bias Network
The Bias Network is designed to set the Q-Point to allow a large swing in the output signal, vo, as a result of large input Voltage (vin = vgs) Changes.• The FET MUST
Remain in SATURATION during the entire Swing
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CS-Amp Small Signal Model Recall the Small Signal FET Model from
Last time Note that Caps & DC-Srcs are Shorts Yields the small signal Model
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
LargeSmall Signal Model→ ShortTo ACSignals
𝐺𝑆
𝐷𝐺𝑁𝐷 𝐺𝑁𝐷
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CS-Amp Voltage Gain
By Parallel Resistors
Use these equivalent Resistances to simplify the small signal Ckt
Also define vin and vo for the equivalent circuit
21
21
RRRRRG
LDdL RRrR1111
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CS-Amp Voltage Gain
By V-Divider on Left Loop
On Right (OutPut) Loop
Thus by Ohm
Also Thus Av:
gsv
ov
inv
ini oi
G
Gin RR
Rtvv
gsmvg
gsmo vgi
gsmLoLo vgRiRv
gsin vv
mLgs
gsmL
in
ov gR
vvgR
vvA
[email protected] • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx13
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CS-Amp input Resistance
Recall R = ∆V/∆I For the Common
Source Amp
From Before
Thus Rin
gsv
ov
inv
ini oi
Gin
inG
in
inin R
iiR
ivR
gsmvg
21
21
RRRRRG
21
21
RRRRRR Gin
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CS Amp OutPut Resistance To find the OUTput
Resistance• Set v(t) = 0
– i.e.; it becomes a SHORT
• Disconnect Load RL
• Find R Looking into the RL terminals
This Produces the Ro circuit
Since vgs = 0 V, then gmvgs = 0 amps• i.e.; the dependent
current source is OPEN Thus can Find Ro by
Parallel combination
Dd
Ddo Rr
RrR
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Check by Thévenin:
[email protected] • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx16
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Check by Thévenin:
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Source Follower Circuit
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Source Follower Circuit Notes on SF Ckt
• R is the internal (Thévenin)resistance of the input source
• C1 and C2 are Coupling Capacitors– They are SHORTS to the Small Signal
• R1, R2, and RS form the Bias (Q-Pt) Network
• In Small-Signal vd connected to GND
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
SF Large Signal Model
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
SF Large Signal Model
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Source Follower Circuit Note that in this case the DRAIN is
connected to DC-Source VDD; a SHORT to the Small Signal.
Then the Small Signal Model
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
SF Small Signal Model
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Source Follower Circuit Again, Equivalent
Resistances
Note that in this Circuit the Drain is at the Bottom (GND’d), and Source is at the Top
Then the Equivalent Model
By Ohm on the Rt
21
21
RRRRRG
LDdL RRrR1111
LRGR
LgsmLoo RvgRiv
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Source Follower Circuit
Note that the• Source is at the vo Voltage• Gate is at the vin Voltage as iin =0
Then by KVL on a clever Loop ogsin
ingso
vvv
vvv
or0
LRGR
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Source Follower Circuit But
recall Substitute out vo in
the previous Eqn
Then the Voltage Gain (amplification)
Factor out vgs
Cancelling vgs Find in the Small Signal Case:
LgsmLoo RvgRiv
Lgsmgsin
ogsin
Rvgvv
vvv
or
Lgsmgs
Lgsm
in
ov Rvgv
RvgvvA
Lmgs
Lmgsv Rgv
RgvA
1
Lm
Lmv Rg
RgA
1
LRGR
[email protected] • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx26
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Source Follower Circuit The Input
Resistance
For Ro • Set v(t) = 0
– i.e.; Short it• Remove RL
• Apply a Voltage PROBE to SD Connections
The probed Circuit
Then Ro =vx/ix • Note that vin = 0 (no
Pwr Src) → G-terminal is at GND
21
21
RRRRR
iv
Gin
in
LRGR
[email protected] • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx27
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Source Follower Circuit And vs fixed at vx so
Now KCL at Top-Right node (in = out)
Subbing out vgs
Collecting Terms
Then Ro =vx/ix
S
x
d
xxgsm R
vrvivg
xgs
xsggs
vv
vvvv
or
0
S
x
d
xxxm R
vrvivg
mSd
xx
xmS
x
d
xx
gRr
vi
vgRv
rvi
11
or
m
Sdx
xo g
RrivR 111
[email protected] • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx28
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Recall from Chp7 Logic Gates
Truth Tables Describe the I/O behavior of Logic Gates, but NOT how they are constructed
Most Modern Logic gates are built from collections of MOSFETS
NOT (inverter) Input = 1 Output = 0 Input = 0 Output = 1
NAND (all high = low, else high) Input 1 Input 2 Output
0 0 1 0 1 1 1 0 1 1 1 0
NOR (any high = low, else high) Input 1 Input 2 Output
0 0 1 0 1 0 1 0 0 1 1 0
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Alternative Symbols for MOSFETs nMOSFETs
• “ON”: when VGS POSITIVE
pMOSFETs• “ON”: when VGS
NEGATIVE
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Alternative Symbol Meaning The Arrow shows the direction of
Current flow in SOURCE Connection
• In an nFET current flows: Drain→Source– Current flows OUT of the source when FET On
• In a pFET current flows: Source→Drain– Current flows Into the Source when FET On
nFETpFET
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CMOS What is it? “CMOS” it the technology used in
Digital Integrated Circuits such as MicroProcessors. The Meaning
C ≡ Complementary ← The key M ≡ Metal O ≡ Oxide S ≡ Silicon
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Complementary Logic In Perfect Complementary Logic circuits
every nFET (or pFET) has it’s opposite, or complementary pFET (or nFET)
Example: CMOS Inverter
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Switch Model for CMOS Logic Ckts The INPUT to CMOS Logic Circuits is
assumed to be DIGITAL; that is the Input is one of• Hi (usually VDD) OR Lo (usually GND)
Example: CMOS Inverter
(a) Input isLo;Output is Hi
(a) Input isHi:Output is Lo
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CMOS Inverter Summarized Note that SOURCE and
BODY are “tied Together”• This is very typical for
Enhancement Mode MOSFETS A third Alternative seen in
Logic Ckt Analysis is the “Invert BUBBLE” on the pFET
nFET pFET
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Invert-Bubble Inverter Circuit Using the
Inversion-Bubble facilitates drawing and analysis of CMOS Logic Circuits.
The “Bubble” Version of the Inverter ckt
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CMOS Voltage Levels for 1 & 0 As discussed previously a “digital” 1 or
0 is represented by a RANGE (analog) of Voltage Levels. For typical CMOS
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CMOS NAND Gate NAND: All Hi → Lo, else Hi
Basic Circuit A-Hi & B-LoVout Connected to
VDD
BOTH A & B HiVout Connected to
GND
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CMOS NAND “Switch” Analysis Drawing the FETs as switches can
Speed and/or Clarify the output analysis
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CMOS NAND “Bubble” Analysis
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CMOS NOR Gate NOR: Any Hi → Lo, else Hi
Basic Circuit A-Hi & B-LoVout Connected to
GND
BOTH A & B LoVout Connected to
VDD
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CMOS NOR Switch Analysis NOR: Any Hi → Lo, else Hi
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
WhiteBoard Work Determine the TRUTH Table for the
CMOS Logic Gate Below
A B OutL LL HH LH H
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
All Done for Today
TypicalCMOS gateI/O Curve
CMOS Inverter
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Bruce Mayer, PERegistered Electrical & Mechanical Engineer
Engineering 43
Appendix
Other CMOS Gates
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
DC Srcs SHORTS in Small-Signal In the small-signal equivalent circuit DC
voltage-sources are represented by SHORT CIRUITS; since their voltage is CONSTANT, the exhibit ZERO INCREMENTAL, or SIGNAL, voltage
Alternative Statement: Since a DC Voltage source has an ac component of current, but NO ac VOLTAGE, the DC Voltage Source is equivalent to a SHORT circuit for ac signals
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Ways to Make 1’s & 0’s
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
3-Input NAND
Ref: 2010-005. Wakerly - Chapter_03 - logic gates_VERYGood.pptx
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CMOS Buffer (Unity Gain) Inverters in SERIES
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
AND Gate
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
AND-OR-INVERT gate
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
AND-OR-INVERT gate SYMBOL
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
OR-AND-INVERT gate
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
OR-AND-INVERT gate SYMBOL
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
HC CMOS Logic-Family Noise Lvls Noise levels
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
[email protected] • ENGR-43_Lec-12c_FETs-3_MOSamps_MOSgates.pptx57
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis