Fall 2006
Lillevik 333f06-l15 1University of Portland School of Engineering
EE 333
Computer OrganizationLecture 15
ROM, RAM memory design
Direct-mapped cache memory
Fall 2006
Lillevik 333f06-l15 2University of Portland School of Engineering
EE 333
Memory design goals
• Unlimited memory size– No upper bound on memory addresses– Not practical or possible: cost, implementation
• Infinite memory bandwidth– Zero latency memory accesses– Not practical or possible: cost, laws of physics
• Memory hierarchy can approximate goals
Fall 2006
Lillevik 333f06-l15 3University of Portland School of Engineering
EE 333
General memory design
A
DQ
E
R/W
A
DQ
E
R/W
In 0
E
1
n
AddressData
R/W
Qout(lower bits)
(upper bits)
decoder
memory
memory
Fall 2006
Lillevik 333f06-l15 4University of Portland School of Engineering
EE 333
RAM design: 16x8Use 16x4
Fall 2006
Lillevik 333f06-l15 5University of Portland School of Engineering
EE 333
RAM 16x8 trace
Writing Reading
Fall 2006
Lillevik 333f06-l15 6University of Portland School of Engineering
EE 333
RAM design: 32x8 ?Use 16x4
Fall 2006
Lillevik 333f06-l15 7University of Portland School of Engineering
EE 333
RAM 32x8 trace
Writing
Reading
Fall 2006
Lillevik 333f06-l15 8University of Portland School of Engineering
EE 333
Main and cache memory
Each memory may contain a subset of the others
Processor
Data are transferred
Cache
Main
Fall 2006
Lillevik 333f06-l15 9University of Portland School of Engineering
EE 333
Principle of locality
Programs access a relatively small portion of their address space at any instant of time
• Temporal locality: once memory is accessed, its likely to be accessed again (locality in time)
• Spatial locality: once a memory address is selected, its neighbors are likely to be selected (locality in space)
Fall 2006
Lillevik 333f06-l15 10University of Portland School of Engineering
EE 333
Memory-cache mappings
• Lower address bits access cache• Upper address bits (tag) stored in an extra
memory, same length as cache• Accesses
– Upper address bits compared to tag bits– Result
• Hit: a match is found, data in cache• Miss: no match, data in main memory
Fall 2006
Lillevik 333f06-l15 11University of Portland School of Engineering
EE 333
Four cache cases
• Read– Hit– Miss
• Write– Hit – Miss
NOTE: hit rate + miss rate = 1.0
Fall 2006
Lillevik 333f06-l15 12University of Portland School of Engineering
EE 333
Direct-mapped cache
Memory-cache mappings not unique!
00001 00101 01001 01101 10001 10101 11001 11101
000
Cache
Memory
001
01
001
11
001
011
101
11
8-word cache
32-word memory
Fall 2006
Lillevik 333f06-l15 13University of Portland School of Engineering
EE 333
Cache writes
• Data from CPU written to cache
• Tag bits of address written to cache tag memory
• Data from CPU written to memory (write-through)
• Valid bit set
Fall 2006
Lillevik 333f06-l15 14University of Portland School of Engineering
EE 333
Index Tag DataV000001010011100101110111
NNNNNNNN
Filling the cache
000
Y 10 Mem (10110)
Y 11 Mem (11010)
Y 10 Mem (10000)
Y 00 Mem (00011)
Memory word, tag written upon cache miss
Fall 2006
Lillevik 333f06-l15 15University of Portland School of Engineering
EE 333
Find the cache contents?
CPU write Cache write
adr data tag adr data0 0001 0x123 00 001 123
1 1001 0x555 11 001 555
0 1111 0xaaa 01 111 aaa
0 0101 0x321 00 101 321
1 0001 0xabc 10 001 abc
Assume: 32 word memory, 8 word cache
Fall 2006
Lillevik 333f06-l15 16University of Portland School of Engineering
EE 333
Cache reads
• Hit– Data from cache sent to CPU– Access time very fast
• Miss– Data from memory sent to CPU– Data also written into cache– Tag bits written to tag memory– Access time slow
Fall 2006
Lillevik 333f06-l15 17University of Portland School of Engineering
EE 333
Read hit or miss?
Cache memory
index tag data000 10 0x123
001 11 0x456
010 01 0x789
011 00 0xabc
100 01 0xdef
101 11 0x123
110 10 0x456
111 00 0x789
CPU read
adr hit/miss1 0000 h
0 0011 H
1 0001 M
0 1111 m
1 1101 H
0 1010 H
0 0000 M
0 0011 H
Fall 2006
Lillevik 333f06-l15 18University of Portland School of Engineering
EE 333
Another look at writes
• Write-through (hits & misses the same)– All writes update memory and cache– Simple, less expensive, slow
• Write-back (hits & misses different)– A write updates cache only (inconsistency)– Memory updated only for write miss to
modified cache (miss modified)– Faster, more expensive
Fall 2006
Lillevik 333f06-l15 19University of Portland School of Engineering
EE 333
Write back cache
“Miss modified” blocks must update (WB) memory
Index Tag DataV000001010011100101110111
YNYYNNYN
000
N 10 Mem (10110)
Y 11 Mem (11010)
N 10 Mem (10000)
Y 00 Mem (00011)
MN 11 Mem (11000) No write back
N 10 Mem (10010) Write backN 01 Mem (01011) Write back
N 01 Mem (01110) No write back
Fall 2006
Lillevik 333f06-l15 20University of Portland School of Engineering
EE 333
Write-back?
Cache memory
index V M tag data000 Y Y 10 0x123
001 N Y 11 0x456
010 N N 01 0x789
011 Y Y 00 0xabc
100 Y N 01 0xdef
101 Y Y 11 0x123
110 Y Y 10 0x456
111 N Y 00 0x789
CPU write
adr hit? WB?1 0001
1 1101
0 0011
0 0011
1 0000
0 1110
0 0000
0 1111
Fall 2006
Lillevik 333f06-l15 21University of Portland School of Engineering
EE 333
Fall 2006
Lillevik 333f06-l15 22University of Portland School of Engineering
EE 333
RAM design: 32x8 ?Use 16x4
Fall 2006
Lillevik 333f06-l15 23University of Portland School of Engineering
EE 333
Find the cache contents?
CPU write Cache write
adr data tag adr data0 0001 0x123 00 001 0x123
1 1001 0x555 11 001 0x555
0 1111 0xaaa 01 111 0xaaa
0 0101 0x321 00 101 0x321
1 0001 0xabc 10 001 0xabc
Assume: 32 word memory, 8 word cache
Fall 2006
Lillevik 333f06-l15 24University of Portland School of Engineering
EE 333
Read hit or miss?
Cache memory
index tag data000 10 0x123
001 11 0x456
010 01 0x789
011 00 0xabc
100 01 0xdef
101 11 0x123
110 10 0x456
111 00 0x789
CPU read
adr hit/miss?1 0000 h
0 0011 h
1 0001 m
0 1111 m
1 1101 h
0 1010 h
0 0000 m
1 0011 m