ESSDERC ‘02
Gate Oxide Process Impact on RNCE Gate Oxide Process Impact on RNCE for Advanced CMOS for Advanced CMOS TTransistorsransistors
F.Arnaud*, M.Bidaud***STMicroelectronics, Central R&D, 850 rue J.Monet 38926 Crolles, FRANCE
**Philips Semiconductors, 850 rue J.Monet 38926 Crolles, FRANCE
Sept. 2002 / Firenze / Italy 2ESSDERC ‘02
F.Arnaud and M.Bidaud
OutlineOutline
IntroductionParasitic effect of gate oxidation stepsExperimental matrix desciptionReverse Narrow Channel Effect (RNCE)– Threshold Voltage– Body Factor
Edge current tool– Theory and test structure– Measurement and temperature effect
Conclusions
Sept. 2002 / Firenze / Italy 3ESSDERC ‘02
F.Arnaud and M.Bidaud
Introduction Introduction (1/2)(1/2)
0
1
2
3
4
5
6
Technology node
EO
T (n
m)
EOT= Equivalent Oxide Thickness
EOT reduction best process way to enhance Ion/Ioff compromize
Sept. 2002 / Firenze / Italy 4ESSDERC ‘02
F.Arnaud and M.Bidaud
Introduction Introduction (2/2)(2/2)
MOSFET mobility degradation at low electric field
Gate leakage reduction w.r.t. pure oxide at same EOT
N.B.T.I. degradation due to nitrogen at Si-SiO2interface
Inihibition of P+ gate Boron diffusion inisdeP-channel
RisksAdvantages
Oxynitride introduction for advanced gate material induced:
This work: we studied the impact of gate oxidation mode on RNCE
Sept. 2002 / Firenze / Italy 5ESSDERC ‘02
F.Arnaud and M.Bidaud
OutlineOutline
IntroductionParasitic effect of gate oxidation stepsExperimental matrix desciptionReverse Narrow Channel Effect (RNCE)– Threshold Voltage– Body Factor
Edge current tool– Theory and test structure– Measurement and temperature effect
Conclusions
Sept. 2002 / Firenze / Italy 6ESSDERC ‘02
F.Arnaud and M.Bidaud
Dopants Dopants segregation phenomena segregation phenomena (1/2)(1/2)
After gate oxidation stepsBefore gate oxidation steps
> 5.1017 at/cm3
< 5.1017 at/cm3
STIActive area
Uniform Channel doping
> 5.1017 at/cm3
< 5.1017 at/cm3
STIActive area
Final Channel doping
☹ Gate oxidation process induced a Channel-Boron pumping toward the trench oxide
This parasitic effect is called dopants segregation effect
Sept. 2002 / Firenze / Italy 7ESSDERC ‘02
F.Arnaud and M.Bidaud
Dopants Dopants segregation phenomena segregation phenomena (2/2)(2/2)
Dopants segregation consequencies:
Bulk doping reduction Nb Nbeff
Vth of narrowest transistor reduction
SRAM leakage static consumption increase
Parasitic ‘’ hump’’ effect with back bias
Segregation coefficient:
meff = m0 . Exp (- Ea/k.T)
meff depends strongly on gate oxidation characteristic (T°, time, ambient …)
Sept. 2002 / Firenze / Italy 8ESSDERC ‘02
F.Arnaud and M.Bidaud
RNCE RNCE and Iand IedgeedgeNarrow deviceLarge device
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
0.1 1 10
Wg (µm)
Vth
/Vth
(w=1
0µm
) ra
tio
S DG
S DG
Parasitic area
Vthchannel > Vth
parasitic
Iofftransistor = Ichannel.Wg + 2.Iedge
Sept. 2002 / Firenze / Italy 9ESSDERC ‘02
F.Arnaud and M.Bidaud
OutlineOutline
IntroductionParasitic effect of gate oxidation stepsExperimental matrix desciptionReverse Narrow Channel Effect (RNCE)– Threshold Voltage– Body Factor
Edge current tool– Theory and test structure– Measurement and temperature effect
Conclusions
Sept. 2002 / Firenze / Italy 10ESSDERC ‘02
F.Arnaud and M.Bidaud
Experimental matrixExperimental matrix
141.6RTN 950°CDPN 35sNO anneal 1000°C/15s
RTN + DPN + Anneal
101.8RTO 900°CDPN 35sNO anneal 1000°C/15s
RTO + DPN + Anneal
81.65RTO 900°CDPN 35s
RTO + DPN
41.8RTO 900°CRTN 950°C
RTO + RTN
02.0Pure oxideRTO 900°C
RTO
NitrogenConc.(%)
EOT*(nm)
Process featuresGate oxideProcess
* All the EOT values have been extracted from C-V curve fitting by Schrödinger-Poisson method
Sept. 2002 / Firenze / Italy 11ESSDERC ‘02
F.Arnaud and M.Bidaud
OutlineOutline
IntroductionParasitic effect of gate oxidation stepsExperimental matrix desciptionReverse Narrow Channel Effect (RNCE)– Threshold Voltage– Body Factor
Edge current tool– Theory and test structure– Measurement and temperature effect
Conclusions
Sept. 2002 / Firenze / Italy 12ESSDERC ‘02
F.Arnaud and M.Bidaud
RNCE RNCE experimental resultsexperimental results
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
0.1 1 10
Wg (µm)
Vth
/Vth
(w=1
0µm
) ra
tio
RTORTO+RTNRTO+DPNRTO+DPN+AnnealRTN+DPN+Anneal
☹ pure oxide process is the worst option in term of RNCE
☺ oxynitride solutions reduce strongly the Vth-Wg roll down
Sept. 2002 / Firenze / Italy 13ESSDERC ‘02
F.Arnaud and M.Bidaud
Body Body Factor method Factor method descriptiondescription
( )BBSBbthth VKVV Ψ−+Ψ⋅=− .2.20
ox
subscB C
NqK ...2 ε=ox
subsc
ox
BB
Nq
T
KK
εε
ε
.
...2
0
* ==
1.E-12
5.E-06
1.E-05
2.E-05
2.E-05
3.E-05
3.E-05
4.E-05
4.E-05
5.E-05
5.E-05
0 0.2 0.4 0.6 0.8 1 1.2
Vgate (Volt)
Idra
in (A
/µm
)
0.E+00
1.E-04
2.E-04
3.E-04
4.E-04
5.E-04
6.E-04
7.E-04
8.E-04
9.E-04
Gm
(S)
Threshold
current Ith 1.E-06
1.E-05
1.E-04
1.E-03
0 0.05 0.1 0.15 0.2 0.25 0.3
Vgs (Volt)
Id (A
)
Ith
Vth @VBS
Sept. 2002 / Firenze / Italy 14ESSDERC ‘02
F.Arnaud and M.Bidaud
Body Body Factor experimantal resultsFactor experimantal results
Pure oxide process increases the Boron segregation close to STI edge
Agressive nitridation options limit the dopants concentration reduction
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
0.1 1 10
Wg (µm)
Kb* /K
b* (w=1
0µm
) ra
tio
RTORTO+RTNRTO+DPNRTO+DPN+AnnealRTN+DPN+Anneal
Sept. 2002 / Firenze / Italy 15ESSDERC ‘02
F.Arnaud and M.Bidaud
OutlineOutline
IntroductionParasitic effect of gate oxidation stepsExperimental matrix desciptionReverse Narrow Channel Effect (RNCE)– Threshold Voltage– Body Factor
Edge current tool– Theory and test structure– Measurement and temperature effect
Conclusions
Sept. 2002 / Firenze / Italy 16ESSDERC ‘02
F.Arnaud and M.Bidaud
Edge current Edge current extraction extraction methodmethod
Iofftransistor = Ichannel.Wg + nedge.Iedge
Nedge= 2 Nedge= 6 Nedge= 12
Ioff = 0.0519.Nedge + 0.7865R2 = 0.9965
0
0.5
1
1.5
2
2.5
3
3.5
4
0 10 20 30 40 50 60
Nedge (number)
Tota
l Iof
f (nA
)
Slope = edge component
Intercept = channel component
Sept. 2002 / Firenze / Italy 17ESSDERC ‘02
F.Arnaud and M.Bidaud
Edge current experimental resultsEdge current experimental results
0
0.5
1
1.5
2
2.5
3
3.5
4
25°C 50°C 75°C 100°C
Temperature (°C)
I edg
e / I
cha
nnel
rat
ioRTORTO+RTNRTO+DPNRTO+DPN+AnnealRTN+DPN+Anneal
Thanks to a lower Boron segregation inside STI edge parasitic current is reduced by using NO process for gate material
Sept. 2002 / Firenze / Italy 18ESSDERC ‘02
F.Arnaud and M.Bidaud
Edge current and Edge current and T° T° behaviour behaviour (1/2)(1/2)
16
17
18
19
20
21
22
0 0.1 0.2 0.3
Substrate depth (µm)
Dop
ant c
once
ntra
tion
(at/c
m3)
Channel (Boron)SD (Arsenic)
Nj = Junction concentration
Process oxidation modulates the segregation
Segragation modulate Nj
Nj generates a direct tunneling leakage (junction leakage)
Direct tunneling is unsensitive to the temperature
Nj modulates the Off-current
Activation Energy (Ea) of Iedge current is extracted versus T°
More the Ea is high more the segregation is strong
Sept. 2002 / Firenze / Italy 19ESSDERC ‘02
F.Arnaud and M.Bidaud
Edge current and Edge current and T° T° behaviour behaviour (2/2)(2/2)
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
30 32 34 36 38 40
1/Kb.T (1/eV.K)
I edg
e (A
/edg
e)
RTORTO+RTNRTO+DPNRTO+DPN+AnnealRTN+DPN+Anneal
283RTN+DPN+ anneal
384RTO+DPN+ anneal
312RTO+DPN
288RTO+RTN
398RTO
Ea (meV)Process
Higher is the nitridation part
lower is the Ea
and lower is the dopants segregation
Sept. 2002 / Firenze / Italy 20ESSDERC ‘02
F.Arnaud and M.Bidaud
OutlineOutline
IntroductionParasitic effect of gate oxidation stepsExperimental matrix desciptionReverse Narrow Channel Effect (RNCE)– Threshold Voltage– Body Factor
Edge current tool– Theory and test structure– Measurement and temperature effect
Conclusions
Sept. 2002 / Firenze / Italy 21ESSDERC ‘02
F.Arnaud and M.Bidaud
ConclusionsConclusions
The strong interest of oxynitride process (Rapid Thermal Nitridation and Decoupled PlasmaNintridation) to reduce RNCE has been demonstratedBoth Vth-Wg roll down and parasitic edge current have been decreasedBody Factor method and T° measurement put in evidence the role of NO-gas during gate oxidation stepsNitridation option is a safety solution for SRAM cell leakage control, especially for Low Power Applications