Corso di Laurea in Fisica
Design of CMOS logic gates
tolerant of single-event effects for
extreme radiation environments
Relatore interno: Prof. Valentino Liberali
Relatore esterno: Dott. Alberto Stabile
Tesi di laurea di:
Luca Frontini
Matr. n. 809009
Codice PACS: 85.40.-e
Anno Accademico 2013 - 2014
Contents
1 Introduction 7
1.1 Radiation hardening approach for CMOS logic . . . . . . . . . 9
2 Radiation effects on ICs 11
2.1 Interaction between particles and semiconductor . . . . . . . . 11
2.1.1 Ionization . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2 Ionization Effect categories . . . . . . . . . . . . . . . . 13
2.1.3 Displacement phenomenon . . . . . . . . . . . . . . . . 13
2.2 Radiation effects on ICs . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Hardening with respect to TID effects . . . . . . . . . 16
2.2.2 Hardening with respect to SEE effects . . . . . . . . . 18
3 D2RA:Double-Rail Redundant Approach 23
3.1 Properties and constraints . . . . . . . . . . . . . . . . . . . . 23
3.1.1 Logic constraints . . . . . . . . . . . . . . . . . . . . . 24
3.1.2 n-input generalization . . . . . . . . . . . . . . . . . . 25
3.2 Correctness and Minimality . . . . . . . . . . . . . . . . . . . 27
3.2.1 Correctness . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.2 Minimality . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Implementation examples . . . . . . . . . . . . . . . . . . . . 29
3.3.1 2-input AND-NAND . . . . . . . . . . . . . . . . . . . 29
3.3.2 3-input gate . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 Software implementation . . . . . . . . . . . . . . . . . . . . . 39
4 Rad Hard Layout of the D2RA cells 43
4.1 Technology node choice . . . . . . . . . . . . . . . . . . . . . . 43
4.1.1 Total Ionizing Dose effect solution . . . . . . . . . . . . 44
4.1.2 Single Event Effect solutions . . . . . . . . . . . . . . . 44
3
4 CONTENTS
4.2 Logic cells circuits . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.1 AND-NAND and OR-NOR . . . . . . . . . . . . . . . 47
4.2.2 XOR-XNOR . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3 D2RA flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.1 Master-slave edge-triggered D-FF . . . . . . . . . . . . 50
4.3.2 Clock edge detector . . . . . . . . . . . . . . . . . . . . 55
4.3.3 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.4 Complete FF circuit . . . . . . . . . . . . . . . . . . . 57
5 Simulations 59
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2 Modelling single event mechanisms
(state-of-the-art) . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.2.1 Physic based models . . . . . . . . . . . . . . . . . . . 60
5.2.2 Device simulations . . . . . . . . . . . . . . . . . . . . 60
5.2.3 Standard injection model . . . . . . . . . . . . . . . . . 61
5.3 Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.1 The FISAR approach . . . . . . . . . . . . . . . . . . . 63
5.3.2 Calculation of charge collected within each box . . . . 66
5.3.3 Calculation of charge collected by circuit nodes . . . . 67
5.3.4 Circuit simulations . . . . . . . . . . . . . . . . . . . . 67
5.3.5 p-n junction capacitance calculation . . . . . . . . . . . 68
5.3.6 p-diffusion an n-diffusion calculation . . . . . . . . . . 69
5.4 SKILL integration of FISAR simulation . . . . . . . . . . . . . 70
5.4.1 Preliminary geometry exaction . . . . . . . . . . . . . . 70
5.4.2 Area and perimeter calculation . . . . . . . . . . . . . 72
5.4.3 Net name association . . . . . . . . . . . . . . . . . . . 72
5.4.4 Capacity calculation . . . . . . . . . . . . . . . . . . . 73
5.5 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.6 Sensitivity maps . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6 Test structures 79
6.1 AND-NAND and XOR-NXOR tree . . . . . . . . . . . . . . . 79
6.2 Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7 Conclusions 85
7.1 Further development . . . . . . . . . . . . . . . . . . . . . . . 86
CONTENTS 5
Bibliography 87
6 CONTENTS
Chapter 1
Introduction
Microelectronic design techniques in last years had a great evolution which
leads to component size reduction and performance improvement. However
in high energy physics applications newer technologies aren’t immediately
applicable [1]: the presence of a great amount of ionizing particles requires
the adoption of special circuit design.
The success of many experiments in high energy physics demonstrates the
importance of high performance pixel tracking. However, future experiments
will pose major challenges for the detectors: higher pixel density, more complex
logic for triggering and on-chip data analysis, lower power consumption and
higher bandwidth. Requirements for future high energy physics experiments
present multiple challenges in the design of pixel detectors. The first example
is the A Toroidal LHC ApparatuS (ATLAS) and Compact Muon Solenoid
(CMS) upgrades for High Luminosity Large Hadron Collider (HL-LHC). A
summary of the main specifications can be found in Table 1.1.
Table 1.1: Specifications for ATLAS and CMS phase 2 pixel. detectors.
Parameter Value
Particle flux 500MHz cm−2
Pixel hit rate 2GHz cm−2
Readout rate 1MHz
Total single chip Bandwidth 4Gbit/s
Pixel size ≈50µm× 50µmTotal Radiation Dose 10MGy
7
8 CHAPTER 1. INTRODUCTION
Figure 1.1: Radiation hardness classification.
Design of electronics components for physics experiments must be different
from consumer electronics; radiation hardness of electronic systems and
components must be improved.
Radiation hardness can be obtained by modifying in a suitable way
the fabrication process (“Radiation Hardening By Process” - RHBP) or by
designing electronic circuits with a dedicate approach to achieve tolerance to
radiation (“Radiation Hardening By Design” - RHBD). This thesis work is
focused on the second solution.
RHBD at system level
At system level, radiation hardness may consist in software algorithms that
are able to extract correct data from redundant information. To this end, it
is necessary to design redundant electronic systems.
1.1. RADIATION HARDENING APPROACH FOR CMOS LOGIC 9
RHBD at architectural level
At architectural level, Error Correcting Code (ECC) circuitry can be added to
increase the correcting capability of devices. In addition, placement strategies
(Section 4.1.2) can be adopted to mitigate radiation effects. As a single
collision event can affects several bits or logic cells, a common solution
consists in unlinking physical position from logical position. In this way,
radiations effects are logically de-localized, and radiation hardness increases.
RHBD at circuit level
At circuit level, some structures are avoided or significantly reduced. Com-
monly, feedback loops with high gain level are minimized. In addition, suitable
design are used to design more robust circuits.
RHBD at layout level
During the design of the layout, several solutions can be adopted to mitigate
or eliminate damaging effects due to radiation: physical separation, guard
rings, etc.
1.1 Radiation hardening approach for CMOS
logic
This thesis work proposes a new Complementary Metal Oxide Semiconductor
(CMOS) logic family, based on a Double-Rail Redundant Approach, that is
called D2RA. A standard approach to develop rad-hard logic cell consist in
using redundancy and triplication of structures and cells. This approach leads
at least to a triplication of layout area with subsequent increase of chip cost
and power consumption.
This thesis proposes an alternative approach: instead of redundancy of
non rad-hard logic structures, a new logic synthesis method is developed to
design logic cells that propagates both the bit and the inverted one. With this
feature it is possible to know if the radiation causes a change of the bit value
and to stop the propagation of the affected bit. Circuit schematic and layout
have been designed using RHBD approach. A layout-oriented simulation
analysis has been used to validate the designs. Finally, test structures have
been designed, to be included in a multi-project wafer prototype.
10 CHAPTER 1. INTRODUCTION
Chapter 2
Radiation effects on ICs
2.1 Interaction between particles and semi-
conductor
When a particle hits a semiconductor, two main phenomena may occur:
ionization and displacement. Interaction between the semiconductor material
and charged particles is based on Coulomb law and may produce the ionization
of semiconductor material. The ionization phenomenon may generate free
carriers which can drift and diffuse. In some cases, some free carriers can
remain trapped in semiconductor lattice defects. Trapped particles can be
seen as a permanent charge affecting the density distribution of carriers.
Particles may also interact mechanically with the semiconductor material
displacing atoms from their original position to an interstitial position. Lattice
defects change the electrical parameters of the material.
Figure 2.1: (a) HEP creation by ionization effect; (b) HEP separation in a
region enveloped in an electric field.
11
12 CHAPTER 2. RADIATION EFFECTS ON ICS
2.1.1 Ionization
When a particle loses energy via ionization, an electron in the valence band
may acquire enough energy to pass in the conduction band. Thus, a new
electron is present in the conduction band and a new hole in the valence band.
Overall, radiation ionization phenomenon can generate a new Hole-Electron
Pair (HEP). Figure 2.1 shows this phenomenon.
If an electric field exists (e.g., in biased devices), HEPs can be separated
and free carriers move in the semiconductor introducing extra (parasitic)
currents. Successively, carriers can recombine, remain trapped or drift to an
electrode.
There are several particles that can ionize a semiconductor:
• Photons: X and γ rays interact with the material in three different
ways: by photoelectric effect, by Compton scattering or by pair produc-
tion. γ rays are produced by 60Co (Cobalt-60) sources and are a useful
way to make an accelerated test, i.e., to predict interactions with the
radiation for a long period of time (e.g., 10 years) in fews days. X-ray
sources are also used for laboratory tests.
• Neutrons are neutral particles and their interaction with a semicon-
ductor can create: nuclear reaction (the incident neutron is absorbed by
the nucleus which emits other particles (protons, α particles, γ photons)
or an-elastic collisions: there is excitation of the nucleus, which decays,
emitting γ rays [2].
• Protons and electrons are charged particles and ionization can be
induced by means of Coulomb interaction.
• Heavy ions are charged particles with a high atomic number and
ionization can be induced by means of Coulomb interaction.
The energy lost by ionization per unit mass is measured by means of the
Linear Energy Transfer (LET) coefficient. The LET indicates the quantity of
energy lost by ionization and by the incident particle along its path into the
target material. The LET depends on atomic number, on the energy of the
particle and on target material:
LET =dE
ρ · dx
[MeV · cm
2
mg
](2.1)
2.1. INTERACTION BETWEEN PARTICLES AND SEMICONDUCTOR13
where ρ is the density of the target material, and dEdx
indicates the average
energy transferred into the target material per length unit along the particle
trajectory. To estimate the number Cnum of HEP generated, it is necessary
to integrate the LET coefficient:
Etotlost =
∫dE
ρ · dxdx
[MeV · cm
3
mg
](2.2)
and to divide Etotlost by Em, which is the experimental average energy neces-
sary to create one HEP, and is equal to:
• in silicon: Em = 3.6 eV
• in oxide (SiO2): Em = 17 eV
Cnum =Etotlost
Em
(2.3)
From the number of HEP generated, it is possible to calculate the total charge
deposited. For instance, in silicon, a LET of 97MeV cm2/mg corresponds
to a charge deposited of 1 pC/µm. All these assumptions are valid for short
paths [3].
2.1.2 Ionization Effect categories
Ionization effects can be divided into two main categories:
• Temporary ionization effects due to HEP separation and generation of
a parasitic current;
• Permanent ionization effects due to HEP trapped in insulators. Inside
an insulator, the number of carriers due to radiation is smaller than
in semiconductors. Therefore, parasitic currents can be neglected.
However, insulators contain a large number of trapping centres, which
trap carriers generated by radiation. The permanently trapped charges
introduce a shift in device parameters.
2.1.3 Displacement phenomenon
When a particle collides with an atom of the silicon lattice, it may generate
the displacement effect. If the energy transferred from the particle to the
14 CHAPTER 2. RADIATION EFFECTS ON ICS
Figure 2.2: Displacement effect: 1) a particle collides with a silicon atom;
2) the displaced atom hits another atom; 3) two atoms move towards an
interstitial position and two vacancies remain.
silicon it is greater then 20 eV, the particle can displace an atom, which
moves towards an interstitial position (Figure 2.2), and can displace other
atoms along its trajectory. As an example, a neutron at 1MeV transfers
70 keV to a silicon lattice atom, which displaces approximately 100 other
atoms over a length of 100 nm. This phenomenon may produce some lattice
defects which act as energy levels in the band-gap. These levels alter the
semiconductor electric properties (e.g., life time of minority carriers, doping
density, mobility, etc.). As the probability of carrier transition between the
two bands depends exponentially on the band-gap energy, levels in the band-
gap increase generation and recombination. Consequently, the recombination
probability increases. Overall, the displacement phenomenon introduces two
damaging effects (Figure 2.3):
• Generation is dominant in depleted regions of p-n junctions, where it
causes inverse current;
• Recombination is dominant in forward-biased p-n junctions, where it
reduces charge flux.
2.2. RADIATION EFFECTS ON ICS 15
Figure 2.3: Displacement damaging effects: (a) generation effect; (b) recom-
bination effect.
2.2 Radiation effects on ICs
The previous Section described the main radiation effects in a generic semi-
conductor or oxide. This section presents damaging effects which occur in
ICs. Radiation effects can be divided in two major categories:
• Cumulative effects, due to a long-time exposure to radiation;
• Single Event Effects (SEE), due to interaction with a single particle.
Cumulative effects can be divided into Total Ionizing Dose (TID) ef-
fects, and Displacement Damage Dose (DDD) effects. TID effects are due
to electron-hole pairs generated in the oxide layer by the radiation crossing
the integrated circuit. Electrons quickly flow towards electrodes while holes
remain trapped within the oxide for a long time [4], [5]. Furthermore, chan-
nel carriers can be trapped at the Si-SiO2 interface [6], [7]. These effects
cause variations in transistor parameters, such as increase or decrease of
threshold voltage, increase of parasitic currents, decrease of carrier mobility
and transconductance. DDD effects are due to collisions between particles
and nuclei of silicon belonging to the lattice structure [8]. These collisions
may create defects into the silicon lattice, introducing energy states in the
band-gap. These trap states facilitate electron transitions between valence
band and conduction band, and a mobility degradation is observed [6]-[9].
Single event effects (SEE) can be divided into two categories. Soft
errors are non-destructive and transient effects: for instance, bit flips occurring
as a consequence of a Single Event Upset (SEU), or Single Event Transient
16 CHAPTER 2. RADIATION EFFECTS ON ICS
(SET). Hard errors are destructive, i.e., they cause irreversible effects (e.g.,
Single Event Gate Rupture: SEGR).
2.2.1 Hardening with respect to TID effects
In CMOS integrated circuits, the region most sensitive to cumulative effects
is the oxide. When a single particle interacts with the MOS oxide layers,
HEPs are created. The number of pairs generated is proportional to the
particle LET. A fraction of the radiation-induced HEPs recombines after
being generated. The HEPs which do not recombine are separated by the
electric field in the oxide. Electrons are quickly collected by electrodes because
their mobility is approximately 20 cm2 V−1 s−1, while holes move slowly by
hopping transport towards Si-SiO2 interface, because their mobility ranges
from 10× 10−4 cm2 V−1 s−1 to 10× 10−11 cm2 V−1 s−1 and depends strongly
on the temperature and on the electric field. Part of these holes remains
trapped into the oxide for a long time. The trapped holes can be seen as
permanent positive charges. In a MOS transistor, the permanent positive
charges introduce a negative shift in threshold voltage:
∆VOT = − q
Cox
∆NOT = − q
εoxtox∆Not (2.4)
where ∆VOT is the threshold voltage shift due to holes trapped into the oxide,
q is the elementary charge, Cox = toxεox
is the oxide capacitance per unit area,
NOT is the effective density of trapped holes, εox is the dielectric constant of
the oxide, tox is the oxide thickness.
At low temperature (80K) the threshold shift is due only to the holes
trapped in the gate oxide. Saks et al. [10] showed that for oxide layers thicker
than 30 nm, ∆VOT is proportional to tox according to the results obtained by
Boesch and McGarrity [11]. On the contrary, for oxide thickness lower than
approximately 30 nm, ∆VOT is shown in Figure 2.4 as a function of tox. For
thin gate oxide (e.g, for thickness lower than approximately 3 nm), threshold
shift is negligible. Similar results were obtained at room temperature [12].
Defects at the Si–SiO2 interface introduce energy states in the band-gap,
which may trap channel carriers. Threshold voltage shift depends on device
biasing. For n-channel transistors the Fermi level in the silicon at the Si–SiO2
interface lies between Einterface and Econduction, hence, the acceptor-like traps
which are below the Fermi level will be negatively charged, and then the
2.2. RADIATION EFFECTS ON ICS 17
Figure 2.4: Threshold voltage shift ∆VOT as function of the oxide thick-
ness: experimental data are obtained at 80K with an electric field of
2MV cm−1 [10].
threshold voltage shift will be positive. Similarly, for a p-channel transistor,
the threshold voltage shift will be negative.
∆VIT = −QIT
COX
(2.5)
where QIT is the density of charge trapped at interface. Figure 2.5 shows
the energy band diagram for a nMOS transistor with a positive bias at the
gate: electrons quickly flow towards the gate and the holes move by hopping
in proximity of the Si-SiO2 interface, where they remain trapped. Figure 2.5
also shows negative carriers trapped at the Si-SiO2 interface. Overall, for
nMOS transistors, the threshold voltage shift depends on absorbed dose. In
some cases, for low dose the threshold voltage shift is caused mainly by holes
trapped into the oxide (∆VOT ), whereas for high dose the threshold voltage
shift is caused mainly by charges trapped at interface (∆VIT ). For pMOS
transistors, the threshold shift is always negative. The total voltage threshold
18 CHAPTER 2. RADIATION EFFECTS ON ICS
Figure 2.5: Trapped particles in silicon oxide and at Si–SiO2 interface [2].
shift is equal to:
∆VT = ∆VOT +∆VIT = −QOT
Cox
− QIT
Cox
(2.6)
Figure 2.6 shows a qualitative example of a threshold voltage shift caused by
radiation.
2.2.2 Hardening with respect to SEE effects
Starting from the seventies, Single Event Effects (SEE) have been careful
studied [13], [14], [15], [16], [17], [18], [19], [20]. Nowadays, many efforts
have been made to improve SEE immunity, especially for mission critical
applications. In last years, technology progress has lead to an increase in
performance and a decrease in area of silicon. However for some electronic
devices, the number of ionized nodes by a single particle increases with
the increasing of device density and the decreasing of transistor area. In
addition, as the scale of integration increases, the amount of stored charge
representing a bit of information decreases, and information loss due to
cell interaction with a single ionizing particle increases; particles with lower
ionizing power (i.e., lower atomic number) become capable of changing cell
logic states [20]. For this reason, digital circuits built in new deep sub-micron
technologies are more sensitive to radiation and require accurate studies to
have a sufficient level of radiation hardness to SEE. Currently, SEEs have
been studied also for terrestrial applications, as recent studies demonstrate
that sea-level applications exhibit failures due to SEEs [21].
2.2. RADIATION EFFECTS ON ICS 19
210
Vth
0V
thT
hre
shold
var
iati
on,
/ |
|
310
410
0
2
1
−1
−2
n−MOS
p−MOS
Dose [Gy]
off
on
on
off
Figure 2.6: Example of a threshold voltage shift in nMOS and pMOS. tran-
sistors.
When a high LET particle strikes into a sensitive node, it generates a
parasitic charge due to the ionization phenomenon. If this charge is larger
than the critical charge required to trigger an abnormal behavior, a SEE
may be seen, which affects the electrical performance of the circuit.
When a ionized particle crosses a p-n junction, it creates a region of HEPs
(Figure 2.7(a)). We have seen in the previous section that the number of
HEPs is proportional to the LET. If the p-n junction is reverse biased, HEPs
are separated. When the number of carriers is very large, a depletion region
deformation called “funnel” is produced. (Figure 2.7(b)). Charges in the
“funnel” region are collected, generating a high intensity current with a short
duration time of approximately 10 ps. After that, the depletion region returns
in pre-collision state, and extra charges move by diffusion (Figure 2.7(c)). This
phenomenon produces a diffusion current with long duration time (≈300 ns)
and low intensity.
Sensitivity versus SEE in any particular device is evaluated by measuring
the corresponding cross section vs LET.
20 CHAPTER 2. RADIATION EFFECTS ON ICS
+ − + −− + − ++ − + −− + − ++ − + −− + − ++ − + −− + − ++ − + −− + − ++ − + −− + − ++ − + −− + − ++ − + −− + − ++ − + −− + − ++ − + −− + − +p−substrate p−substrate p−substrate
n+ n+n+
+ − + −− + − ++ − + −
++++
+
++
+++++
+
+++++
+
+++
++
+
+
+
+ +
−−−
−
−−−
−−−−−−
−−−−
−−−−−−−
−− − −−
− −−−
− −−
−−
−
−−
−
+
++
+
++
+
+ +++
+
+
++
ion track diffusion currentdrift current
(a) (b) (c)
Figure 2.7: (a) hole-electron pair generation due to a high-energy particle
strikes in a p-n junction; (b) depletion region deformation and hole-electron
separation (spike current due to drift); (c) diffusion current.
σ =NSEE
Φ(2.7)
where Φ is the cross section, NSEE is the number of single events and Φ
is the uniform fluence over some fiducial area. Usually, the cross section
is normalized with respect to the number of bits: σ is expressed in square
centimeters per bit (cm2/ bit). The error prediction rate can be derived by
the cross section and some others parameters like the mission duration and
the nature of particle. Figure 2.8 shows a qualitative example of cross section
vs. LET. The threshold LET (LETth ) is defined as the maximum LET value
at which no effect is observed at a fluence of 1× 107 particles/cm2.
The asymptotic cross section saturation is the value of σ approached at
high LET values. The curve of σ as function of the LET is obtained by
measuring the cross section at a few LET values and fitting the data with a
Weibull curve:
σ(LET ) = σsaturation
[1− e
(−LET−LETth
W
)S]
(2.8)
where W and S are fitting parameters [22].
2.2. RADIATION EFFECTS ON ICS 21
Figure 2.8: Cross section qualitative example. LETth indicates the minimum
level of LET which triggers a SEE.
22 CHAPTER 2. RADIATION EFFECTS ON ICS
Chapter 3
D2RA:Double-Rail Redundant
Approach
This chapter presents a new logic family designed using a Double-Rail Re-
dundant Approach (D2RA) to develop radiation hardened logic cells.
The first part analyses the logic constraints and the operation principle of
the circuit. Then a synthesis method is proposed to match the constraints
and to design D2RA logic cells in a fully-CMOS technology. This method is
implemented in a software that performs the minimization of the transistor
number for two and three input logic functions.
The second part explains the circuit schematic of all non trivial input
logic functions and of a flip-flop. The layout is designed in the Taiwan
Semiconductor Manufacturing Company (TSMC) 65 nm technology, according
to a standard cell design approach.
3.1 Properties and constraints
To achieve a good resistance to SEU, the propagation of a SET has to be
prevented from propagating across other parts of the circuit. For this purpose
an indicator is introduced that controls if an error has occurred.
To discriminate between correct and incorrect data, the same logic infor-
mation, i.e., bit and inverted bit, is stored in two different nets. If a SET
occurs, the bit and the inverted bit will assume the same logic value: 00 or
11. This indicates that the data is not valid. If a SET occurs, the data is not
valid, and the flip-flop at the end of the logic data path stops the signal. In
23
24 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
Figure 3.1: Example of a logic data path, with a SET propagation stopped by the flip-flop.
this way, a SET propagation will not trigger a SEU.
With this approach, a conventional two input standard cell will have four
input pins (A, B, C, D) and two output pins (Y , Z): normally, bit B is the
complement of A, bit D is the complement of C, and bit Z is the complement
of Y . Figure 3.1 shows an example of a D2RA logic chain.
Because of the two complementary output bit, there is no need of an
inverter and the inverted function can be obtained just by exchanging the
two outputs.
3.1.1 Logic constraints
The circuit is implemented in fully-CMOS technology, with a pull-up made
of PMOS transistors and a pull-down made of NMOS transistors, so the 0000
input combination must give 11 at the outputs, and similarly the 1111 input
must give 00 at the outputs. Invalid input data must produce two outputs
(Y and Z) with the same logic value (00 or 11).
The above listed constraints are summarized in the Karnaugh maps [23]
shown in Figure 3.2:
• correct points correspond to the set of input valid data, and must have
different output logic values (01 or 10);
• “gravity points” correspond to 0000 and 1111 at inputs, and they give
11 and 00 at the outputs;
• the other faulty points that correspond to the set of invalid data different
3.1. PROPERTIES AND CONSTRAINTS 25
AB
CD00 01 11 10
00
01
11
10
1 - --
- 0 0-
- 0 1-
- - -0
(a) AND
AB
CD00 01 11 10
00
01
11
10
1 - --
- 1 1-
- 1 0-
- - -0
(b) NAND
Figure 3.2: Karnaugh map of the D2RA AND-NAND function: the map on
left synthesize Z output, the right one Y .
x3x4
x1x2 00 01 11 10
00
01
11
10
1 1 1-
1 0 00
1 0 10
- 0 00
(a) AND
x3x4
x1x2 00 01 11 10
00
01
11
10
1 1 1-
1 1 10
1 1 00
- 0 00
(b) NAND
Figure 3.3: Filled Karnaugh map of the D2RA AND-NAND function.
from 0000 and 1111 are represented by don’t cares (-), which can be
either 0 or 1, provided that they assume the same value in both maps.
With the constraints defined above, each correct point can be covered
with a cube containing one of the gravity points, as shown in Figure 3.3.
3.1.2 n-input generalization
A generalization to n-input functions can be done. A change of notation is
needed: let {0, 1}2n be the Boolean space with input variables x1, x2, ..., x2n
and output f and f .
For the cell synthesis problem, let us consider adjacent pairs of variables.
26 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
Indeed, the meaningful points are the ones such that xi �= xi+1 for each odd
i ∈ {x1, x2, ..., x2n}. These points are called correct points. The set C ⊂{0, 1}2n is the set of correct points in {0, 1}2n. All points in F = {0, 1}2n \Care called faulty points. For example, in the Boolean space {0, 1}8 while the
point 01011010 is correct, the point 01110001 is faulty.
In the Boolean space {0, 1}2n there are two special faulty points, called
gravity points, such that each cube of the final cover contains exactly one of
them. These two points are 0 = 00...0 and 1 = 11...1.
Recall that a generic cell represents a Boolean function f : {0, 1}2n →{0, 1, -}, indeed, the cell outputs two values: f and its complement f . In
particular, the values of f and f , are defined on both correct and gravity
points. If v is a correct point we have that f(v) = 1− f(v) ∈ {0, 1}. Moreover,
by logic constraints, f(0) = f(0) = 1 and f(1) = f(1) = 0. For any other
faulty point v we have that f(v) = f(v) = -. For example, consider the
Karmaugh maps for the AND-NAND port depicted in Figure 3.3. The
corresponding functions are f and f such that: f(0101) = 0, f(0110) = 0,
f(1001) = 0, f(1010) = 1, and f(0101) = 1, f(0110) = 1, f(1001) = 1,
f(1010) = 0. Moreover, f(0000) = f(0000) = 1, f(1111) = f(1111) = 0, and
f(v) = f(v) = - for any other faulty point v.
In the synthesis process, we must obtain two covers, Cf and Cf , such that
for each correct point v we have Cf (v) = 1− Cf (v) and for each faulty point
u we have Cf (u) = Cf (u).
Let v = v1v2...v2n be a correct point; recalling that vi is the value of
variable xi in the point v, if f(v) = 0 then the product pv,f =∏
i|vi=1 xi, else
if f(v) = 1 then the product pv,f =∏
i|vi=0 xi.
For example, consider the correct point v = 0110010110. If f(v) = 0 then
pv,f = x2x3x6x8x9 and the corresponding cube is -11--1-11-. If f(v) = 1 then
pv,f = x1x4x5x7x10 and the corresponding cube is 0--00-0--0.
As we can note from the above example, a product pv,f always corresponds
to a cube containing {-, 1} or {-, 0} only. Moreover, for each couple of variables
xi, xi+1 ,when i is an odd number, one variable is equal to 0 or 1, and the
other variable is equal to -.
We can now define the covers Cf and Cf of the functions f and f describing
a general n-input cell. Cf (resp., Cf ) contains the products pv,f (resp., pv,f )
covering all the correct points v. The faulty points not covered by any pv,f or
pv,f are set to 0 and are covered in an optimal way.
For instance, consider again the AND-NAND port represented in Figure 3.2.
3.2. CORRECTNESS AND MINIMALITY 27
x3x4
x1x2 00 01 11 10
00
01
11
10
1
0
(a) AND
x3x4
x1x2 00 01 11 10
00
01
11
10
1
0
(b) NAND
Figure 3.4: Neighborhoods of the two gravity points 1 (a) and 0 (b).
The cover Cf must contain a product for each correct point, i.e., p0101,f = x2x4,
p0110,f = x2x3, p1001,f = x1x4, and p1010,f = x2x4, as shown in Figure 3.3.
3.2 Correctness and Minimality
These two properties are necessary to build a functional logic and to minimize
the number of transistors. Indeed, correctness ensures that all don’t care
have a unique value (0 or 1) and minimality ensures that the produced covers
are the most compact in the number of products and literals. The following
sections present the main theorems, whose demonstration is given in [24].
3.2.1 Correctness
We first observe that, by the definition of pv,f , the dimension of pv,f is n
since v is a correct point and contains exactly n 0’s and n 1’s. We can also
note that pv,f cannot contain at the same time both 0 and 1. This simply
derives from the fact that the only cube containing both 0 and 1 is the entire
Boolean space of dimension 2n, while any pv,f has dimension n.
Let g = gg...g be a gravity point. The neighborhood Ng of g is:
Ng = {v1...v2n|∀ odd i ∈ {1, ..., 2n}(vi = g) ∨ (vi+1 = g)}
For example, Figure 3.4 shows the neighborhoods of the two gravity points
0 and 1 in {0, 1}4. The following lemma proves some properties of pv,f1. In
1Note that, since f is a Boolean function, all properties shown for f hold also for f .
28 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
particular, each product pv,f contains only one correct point, and it is entirely
contained in the neighborhood of 0 or 1.
Lemma 1. Let v = v1v2...v2n be a correct point in {0, 1}2n, and let f be a
function such that f(v) = c ∈ {0, 1}. Thus, we have that:
1. The product pv,f \ v ⊂ F.
2. If f(v) = 0 then pv,f ⊂ N1.
3. If f(v) = 1 then pv,f ⊂ N0.
The following lemma shows that the intersection of N0 and N1 is the set of
correct points C, i.e., C is a sort of border line between the two neighborhoods.
Lemma 2. N0 ∩N1 = C.
The following two lemmas are crucial for proving the correctness of the
proposed synthesis method. In practice, the lemmas show that any product,
pv,f or pu,f , covering a faulty point u (different from 0 or 1) must contain the
same gravity point g. This means that g is the value of u in both covers Cf
and Cf .
Lemma 3. Let v and v′ be two different correct points such that f(v) = 1
and f(v′) = 0, then pv,f ∩ pv′,f = ∅.
Lemma 4. Let v and v′ be two different correct points such that f(v) �= f(v′),
then pv,f ∩ pv′,f = ∅.
Finally, we can show the correctness Theorem, which states that, in the
propose covers, all correct points are covered and any faulty point has a
unique value (0 or 1).
Theorem 1. Let f be a Boolean function, and let Cf and Cf be the covers
of f and f . The following properties hold:
1. Each correct point v is covered by Cf and by Cf .
2. Let u be a faulty point that is covered by a cube pv,f (or pv, f ) in Cf
(resp., Cf), each other cube, pv′,f or pv′,f , that covers u (if any) is such
that f(v) = f(v′) = f(v) = f(v′).
Note that, by definition of Cf and Cf , the faulty points that are not
covered by any products pv, f or pv,f have value 0, and are covered in a
minimal way.
3.3. IMPLEMENTATION EXAMPLES 29
3.2.2 Minimality
We now show that any cube pv,f (resp., pv,f ) of the proposed cover Cf (resp.,
Cf) cannot be further enlarged. Consider, for example, the correct point
v = 10011010 such that f(v) = 1 and thus f(v) = 0. We have that the cube
corresponding to pv,f is -00--0-0 and the the cube corresponding to pv,f is
1--11-1-. If we try to expand 1--11-1- then we have to substitute a 1 with
a - and we obtain, e.g., ---11-1-. The obtained product ---11-1- and -00--0-0
overlap in 00011010, i.e., 00011010 is already covered by the cube -00--0-0
in Cf and it has value 1. Thus, 00011010 cannot have value 0 in Cf since
it is a faulty point (faulty points must have the same value in both Cf and
Cf ). Therefore, we cannot further expand 1--11-1-. This example give us the
intuition for the following proposition.
Proposition 1 (Minimal form). Cf and Cf are minimal, i.e., we cannot
cover any correct point v with a cube greater than pv,f or pv,f .
Indeed, the two cover Cf and Cf are the most compact in the number of
product and literal.
Theorem 2 (Minimum Form). Cf and Cf are minimum covers.
3.3 Implementation examples
The next sections present some examples of logic synthesis and implementation
in CMOS technology.
3.3.1 2-input AND-NAND
Figure 3.5 shows the Karnaugh map of the AND-NAND logic function filled
with don’t care that at the end will be 1 or 0 in both Y and Z maps output.
The truth table is shown in Table 3.1.
1. The fully-CMOS technology is an inverting logic, therefore 0000 input
must give 1 and 1111 gives 0 in both Karnaugh maps (Figure 3.6).
These elements are called gravity points.
2. For both gravity points are we find the square covers that include
neighborhood, as shown in Figure 3.7.
30 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
AB
CD00 01 11 10
00
01
11
10
- - --
- 0 0-
- 0 1-
- - --
(a) AND - Z output
AB
CD00 01 11 10
00
01
11
10
- - --
- 1 1-
- 1 0-
- - --
(b) NAND - Y output
Figure 3.5: Karnaugh map with the correct points of the D2RA AND-NAND
function.
Table 3.1: Truth table of the AND-NAND port before and after synthesis.
A B C D Z Y
0 0 0 0 - -
0 0 0 1 - -
0 0 1 0 - -
0 0 1 1 - -
0 1 0 0 - -
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 - -
1 0 0 0 - -
1 0 0 1 0 1
1 0 1 0 1 0
1 0 1 1 - -
1 1 0 0 - -
1 1 0 1 - -
1 1 1 0 - -
1 1 1 1 - -
A B C D Z Y
0 0 0 0 1 1
0 0 0 1 1 1
0 0 1 0 1 1
0 0 1 1 - -
0 1 0 0 1 1
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 0 0
1 0 0 0 0 0
1 0 0 1 0 1
1 0 1 0 1 0
1 0 1 1 0 0
1 1 0 0 - -
1 1 0 1 0 0
1 1 1 0 0 0
1 1 1 1 0 0
3.3. IMPLEMENTATION EXAMPLES 31
AB
CD00 01 11 10
00
01
11
10
1 - --
- 0 0-
- 0 1-
- - -0
(a) AND - Z output
AB
CD00 01 11 10
00
01
11
10
1 - --
- 1 1-
- 1 0-
- - -0
(b) NAND - Y output
Figure 3.6: Karnaugh map of the D2RA AND-NAND function with gravity
points in blue, and correct inputs in red.
AB
CD00 01 11 10
00
01
11
10
1 - --
- 0 0-
- 0 1-
- - -0
(a) AND - Z output
AB
CD00 01 11 10
00
01
11
10
1 - --
- 1 1-
- 1 0-
- - -0
(b) NAND - Y output
Figure 3.7: Karnaugh map of the D2RA AND-NAND function with covers.
32 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
AB
CD00 01 11 10
00
01
11
10
1 1 1-
1 0 00
1 0 10
- 0 00
(a) AND - Z output
AB
CD00 01 11 10
00
01
11
10
1 1 1-
1 1 10
1 1 00
- 0 00
(b) NAND - Y output
Figure 3.8: Filled Karnaugh map of the D2RA AND-NAND port.
3. Each cover is filled with 0 or 1. Covers that include 1 are filled with
1 because there is a majority of ones and covers that include 0 with
0 because there is a majority of zeros. The filled map is shown in
Figure 3.8.
4. Remaining don’t care have to be filled, in this case nothing change if
are filled both with 0 or 1. In this example, they are filled with ones.
5. Now that all don’t cares are filled, we have to find minimum covers and
synthesize the circuit: all covers are shown in Figures 3.9 and 3.10. The
corresponding literal expressions are:
Y = AC + BCD + ABD = BD(A+ C) + AC (3.1a)
Y = AB + CD + AC + BC + AD = (A+ C)(B + D) (3.1b)
Z = BD + BC + AD = B(C +D) + AD (3.2a)
Z = CD + AB + BD = B(A+ D) + CD (3.2b)
The two circuits built from these expressions are shown in Figure 3.11.
3.3.2 3-input gate
Now we extend the example presented in the previous paragraph to the three
input AND-NAND logic gate.
3.3. IMPLEMENTATION EXAMPLES 33
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 0 00
1 0 10
1 0 00
(a) AND - Z output
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 1 10
1 1 00
1 0 00
(b) NAND - Y output
Figure 3.9: One covers of the D2RA AND-NAND function.
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 0 00
1 0 10
1 0 00
(a) AND - Z output
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 1 10
1 1 00
1 0 00
(b) NAND - Y output
Figure 3.10: Zero coves of the D2RA AND-NAND function.
A D D
CB
Z
A
D
B
C D
D B C
A C A
Y
B
D
C
A
C A
Figure 3.11: Schematic of the D2RA AND-NAND cell: Z output (left) and Y output
(right).
34 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
AB
CD00 01 11 10
00
01
11
10
1 - --
- - --
- - --
- - --
EF
=
00
AB
CD00 01 11 10
00
01
11
10
1 - --
- - --
- - --
- - --
AB
CD00 01 11 10
00
01
11
10
- - --
- 0 0-
- 0 0-
- - --
EF
=
01
AB
CD00 01 11 10
00
01
11
10
- - --
- 1 1-
- 1 1-
- - --
AB
CD00 01 11 10
00
01
11
10
- - --
- - --
- - --
- - -0
EF
=
11
AB
CD00 01 11 10
00
01
11
10
- - --
- - --
- - --
- - -0
AB
CD00 01 11 10
00
01
11
10
- - --
- 0 0-
- 0 1-
- - --
(a) NAND - Y
EF
=
10
AB
CD00 01 11 10
00
01
11
10
- - --
- 1 1-
- 1 0-
- - --
(b) AND - Z
Figure 3.12: Karnaugh map of the three input D2RA AND-NAND cell. Valid outputs of
AND-NAND logic port are in red, gravity points are in blue.
3.3. IMPLEMENTATION EXAMPLES 35
1. As we use a fully-CMOS technology, 111111 input must give 1 output
and 000000 input must give 0 output. Blue numbers are gravity points.
Red outputs are the correct bits of the AND-NAND cell, as shown in
Figure 3.12.
2. For both gravity points we find the 8-cell cubic covers that include the
neighboring bits.
3. We fill each cube with 0 or 1. Covers that include 1 are filled with 1 if
there is a majority of ones and covers that include 0 with 0 if there is a
majority of zeros. An example is shown in Figure 3.13 and the filled
map in Figure 3.14.
4. Now we have to fill remaining don’t care. A software (described in
Section 3.4) can do the filling. In this case the best substitution that
minimizes the number of literals consists in filling all remaining don’t
care with ones.
5. Now that all input bit combinations have a determinate output, we can
find the minimum covers and synthesize the circuit. The covers are
shown in Figure 3.15.
The corresponding literal expressions are:
Y = CD + AB + EF + BCE + BCF + ACF + ADE + BDE
+ ADF + ACE
= (A+ B)[C(F + E) + DE] + A(B + DF ) + CD + EF (3.3a)
Y = BCDF + ACDF + ABCF + ABDF + BCDE + ABDE
+ ACE + BDEF + ADEF + ACEF + BCEF
= [(F + E)(A+ C) + EF ] + FA [D(E + C) + C(B + E)]
+ EC(A+ FB) (3.3b)
Z = EF + AB + CD + BDF = F (E + BD) + AB + CD (3.4a)
Z = BDF + BCF + ADF + ACF + BDE + BCE + ADE
= [EB + F (A+ B)] (C +D) + ADE (3.4b)
36 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
AB
CD00 01 11 10
00
01
11
10
1 - --
- - --
- - --
- - --
EF
=
00
AB
CD00 01 11 10
00
01
11
10
1 - --
- - --
- - --
- - --
AB
CD00 01 11 10
00
01
11
10
- - --
- 0 0-
- 0 0-
- - --
EF
=
01
AB
CD00 01 11 10
00
01
11
10
- - --
- 1 1-
- 1 1-
- - --
AB
CD00 01 11 10
00
01
11
10
- - --
- - --
- - --
- - -0
EF
=
11
AB
CD00 01 11 10
00
01
11
10
- - --
- - --
- - --
- - -0
AB
CD00 01 11 10
00
01
11
10
- - --
- 0 0-
- 0 1-
- - --
(a) NAND - Z
EF
=
10
AB
CD00 01 11 10
00
01
11
10
- - --
- 1 1-
- 1 0-
- - --
(b) AND - Y
Figure 3.13: Karnaugh map of the three input AND-NAND cell. All the covers that include
a gravity point.
3.3. IMPLEMENTATION EXAMPLES 37
AB
CD00 01 11 10
00
01
11
10
1 1 1-
1 1 1-
1 1 1-
- - --
EF
=
00
AB
CD00 01 11 10
00
01
11
10
1 1 1-
1 1 1-
1 1 1-
- - --
AB
CD00 01 11 10
00
01
11
10
1 1 1-
1 0 00
1 0 00
- 0 00
EF
=
01
AB
CD00 01 11 10
00
01
11
10
1 1 1-
1 1 10
1 1 10
- 0 00
AB
CD00 01 11 10
00
01
11
10
- - --
- 0 00
- 0 00
- 0 00
EF
=
11
AB
CD00 01 11 10
00
01
11
10
- - --
- 0 00
- 0 00
- 0 00
AB
CD00 01 11 10
00
01
11
10
1 1 1-
1 0 00
1 0 10
- 0 00
(a) NAND - Z
EF
=
10
AB
CD00 01 11 10
00
01
11
10
1 1 1-
1 1 10
1 1 00
- 0 00
(b) AND - Y
Figure 3.14: Filled Karnaugh map, with all covers that contains a gravity point.
38 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 1 11
1 1 11
1 1 11
EF
=
00
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 1 11
1 1 11
1 1 11
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 0 00
1 0 00
1 0 00
EF
=
01
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 1 10
1 1 10
1 0 00
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 0 00
1 0 00
1 0 00
EF
=
11
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 0 00
1 0 00
1 0 00
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 0 00
1 0 10
1 0 00
(a) NAND - Z
EF
=
10
AB
CD00 01 11 10
00
01
11
10
1 1 11
1 1 10
1 1 00
1 0 00
(b) AND - Y
Figure 3.15: Minimum covers for the D2RA 3-input port. One covers are shown in purple,
zero covers are in green.
3.4. SOFTWARE IMPLEMENTATION 39
The result are the two circuits shown in Figure 3.16, one for Z-output
and one for Y -output.
3.4 Software implementation
A software has been implemented in C++ to automate the filling procedure
and to solve Karnaugh map giving as result the literals of the logic function.
C++ was chosen for the possibility to make objects that describe Karnaugh
maps and the related covers, that permit to do operations between arrays,
that represents covers and maps, in a simple way.
The software receives an input text file with the truth table, as the two
last columns of Table 3.1, were possible entries are: 0, 1 or -. All possible
covers are computed and stored. Then it fills the Karnaugh map using the
synthesis method shown in the past sections. At the end of this procedure it
prints a Karnaugh map similar to Figure 3.13.
The user can decide to fill remaining don’t care with all ones, zeros or to
try all possible combinations and find which minimize the number of literals.
The software now finds the minimal covers. When minimization is done,
the program print the full filled Karnaugh map (as Figure 3.14) and an
expression of literal output as a sum of products (as in Equations 3.3 or 3.4).
The used algorithm is shown in Algorithm 3.1.
40 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
A B A C E
C
EF
D
E
B D
F
D F
F
A
D C
E C B E
E
C
A F
B
D
B
E
F
F E
A C
Y
E B
D
A C
F
B B
C D
B
D
F
A B
A
D
E
Z
Figure 3.16: Schematic of the AND-NAND cell: Z and Y output.
3.4. SOFTWARE IMPLEMENTATION 41
Algorithm 3.1 Filling algorithm for a 3-input D2RA.
read truth table from file
Initialize double Karnaugh map K {as in Figure 3.12 without blue output}cell 000000 ← 1
cell 111111 ← 0
Make all possible covers:
for 000000 to 111111 do
if cell contents is 1 then
if no neighbouring 0’s then
fill a cube with 1’s to position 000000
end if
else if cell content is 0 then
if no neighbouring 1’s then
fill a cube with 0’s to position 111111
end if
end if
end for
Fill residual don’t care with ones (or zeros) to minimize literals
Find all prime covers
print Karnaugh map and literal equation
42 CHAPTER 3. D2RA:DOUBLE-RAIL REDUNDANT APPROACH
Chapter 4
Rad Hard Layout of the D2RA
cells
This chapter presents the techniques used to design a D2RA logic family that
include two inputs logic cells and a D-type flip-flop. Circuits are designed in
the 65 nm technology developed by TSMC.
4.1 Technology node choice
The first generation of LHC microelectronics components has been designed
and developed using a commercial 250 nm CMOS technology with special
layout techniques (Enclosed Layout Transistors, ELT, and guard-rings). A
second generation for upgraded LHC detectors uses a 130 nm CMOS tech-
nology, which offers significant advantages in terms of density and power
dissipation, especially because it does not require enclosed transistor layouts.
In the vision towards future experiments or upgrades, the demand for ever
smaller pixels, faster serializers and lower power in digital circuits requires a
full evaluation of a more advanced low-power technology which brings further
benefits to high volume designs.
The particular choice of 65 nm was done considering a number of factors.
First of all it allows for considerably higher density and lower power consump-
tion designs compared to previously used technologies (mainly 250 nm and
130 nm). It is a mature technology, being first introduced in the market in
2007 and it will be available for the foreseeable future, as it is widely used in
the semiconductor industry. Moving to a new technology will cause an in-
43
44 CHAPTER 4. RAD HARD LAYOUT OF THE D2RA CELLS
crease in the NRE costs, which is the main reason why even more downscaled
technologies (45 nm or smaller) were not considered. This technology does
not require special hardened by design transistor layouts for digital logic in
order to be TID-tolerant up to 200 Mrad [25].
Simulations show that HL-LHC pixel detectors will integrate a fluence
of about 1016 neutron/cm2 (1 MeV neutron equivalent) and a Total Ionizing
Dose (TID) of 10 MGy (1 Grad).
An important performance degradation has been observed for both N
and P channels devices starting from a dose level of 2 MGy and particularly
for narrow PMOS devices. At a dose level of 10 MGy, the PMOS transcon-
ductance loss is near 100% for narrow channel devices (measured at room
temperature) which turns the device completely off [1], as shown in Figure 4.1.
4.1.1 Total Ionizing Dose effect solution
To avoid the loss of transconductance at 10 MGy, both PMOS and NMOS
transistors are larger than minimum width: they have Wp =1.5 µm and
Wn =500 nm, as shown in Figure 4.2.
These values are chosen to keep the transconductance at least at 50% of
the nominal value at 10MGy TID.
4.1.2 Single Event Effect solutions
D2RA are combinational logic cells, so the parasitic charge collected by a
node can cause a SET in the output signals.
Reduction of SET
If a radiation hits a portion of circuit where there is an electric field, the
generated charges can influence different adjacent circuit nodes, as shown in
Figure 4.3.
The current flowing to a node may be also generated by charge generated
by radiation in in other parts of the circuit. For this reason, the two parts of
a D2RA cell are placed at a minimum distance of 5µm (Figure 4.4).
A circuit design solution to decrease SET propagation consist in maxi-
mizing the number of transistors connected to supply and ground voltages
(VSS and VDD). This reduces the radiation sensible area: ground and power
4.1. TECHNOLOGY NODE CHOICE 45
Figure 4.1: PMOS and NMOS devices ON state current versus TID for
devices having different channel width [25].
46 CHAPTER 4. RAD HARD LAYOUT OF THE D2RA CELLS
Figure 4.2: Layout of a part of the D2RA AND-NAND cell, showing MOS
width.
Figure 4.3: Spatial distribution of the charge injection due to radiation in an
integrated circuit. The ionization involves several circuit nodes.
4.2. LOGIC CELLS CIRCUITS 47
Figure 4.4: Four input D2RA logic tree composed by AND-NAND logic cells:
each cell (a) is connected with the (b) part respecting 5µm constraint.
supplies collect the injected charge and prevent SET propagation in others
nodes.
Reduction of SEU
The resistance to SEU is intrinsic in the logic family design: as shown in
Section 3.1, the insertion of a flip flop capable to stop invalid data stops the
propagation of SEU thought the logic chain.
4.2 Logic cells circuits
This section shows the design of the cells of the D2RA logic family. For each
cell, both the schematics and the layout are presented. Each cell is made of
two parts, one that processes output bit and one that processes the inverted
one.
Standard Cells
All logic cells are designed to be used in a standard cells design. Only Metal-1
is used for local interconnection. This allows better routing and less levels
of metal interconnections in the final chip. Power supply and ground metals
are 0.33µm wide to match standard cell values of the foundry library. The
highness of the entire cell (3.83µm) is designed to allow uniform horizontal
routing thought different lines of standard cells, as show in Figure 4.5.
4.2.1 AND-NAND and OR-NOR
The AND-NAND and the OR-NOR cells have the same circuit, with inverted
outputs and inputs, this can be derived from De Morgan’s Law (“The negation
48 CHAPTER 4. RAD HARD LAYOUT OF THE D2RA CELLS
Figure 4.5: XOR-NXOR cells with metal-3 (highlighted in green) horizontal
continuous routing trough VSS.
of a conjunction is the disjunction of the negations”). Circuit schematics
are shown in Figure 4.6. The two layout of cells B_CMOS_CELL_1_SC and
B_CMOS_CELL_2_SC, that synthesize respectively Z and Y outputs, are shown
in Figure 4.7.
4.2.2 XOR-XNOR
This logic function has the two blocks made with the same circuit that gives
both the output bit, with inputs (A, B, C, D), and the inverted one, with
inputs (B, A, C, D). The circuit schematic and the layout of the the cell
(B_CMOS_CELL_3_SC) are shown in Figure 4.8.
4.3 D2RA flip-flop
The D2RA logic uses the propagation of the bit and of the inverted bit. An
invalid data (0,0) or (1,1) has to be stopped. The circuit component that
performs this operation is the Delay flip-flop (D-FF).
4.3. D2RA FLIP-FLOP 49
A D D
CB
Z
A
D
B
C D
D B C
A C A
Y
B
D
C
A
C A
Figure 4.6: Schematic of the AND-NAND cell: Z output (left) and Y output
(right).
Figure 4.7: The two layout cells that composes AND-NAND and OR-NOR
D2RA cells: B_CMOS_CELL_1_SC and B_CMOS_CELL_2_SC, that synthesizes Z
(left) and Y (right).
50 CHAPTER 4. RAD HARD LAYOUT OF THE D2RA CELLS
C A
B D
Y
B
D
C
A
Figure 4.8: Schematic and layout of the D2RA XOR-NXOR cell.
4.3.1 Master-slave edge-triggered D-FF
A master-slave D-FF is made by connecting two multiplexers controlled by a
clock signal, in a master-slave configuration (Figure 4.9). In this configuration
the second latch (slave) changes only in response to a change in the first
(master) latch.
The master-slave D-FF is designed to be triggered by the rising edge of
the clock (positive-edge triggered master-slave D-FF).
When CLK is low (and CLK is high) the master latch stores the input
value in OUTmaster and OUT master circuital nodes. When CLK is high (and
CLK is low) the slave latch stores the input value (node OUTmaster and
OUT master ) in OUTslave and OUT slave circuital nodes.
When the CLK signal goes high (01 to 10) the signal at the input A
and B is propagated to OUTslave and OUT slave circuital nodes. The Master
latch stores signal in his output nodes when clock is low and when the clock
turns high the master latch stops propagating the input signal to OUTmaster
and OUT master nodes, storing the actual bit value. At the same time, when
CLK switch from low to high, the slave latch propagates the signal from
OUTmaster and OUT master to the outputs OUTslave and OUT slave. When the
4.3. D2RA FLIP-FLOP 51
A
BC
D
MUX
MASTER
CLK
CLK
A
B
C
D
MUX
SLAVE
OUTslave
OUT slave
CLK
CLK
OUTmaster
OUT master
Figure 4.9: Block scheme of a master-slave D-FF.
A
B
C
D
MUX Y
Z
ST
Figure 4.10: Block scheme of a D2RA MUX.
clock signal returns to low (10 to 01), the output of the slave latch is captured,
and the value seen at the last rising edge of the clock is held while the master
latch begins to accept new values in preparation for the next rising clock
edge.
Multiplexer
A D2RA Multiplexer (MUX) is needed to build the master-slave D-FF. A
MUX output is equal to the input selected by the control signal (in this case
the pair CLK and CLK).
The MUX logic gate is a three input D2RA cell (Figure 4.10). One input
is the pair CLK = S and CLK = T . A SEE may involve also clock signals,
52 CHAPTER 4. RAD HARD LAYOUT OF THE D2RA CELLS
AB
CD00 01 11 10
00
01
11
10
0 0 11
0 0 00
1 1 11
1 0 11
ST
=
10
AB
CD00 01 11 10
00
01
11
10
0 1 01
1 1 00
0 0 00
1 1 01
AB
CD00 01 11 10
00
01
11
10
0 0 11
0 0 11
0 0 11
0 0 01
(a) MUX-master (Z)
ST
=
01
AB
CD00 01 11 10
00
01
11
10
0 1 01
0 1 01
0 1 01
0 1 01
(b) MUX-master (Y)
Figure 4.11: Karnaugh map of the three input D2RA MUX-master cell.
so a circuit is designed (Section 4.3.2) to sense if the change of state of CLK
and CLK is simultaneous, therefore valid, or not, therefore due to a SEE. In
this case CLK and CLK have been corrected eliminating SET from signals.
Because of correction of clock signal, bit combination (1,1) and (0,0) of CLK
and CLK can be inverted.
The master and the slave MUX are made of two parts that will be placed at
a distance of 5 µm. The two parts have the same circuit: B_CMOS_CELL_4_SC
(Figure 4.14) with different inputs.
The designed circuit is the same for Y and Z output. Only input signals
changes. This paragraph is explains the design of the slave-MUX and the
master-MUX which is obtained by changing the inputs. The Karnaugh maps
are shown in Figure 4.11, and correspond to the following equations:
Y = CS + AC + ABS + BDC (4.1a)
= C(S + A) + B(AS + CD)
Y = ASB + AC + ADS + CB + CS (4.1b)
= C(S + B + A) + SA(B + D)
4.3. D2RA FLIP-FLOP 53
AB
CD00 01 11 10
00
01
11
10
0 0 00
0 0 00
1 1 11
1 1 11
ST
=
10
AB
CD00 01 11 10
00
01
11
10
0 0 00
1 1 11
0 0 00
1 1 11
AB
CD00 01 11 10
00
01
11
10
0 0 11
0 0 10
1 0 11
1 0 11
(a) MUX-slave - (Z)
ST
=
01
AB
CD00 01 11 10
00
01
11
10
0 1 01
1 1 01
0 1 00
1 1 01
(b) MUX-slave (Y)
Figure 4.12: Karnaugh map of the three input D2RA MUX-slave cell.
Z = DT + ABT + BD + DCA (4.2a)
= D(T + B) + A(BS + DC)
Z = DT + BCT + BD +DA+ ABT (4.2b)
= D(T + B + A) + BT (C + A)
Four inverters are needed to obtain the inverted signals at the input of
the circuit, the design of the inverter is described in Section 4.3.3.
The propagation of SEE must be stopped. Red output in Figures 4.11
and 4.12 are the result of a correct input, green output are corrected to
prevent propagation of SEE and blue is not correct.
Correct output is generated using both pairs of MUX inputs: for example
in master-MUX the 0010 input has always 10 output. This prevents the
propagation of faulty data to the output. Blue data are incorrect but are
transmitted, however it should be impossible to have the pairs 00 and 11. The
bit stored in (OUTslave, OUT slave) and (OUTmaster, OUTmaster) is certainly
correct, so (0,0) or (1,1) are impossible to have. The blue bits values are
chosen to minimize the number of literals.
54 CHAPTER 4. RAD HARD LAYOUT OF THE D2RA CELLS
Figure 4.13: Layout of CMOS cell MUX.
4.3. D2RA FLIP-FLOP 55
S B A
C
D B
A
S
Y
C
S A
B
A
S
D
C
Figure 4.14: Schematic of the D2RA MUX cell.
4.3.2 Clock edge detector
A circuit is designed to detect when a change of state is due to a SEE. This
is necessary because the master-slave D-FF without this circuit is triggered
also if a SEE influences either CLK or CLK. It is made of two inverters, a
NOR-NXOR gate, and a MUX, as shown in Figure 4.16.
The inverters generate signal CLKinveted and CLKinverted, the clock
signals and the inverted ones are given at the input of the XOR-XNOR D2RA
gate that generates the CLKenable (and CLKenable). These signals are the
inputs of the MUX and they select whether CLK or CLK can be propagated
to the output or have to be stopped. The circuit stops SEE propagation on
clock signal and also corrects clock when a SEE happened. A simulation is
shown in Figure 4.15.
4.3.3 Inverter
The inverters in the MUX and in the Clock edge detector have to be resistant
to SEE, to do that three inverters are put in parallel. The width of transistors
is 0.5 µm for NMOS and 1.5 µm for PMOS. The redundancy ensures that the
logic value of the output is preserved in case a SEE happens in one of the
inverters. The inverter layout is shown in Figure 4.17.
56 CHAPTER 4. RAD HARD LAYOUT OF THE D2RA CELLS
Figure 4.15: Simulation of front detector: signal NCLK and CLK have some SET, the
signal CLK VALID is high when is present a SET, at the output CLK and NCLK signals
are correct.
CLK
CLK
inverted
CLK
CLK
inverted
CLKVALID
CLKVALID
CLKOUT
CLKOUT
MUX
SLAVE
Figure 4.16: Block scheme of the clock edge detector.
4.3. D2RA FLIP-FLOP 57
Figure 4.17: Layout of inverter.
CLK
CLK
CLKcorrect
CLKcorrect
A
A
Y
Y
CLK
front detector
FF
master
-
slave
Figure 4.18: Block scheme of full Flip Flop circuit.
4.3.4 Complete FF circuit
The complete FF circuit is shown in Figure 4.18 and it is made by two blocks:
the Clock edge detector and the master-slave FF. Clock signal enters in the
first block and is checked and propagated to the second block, data signal
instead enters directly in FF block.
58 CHAPTER 4. RAD HARD LAYOUT OF THE D2RA CELLS
Chapter 5
Simulations
This chapter presents the method used to simulate radiation effects in circuits,
in the first part it is introduced the method and his peculiarity, in the second
part are described the implementation in SKILL language, in the third part
are explained the simulations and the results.
5.1 Introduction
Is important to know how much charge is collected in sensitive nodes to
simulate how radiation affects ICs. Basic properties of charge collection due
to the interaction between particles and CMOS devices have been carefully
investigated in the past years [26] [27] [28].
The physics of charge collection has also been studied in detail through
the use of two-dimensional (2-D) and three-dimensional (3-D) numerical
simulations [28]. Typically, a drift-diffusion model has been used to simulate
SEE in devices. Commercial software is also based on 3-D drift-diffusion
model; however, a 3-D model requires detailed information about fabrication
process, which is not commonly available.
The used technique is based on multiple current injection in order to model
and simulate the interactions between a single particle and p-n junctions, it
was successfully used for ICs design for space application [29].
59
60 CHAPTER 5. SIMULATIONS
5.2 Modelling single event mechanisms
(state-of-the-art)
This section presents the techniques used to model interaction between parti-
cles and p-n junction, a description of physic mechanism model, multidimen-
sional device simulations and circuit simulation.
5.2.1 Physic based models
At physical level, a drift-diffusion model was used to simulate mechanism. This
model was based on Boltzmann transport equation describing the statistical
distribution of particles in a fluid. Approximating this equation, it is possible
to solve a charge transport system using the Poisson equation combined with
the current continuity equations. All these equations are discretized and
solved using a finite-difference or finite-element techniques [15]. Normally,
drift-diffusion method consists in three state equations. However, in state-of-
the-art literature, more accurate models based on five or six state equations
exist. Obviously, these latter models are more computer-intensive than drift-
diffusion models.
5.2.2 Device simulations
Commercial softwares used to design ICs are based on 2-D (planar) environ-
ments (e.g. Cadence Virtuoso). Designers draw 2-D polygons in different
layers which are used to fabricate lithograph to build different real 3-D layers.
Since phenomena of interaction between a particle and ICs strongly depend
on vertical structure of ICs, to achieve a high level of accuracy three dimen-
sions models are required which are able to describe non-orthogonal (with
different incidence angles) particle strikes. For instance, Figure 5.1 shows a
non-orthogonal particle which collides into an IC. This particle ionizes several
p-n junctions [15].
A particle may ionize different regions with different charge density values.
Unfortunately, silicon foundries do not always release vertical information
about fabrication process (e.g. layer thickness, doping profiles, etc.) and
these parameters may be strongly different for similar technologies. For these
reasons, it is very difficult to perform a 3-D simulation using only the set of
2-D parameters provided by the silicon foundry.
5.3. SIMULATION MODEL 61
Figure 5.1: Non-orthogonal particle that collide in a IC.
5.2.3 Standard injection model
The most used model is based on a double-exponential current pulse:
i(t) =Q
t1 − t2(e−t/t1 − e−t/t2) (5.1)
where Q is the total injected charge, t1 is the collection time constant of
the junction, t2 is the time constant for initially establishing the ion track.
Interaction models presented in the literature were based on the injection
of a current pulse in a node of the SPICE netlist to estimate the critical
charge of all circuit nodes. For this reason, injection was done on every node,
one after the other. Depending on the circuit response, the current pulses
may create SETs which lead node voltage at values which exceed the dynamic
of the device (greater than power voltage supply or lesser than 0 V).
5.3 Simulation Model
These SET values that results from simulation based on double-exponential
current pulse are not reasonable and do not correspond to the physic reality.
For this reason is used another model of injection at circuit level, that is
presented in [29].
The model is based on the multiple injection of parasitic currents by means
of voltage-dependent current generators. Figure 5.2 shows the schematic of
the proposed model assuming that there are four nodes ionized by radiation.
In this case, holes are injected in four different p-diff/n-well junctions, the
number of junction can change depending on the particle hit position. Total
charge is injected by means of the non-dependent current generator Is in the
node chargep. Is generates a current similar to a Dirac’s delta with an area
which is equal to the value of total charge to inject. In this way, the Dirac’s
delta time correspond to the single event time. Moreover, the rise time of the
62 CHAPTER 5. SIMULATIONS
Figure 5.2: Injection model for 4 differnet p-diff/n-well junctions.
5.3. SIMULATION MODEL 63
generator Is have the same time profile of the rise time of currents generated
by the Voltage Controlled Current Generators: VCCS (G1, G2, G3 and G4).
Indeed, the current generated by the VCCS generators are the product of
the V s and the Vn:
in(t) = kn · Vs · Vn (5.2)
where Vn is taken between target node n and the voltage power supply,
k is used to split the total charge in different junctions with different values
depending on the hit position and on the geometrical shape of the junction.
To inject electrons in p-substrate/n-diff junctions we have to use a negative
Dirac’s delta and take Vn between ground and the target node. With this
model, it is also possible to make a coarse modelization of the recombination
effect. In fact, the recombination time is given by the time τ = Cs ·Rs.
5.3.1 The FISAR approach
FISAR: Fault Injection Simulation and Analysis for Radiation hardening
is used to validate the SEE robustness of large blocks at layout level. The
technique is based on the injection of a parasitic current at the circuit level,
to simulate the interaction between a single ionizing particle and the p-n
junctions within any region of the IC. In addition, depending on the nature of
the particle and on the energy of the particle, the extension of the ionization
column may range from some nanometres to some micrometres as shown in
Figure 5.3 [15]. As the region affected by an ionizing particle may be larger
than the area of a single node (Figure 4.3), an accurate model must include
all the parasitic currents simultaneously generated in adjacent nodes. For
this reason, it is necessary to inject a current pulse in all the nodes affected
by the ionization effect due to the particle.
Figure 5.4 shows a layout portion of a XOR-XNOR tree where a grid is
applied to the layout, partitioning it into an array of square elements called
boxes. In this example, the pitch of the grid is 0.5 µm, but the FISAR
approach can accept different values, depending on the extension of the
ionization column [15]. As an example, the extension of the ionization column
in silicon due to 210 MeV chlorine ion is approximated to 1.94µm. A 3×3
box array (called window) corresponds to the ionization region. Figure 5.5
shows a detail of the 5.4, illustrating the green window.
64 CHAPTER 5. SIMULATIONS
Figure 5.3: Radial track structure of low and high-energy ions with the same
incident LET. The dotted line draws the gaussian approximation of the track
center region. All three curves have the same integral charge[15].
Figure 5.4: Portion of the layout of a XOR tree with boxes.
5.3. SIMULATION MODEL 65
Figure 5.5: Detail of red window in Figure 5.4 with HEP density.
Figure 5.6: CMOS layers used to find p-n junctions.
CMOS processes are based on complementary MOS transistors (p-channel
transistors and n-channel) integrated onto the same substrate. p+ implan-
tation regions are obtained by adding acceptor atoms to the silicon lattice,
instead n+ ones are obtained by adding donor atoms to the silicon lattice.
Drains and sources correspond to diffusion regions (also called active areas),
that have thin oxides made to achieve a good MOS conductance. Building
a n-channel transistor is necessary to create a drain and a source diffusion
regions implanted with n+ (donors) also called n-diffusion regions. Whereas,
for p-channel transistors it is required to create diffusion regions with p+
implantation, also called p-diffusion regions. To take into account layout
geometries, we assume that the charge collected by each circuit node is
proportional to the p-n junction capacitance (relative of the node itself) of
n-diffusion or p-diffusion within a single window. CMOS layers used to
66 CHAPTER 5. SIMULATIONS
Figure 5.7: 2D gaussian function approximated with constant values on a 3x3
box array.
calculate the p-n junction capacitance are shown in Figure 5.6. In addition,
Figure 5.6 shows the p-n junction positions. It is assumed that ionization
does not involve metal interconnections.
5.3.2 Calculation of charge collected within each box
Generated parasitic charge is assumed to be collected only by p-n junctions.
The spatial distribution of the HEP (Hole-Electron-Pair) density is approx-
imated by means of a 2-D gaussian function, sampled in a 3×3 array, as
shown in Figure 5.7. As it is shown in Figure 5.3, where it is depicted the
released charge of a 210MeV chlorine ion in silicon, a better description
of the physical mechanism may be achieved using a non-gaussian function.
Assuming that the colliding angle of the particle is orthogonal to the IC
surface, and neglecting ionization outside the 3×3 array when the SEE occurs,
the total charge is spread among a cluster of 9 layout boxes. It is possible to
relate charge deposition with LET (Linear Energy Transfer): in silicon, a LET
of 97MeV cmmg−1 corresponds to a charge deposition of 1 pC µm−1. Hence,
knowing the particle energy, the particle species and the target material, it is
possible to calculate the total value of generated parasitic charge, which will
be divided among boxes. In particular, the charge within each box, Qb,k can
be calculated as a part of the total charge generated within the window k:
Qb,k = Qtot · wb,k (5.3)
5.3. SIMULATION MODEL 67
where Qtot is the total charge, and w b,k is the weight of each box, shown in
Figure 5.7 as a percentage.
5.3.3 Calculation of charge collected by circuit nodes
For each box, the charge generated by the particle collision Qb,k is divided
between nodes, in proportion to their junction capacitances.To obtain the
p-n junction capacitance of each box node, area and perimeter values are
multiplied with the unit junction capacitances specified in the transistor
models. Then, the amount of charge Qn,b,k collected by the node n inside the
box b referring to a window k is:
Qn,b,k = Qb,kCb,n∑
m∈b Cm,b
(5.4)
where Qb,k is the charge generated in the box b in the window k, Cb,n is the
capacitance of the node n inside the box b, and the sum is calculated for all
nodes lying within the box b. The calculation to find the portion of total
charge of each node Qn,k, is repeated for each node n and for each box b
inside the 3×3 window:
∀n ∈ k : Qn,k =9∑
b=1
Qn,b,k (5.5)
This calculation is repeated for all the windows k of the layout grid.
5.3.4 Circuit simulations
A circuit-level simulator is used to perform simulations (e.g., SPICE, Spectre).
In this case is used Spectre. Simulations are not performed for windows
which do not include p-n junctions. For circuit-level simulations a Polynomial
Voltage Controlled Current Source PVCCS generator is added for each of the
nodes lying within the ionized region. These current generators are labelled
Gn. In addition the tool adds to the netlist a node chargen which store the
total charge to inject in p-sub/n-diff junctions and a node chargep which
store the total charge to inject in p-diff/n-well junctions. The total charge are
stored by means of a capacitor Csn (for p-sub/n-diff juctions) and a capacitor
Csp (for p-diff/n-well junctions). As seen before in section 5.2.3, the event
time is chosen by means of non-dependent current generator which generates
68 CHAPTER 5. SIMULATIONS
a current impulse (ideally a Dirac’s delta). In Spectre netlist the Dirac’s
delta is modeled as a short triangular pulse with a duration of 20 ps. The
beginning of the pulse corresponds with to the beginning of the event. An
example of netlist is:
Csn (chargen 0) capacitor c=100f
Rsn (chargen 0) resistor r=1G
Isn(0 chargen) isource type=pulse val0=0 val1=-1.000000e-001 period=1 \
delay=75n rise=10p fall=10p width=0
Csp (chargep 0) capacitor c=100f
Rsp (chargep 0) resistor r=1G
Isp(0 chargep) isource type=pulse val0=0 val1=-1.000000e-001 period=1 \
delay=75n rise=10p fall=10p width=0
G0 (chargen net20 chargen 0 net20 0) pvccs \
gain=0.093473 coeffs=[ 0 0 0 0 1 0]
G1 (chargen net15 chargen 0 net15 0) pvccs \
gain=0.033179 coeffs=[ 0 0 0 0 1 0]
G2 (chargen Y chargen 0 Y 0) pvccs \
gain=0.063027 coeffs=[ 0 0 0 0 1 0]
G3 (chargen VDD chargen 0 VDD 0) pvccs \
gain=0.092545 coeffs=[ 0 0 0 0 1 0]
G4 (chargen VSS chargen 0 VSS 0) pvccs \
gain=0.248775 coeffs=[ 0 0 0 0 1 0]
G5 (chargep net03 chargep 0 net03 0) pvccs \
gain=0.081435 coeffs=[ 0 0 0 0 1 0]
G6 (chargep VSS chargep 0 VSS 0) pvccs \
gain=0.085565 coeffs=[ 0 0 0 0 1 0]
5.3.5 p-n junction capacitance calculation
The n-diffusion and p-diffusion geometrical areas and perimeters are es-
sential to calculate p-n junction capacitances, which are given by:
C = (Cj · Adiff ) + (Cjswg · Pgdiff ) + (Cjsw · Padiff ) (5.6)
where Adiff is the geometrical area of the diffusion region, Pgdiff is the
perimeter for the diffusion region along polysilicon gate and Padiff is the
perimeter for diffusion region not along polysilicon gate. Cj is the unit
capacitance for area diffusion. Cjswg is the unit capacitance for perimeter
diffusions along the polysilicon gate. Cjsw is the unit capacitance for perimeter
diffusions not along the polysilicon gate.
5.3. SIMULATION MODEL 69
Figure 5.8: Areas and perimeters of diffusion region for a conventional
transistor.
Because n-well junction capacitances aren’t negligible Cjnwsw and Cjnw,
that are omitted in first FISAR implementation [29], are now added to
consider the capacitance due to the n-well.
Unit capacitance values are contained in models used for circuit simulation.
In modern technologies, for the same perimeter value, capacitances along
the gate have higher values than capacitances not along the gate due to the
trench isolations.
Figure 5.8 shows the areas and perimeters of a diffusion region for a
conventional transistor in 3-D.
5.3.6 p-diffusion an n-diffusion calculation
These fabrication layers are used to calculate the p-n junctions areas: polysili-
con (PO), implantation p (PP) or n (NP), n-well (NW) and active area (OD).
The first step is to evaluating p-diffusion and n-diffusion geometries as follows:
Ndiff =NP ∩ (OD \NW ) (5.7a)
Pdiff =PP ∩ (OD ∩NW ) (5.7b)
where ∩ and \ indicate respectively the geometrical intersection and difference
among polygons.
70 CHAPTER 5. SIMULATIONS
5.4 SKILL integration of FISAR simulation
SKILL is a Lisp language used to write scripts in Cadence Virtuoso [30].
Originally FISAR was developed in MATLAB environment, the layout was
exported by a GDS file and layout geometry successively extracted.
Skill language si deeply integrated in Cadence virtuoso environment, indeed
the script act directly on layout in cadence editor VirtuosoGXL. This feature
allows to skip GDS exportation and importation in third part environment.
To associate layout polygons with signal name it is necessary to use
Cadence “LayoutGXL” and to build the circuit layout generating the layout
of each instance present in the circuit schematic with the software command
“generate from source”, that automatically generates instances with assigned
circuit pins or assign pin manually. In this way, the virtuoso software knows
the node name for each of the layout geometries. Actually, the software
proposed in this thesis does not handle more than one hierarchy level.
The program input is the cellview (a sort of pointer to the cadence layout)
of circuit layout and the output are the SPICE language files that describe
the radiation effects in each window.
The script executes the following operations: (1) preliminary geometry
extraction and structures definition; (2) calculation of the areas and the
perimeters; (3) link the corresponding signal to each NDIFF and PDIFF
geometries and (4) finally the composition of the simulation files.
5.4.1 Preliminary geometry exaction
Geometries are extracted from NP (N-implantation), PP (P-implantation),
NW (N-well), CO (Contact), PO (Poly-silicon) layers using 5.7a and 5.7b
formulas. Boolean operations between shapes, in the different layers, are
made by the function CCShierLayerOps that generate output on another
designed layer.
To handle all the data in a efficient way some structures are defined,
starting from the top level is created WindowList that is a list of structures
that describe windows, this structure is call SimStruct. Hierarchy and
components are shown in Figure 5.9.
Then is drawn the grid of all boxes. Shapes are divided in each box doing
an AND operation between the box square and all layer funded previously,
the result, that is stored in structures, is the list of all the shapes of active
5.4. SKILL INTEGRATION OF FISAR SIMULATION 71
SimStruct
LateralSquareID
Square
CornerSquareID
Square
CenterSquareID
Square
Knn
("signal","k")
Knp
("signal","k")
ShapeList
ShapesInSquares
SquareID
adress to object
Square
ShapesInSquares
ShapeNet
char
NWper NWareagatePerimeter AreaN AreaP
ShapeID
adress toobject
Cj
float
Cjswg Cjsw Cjnw Cjnwswm
float float float float
floatfloatfloat floatfloat
perimeter
float
Figure 5.9: Structure diagram of SKILL script. Green boxes are lists, blue
are structures and red are numbers or data.
72 CHAPTER 5. SIMULATIONS
area or NW present in each box.
5.4.2 Area and perimeter calculation
For each shape present in the box it is necessary to find: N-well area and
perimeter, N-doped and P-doped active area, active area perimeter (excluding
gate perimeter), gate perimeter and shape ID that identified the shape into
the CAD software.
To calculate area is used the function ABarea that requires a rectangle
or a polygon (in this case is used Shoelace formula) in input. To calculate
perimeter is used the function ABperimeter.
Perimeter correction and gate perimeter calculation
Perimeter have to be corrected because the formula ABperimeter calculates
the entire perimeter that include the boundary with the gate (that have a
different capacitance compared to active area perimeter) and the perimeter
due to the division in boxes, as shown in Figure5.10a. To correct box perimeter
is used the procedure in Figure 5.11, note that is not in scale. The Figure
used, shown in Figure 5.10b, is a square, which each side is shifted outside
by the minimum manufacture grid allowed by foundry rules. This procedure
is similar to the one used to calculate gate perimeter: the difference is that
polygon in Figure 5.10b is not used applied on the entire box but only on the
active area shape that is enlarged and intersected with the gate polysilicon.
This intersection is divided by minimum move and the result is the gate
perimeter that is in common with active area.
5.4.3 Net name association
To perform simulation is needed to know the net associated to each shape in
each box of each window. For this reason it is used LayoutGXL. This software
associate each instance with the correct net and pin in a semiautomatic way:
it create instances, the user have to place correctly and to attach pins. All
shapes of active area have associated their net name. This association is
essential because the shape and the instance can be intersected to find the
net corresponding to the shape. The bBox of the shape is extracted and
compared with the bBox of the active area inside the instance, it is necessary
5.4. SKILL INTEGRATION OF FISAR SIMULATION 73
(a)
500 nm5nm 5nm
(b)
Figure 5.10: Qualitative examples: a) Perimeter of an active area. To the
total perimeter have to be subtracted gate perimeter, in yellow dashes, and
box boundaries perimeter, in green dashes. b) polygon used to calculate
perimeter excess and gate perimeter.
a transformation between the coordinates inside the instance and the global
coordinates of the cellview.
5.4.4 Capacity calculation
The capacitance are calculated starting from the area and the perimeter, the
values are shown in Table 5.1
Table 5.1: Table of capacitance value used in simulation.
Capacity type value
Cjn 1.25× 10−3 fF/µm2 - 1.053× 10−5 fF/µm2
Cjswgn 2× 10−10 fF/µm - 1.7× 10−12 fF/µmCjswn 7.9× 10−11 fF/µm - 6.6× 10−13 fF/µmCjp 1.077× 10−3 fF/µm2 + 5.98× 10−6 fF/µm2
Cjswp 6.4× 10−11 fF/µm + 3.5× 10−13 fF/µmCjswgp 2.2× 10−10 fF/µm + 1.2× 10−12 fF/µm
74 CHAPTER 5. SIMULATIONS
Create polygon
Subtract box from polygon
Estract acrive area polygon
Enlarge active area polyogn of
minimum move onlywhere there is
active area
Intersect blue area with
red area
Divide area by minimum move
to find perimeter excess
Figure 5.11: Procedure to find perimeter excess.
5.5 Sensitivity
For each window analyzed, a raw file is generated as output of Spectre simu-
lation. The mapping function collects data from each raw file corresponding
to each window. The first step consists in collecting data about the refer-
ence simulation, i.e., the behavior of the circuit without radiation (without
PVCCS current generators). Successively, data is collected for each raw file
corresponding to the analyzed windows. To compare different layouts has
used glitch area as sensitivity parameter (as in former implementation [29]).
The glitch area is defined as follows:
An,k =
∫ tsup
0
|νn,0(t)− νn,k(t)| dt ∀n ∈ k (5.8)
Especially, for each simulated window k, we have defined two sensitivity
parameter values:
5.6. SENSITIVITY MAPS 75
1. An overall sensitivity value ςall,k which is calculated as:
ςall,k =∑n∈k
An,k ∀k (5.9)
where An,k is the glitch area at the node n, νn,0(t) is the voltage of
the node n not affected by radiation, and νn,k(t) is the voltage of the
node n affected by radiation into the window k. Diffusions biased at
power supply voltages are included in the calculation of p-n junction
capacitances, and hence, bias diffusions collect part of the total charge.
However, in Spectre simulations, power supply nodes are kept at a
constant voltage and therefore, VDD and VSS nodes are not included
in the formula 5.9;
2. The single node sensitivity value ς(n∗,k) is equal to An∗,k for a selected
node n∗:
ς(n∗,k) = An∗,k (5.10)
Finally, all sensitivity values are normalized by dividing each value by
the maximum value obtained. As all sensitivity maps are normalized, the
maximum value of a each map is used to compare different layouts.
5.6 Sensitivity maps
After extracting capacitance values, a shell script has been written to perform
simulation in each window, by injecting the charge in every circuit node. The
result shows if the charge can cause a SET and the entity of it (Figure 5.12).
For each window/simulation the quantity An,k as in Equation 5.8 has been
calculated. In the central box of every affected window a circle (with radius
proportional to the area of the SEE present on output waveform simulation)
has been drawn. An example is shown in Figure 5.13. This allow to have an
immediate view of which part of the circuit is more sensible to SEE and to
simulate its behavior with different radiation dose.
Figure 5.13 Compares simulations made injecting 1 pC/window, 0.1 pC/window
and 0.01 pC/window: a decrease of SET length can be noticed. In addition,
the variance of radius circles decreases. The duration and the deepness of
the SET is different for different charge values: 1 pC/window cause a set of
76 CHAPTER 5. SIMULATIONS
Figure 5.12: Simulation of a AND-NAND D2RA Y -output with the FISAR
approach. The blue waveform at the top is pre-radiation; the purple and
red waveforms are obtained injecting 1 pC/window and 0.1 pC/window in
window 62. They presents a SET, in the top one SET is large and cause a
bit flip, in the bottom one set is narrower because of less charge injected.
5.6. SENSITIVITY MAPS 77
1.2 ns and a change of bit value, 0.1 pC/windowcause a set of 0.2 ns and is
1V deep, 0.01 pC/windowcause a negligible SET, In simulation with bigger
charge injection the SET, if the working frequency is sufficiently high can
cause a SEU (Figure 5.12) Most-sensible area to SEE is between n-mos and
p-nos transistors, where the circles have a bigger radius.
The simulation demonstrate that incident radiation affecting one half of
the D2RA cell, influence only the corresponding output and not the inverted
one. This result can be seen in Figure 5.13.
78 CHAPTER 5. SIMULATIONS
Figure 5.13: Simulation result of a AND-NAND port, each green circle indicates how
much the output Y is influenced by a radiation incident in the box. The injected
charge is 1 pC/window at the top, 0.1 pC/window in the middle and 0.01 pC/window
at bottom.
Chapter 6
Test structures
Once the single circuits are designed is necessary to develop a method to
physically test them under a radiation source. Is important to make a structure
that can be scaled to reach a certain area on silicon wafer to optimize the
probability of interaction between radiation and circuit. It’s chosen to design
a logic tree for testing AND-NAND (OR-NOR have the same cells) and
XOR-NXOR cells and a Shift register to test the flip-flop. The circuit will be
irradiated and at the outputs can be seen if the radiation has affected circuit
functionality.
6.1 AND-NAND and XOR-NXOR tree
To test this cells is chosen to design logic tree, it can easy enlarged to the
necessary dimension.
The minimum tree circuit is composed by only tree logic cells (Figure 6.1
in black, the layout is in Figure 6.2). From this all others trees, with more
input, can be build.
Logic tree construction
Beginning from the base circuit is possible to make circuits with more inputs.
The minimum circuit has to be duplicate and another logic cell,that join the
two sub-tree, has to be added creating a new stage. This procedure is shown
in Figure 6.1.
To make the layout of the new circuit, the structure of the minimum
cell, shown in Figure 6.2, is copied mirroring it to match power sources and
79
80 CHAPTER 6. TEST STRUCTURES
A1A1A2A2
A3A3A4A4
YZ
A1A1A2A2
A3A3A4A4
A5A5A6A6
A7A7A8A8
YZ
Figure 6.1: Enlargement of number of input of a AND-NAND tree. In black
the original tree, in red the copied one and in green the logical port added to
joint the two sub-tree.
another cell, composed by two part is added (respecting 5 µm constraint), the
result is shown in Figure 6.1.
For example in Figure 6.3 is shown the schematic of a 16-input AND-
NAND tree, the layout is in Figure 6.4. The dimensions of all structures are
in Table 6.1.
6.2 Shift register
To test D2RA FF resistance to SEE is proposed a shift register, it is a chain
of FF, the data in input is propagated by one FF to the next at each CLK
rising, so a shift register with n cells outputs input data after n clock cycles.
In Figure 6.5 is shown a 4 cells shift register, the dimension of the layout is
in Table 6.1
6.2. SHIFT REGISTER 81
Figure 6.2: Layout of the AND-NAND (at top) and XOR-NXOR (at bottom)
logic tree base structure.
A1A1A2A2
A3A3A4A4
A5A5A6A6
A7A7A8A8
A9A9A10A10
A11A11A12A12
A13A13A14A14
A15A15A16A16
YZ
Figure 6.3: A 16 input AND-NAND test tree.
82 CHAPTER 6. TEST STRUCTURES
Figure 6.4: Layout of the AND-NAND 16 input logic tree.
Table 6.1: Dimensions of test structures
Input AND-NAND OR-NOR shift register
number w×h (µm) w×h (µm) w×h (µm)
4 13.2× 3.83 16.2× 3.83 318.4× 3.83
8 21.6× 7.33 17.6× 7.33 318.4× 7.33
16 21.6× 14.33 17.6× 14.33 318.4× 14.33
32 21.6× 28.33 17.6× 28.33 318.4× 28.33
64 21.6× 56.33 17.6× 56.33 318.4× 56.33
128 21.6× 112.33 17.6× 112.33 318.4× 112.33
256 21.6× 224.33 17.6× 224.33 318.4× 224.33
512 21.6× 448.33 17.6× 448.33 318.4× 448.33
1024 21.6× 896.33 17.6× 896.33 318.4× 896.33
6.3. SIMULATION 83
ANA
CLK
NCLK
CLK
NCLK
CLK
NCLK
CLK
NCLK
YNYFF- 1 FF- 2 FF- 3 FF- 4
Figure 6.5: Shift register composed by four FF.
FF- 1 FF- 2 FF- 3
FF- 4FF- 5FF- 6
FF- 7 FF- 8 FF- 9
Figure 6.6: Shift register layout, signal propagation. It is not in scale.
Flip Flop shift register construction
The base circuit is the FF, the dimensions of the circuit can be decided adding
or removing link from the chain of FF. Because there are not problems with
signal routing that limits the number of FF in each row, is decided to make a
structure composed by tree column of FF and any number of rows. The data
signal follow the path in figure6.6.
6.3 Simulation
Is performed a simulation of time delay between input and output in non-
radiation environment: the result shows a logarithmic growth of time at the
growing of inputs number, it can be seen in Figure 6.7. This happens because
at the increasing of input the number of stage increase, and with it the time
delay.
The trend is logarithmic because 2n input requires n stages to construct a
full tree. For instance, in Figure 6.3 shown a 16 input AND-NAND tree, it
has 24 inputs and 4 stages.
In the right graphic of Figure 6.7 there is a gap from the linear trend
84 CHAPTER 6. TEST STRUCTURES
0 500 1,000
0.2
0.4
0.6
0.8
1
1.2
Number of inputs
Input-outp
utdelay(n
s)
23 25 27 29
0.2
0.4
0.6
0.8
1
1.2
Number of inputs (log2)Input-outp
utdelay(n
s)
Figure 6.7: Simulation of input-output delay of a XOR-NXOR tree with
parasitic extraction, At left the x-scale is linear, in the right graphic the
x-scale is logarithmic in base 2.
specially in points related with high number of inputs. It is due to metal
parasitism because the metal wire length grows greatly with the growth of
the input: each stage add a great amount of metal path between input and
output. There is no presence of this effect in a simulation without parasitic
extraction, so it is almost totally due to metal interconnections.
Chapter 7
Conclusions
In this thesis the effects of radiation on ICs have been studied and a new family
of standard cells have been proposed with the aim to resist at high-radiation
(1Grad) dose. This resistance is achieved by a Double Rail Redundant
Approach (D2RA).
A new synthesis method has been proposed to synthesize both D2RA cell
halves. This synthesis has the properties of correctness and minimality that
ensures the creation of minimal circuits. The method is implemented in a
C++ software. It received in input the table of truth of a two or three input
logic function, and it generates the Karnaugh maps and the minimal logical
expression.
The logic cells (circuits and layouts) design are:
• Two inputs cells
– AND-NAND
– OR-NOR
– XOR-XNOR
• Three inputs cells
– MUX
• Sequential cells
– Clock edge detector
– D-Flip Flop
85
86 CHAPTER 7. CONCLUSIONS
To simulate the interaction with radiation, the D2RA cells have been
analyzed with the layout oriented simulation, FISAR, which extracts parasitic
capacity directly from the layout trough a SKILL script and write the simula-
tion a Spectre netlist. From simulation results FISAR generates a sensitivity
map of the outputs.
This simulation confirms that radiation incident to one of the two cells
that compose the logic port influences only the corresponding output ensuring
the possible SET of only one output. The logic cells match the requirement
of radiation hardness and speed, the D-FF is more slow, it can handle a speed
of 100MHz, the slowness is due to the clock edge detector.
To characterize the logic cells in a real high-radiation environment some
test structures have been designed:
• AND-NAND logic tree
• XOR-XNOR logic tree
• Shift register with D-FF
In near future the test structures will be placed in a prototype chip and
characterize in an high-radiation environment.
7.1 Further development
To met 2GHz requirement, a different D-FF need to be designed. It will be
necessary to achieve a full integration of D2RA family into a definitive chip.
A possible solution is to provide a clock signal that is not affected by SEE
and eliminate clock edge detector circuit.
FISAR simulation can be refined computing also n-well capacitance, that
is irrelevant for small-signal simulation but absorbs charge generated by
radiation. Unfortunately, Spice model does not contain this value and it is
not provided by TSMC.
FISAR simulation software can be improved building a User Interface
to integrate it in Virtuoso and extending the simulation hierarchically into
instances.
Symbols and abbreviations
Abbreviation Description Definition
ATLAS A Toroidal LHC ApparatuS page 7
CMOS Complementary Metal Oxide Semiconductor page 9
CMS Compact Muon Solenoid page 7
D2RA Duble-Rail Redundant Approach page 9
D-FF Delayed Flip Flop page 48
DDD Displacement Damage Dose page 16
ECC Error Correcting Code page 9
ELT Enclosed Layout Transistors page 43
FISAR Fault Injection Simulation and Analysis for Radiation page 63
HEP Hole Electron Pair page 66
HL-LHC High Luminosity Large Hadron Collider page 7
LET Linear Energy Transfer page 12
RHBD Radiation Hardening By Design page 8
RHBP Radiation Hardening By Process page 8
SEE Single Event Effect page 15
SEGR Single Event Gate Rupture page 16
SET Single Event Transient page 16
SEU Single Event Upset page 15
TID Total Ionizing Dose page 16
TSMC Taiwan Semiconductor Manufacturing Company page 23
VCCS Voltage Controlled Current Generators page 63
87
88 CHAPTER 7. CONCLUSIONS
Bibliography
[1] P. Valerio, “65 nm technology for HEP: Status and perspective,” in PoS,
Vertex2014, Sep 2014.
[2] G. M. Anelli, “Conception et caracterisation des circuits integres
resistants aux radiations pour le detecteur de particules du lhc en tech-
nologies cmos submicroniques profondes,” Ph.D. dissertation, INPG, 46
av. Felix-Viallet, Grenoble (France).
[3] J. Mitchell, “Radiation-induced space-charge buildup in mos structures,”
Electron Devices, IEEE Transactions on, vol. 14, pp. 764–774, Nov 1967.
[4] P. J. McWhorter and P. S. Winokur, “Simple technique for sep-
arating the effects of interface traps and trapped–oxide charge in
metal–oxide–semiconductor transistors,” Applied Physics Letters, vol. 48,
no. 2, 1986.
[5] J. Aitken and D. Young, “Avalanche injection of holes into SiO2,” Nuclear
Science, IEEE Transactions on, vol. 24, pp. 2128–2134, Dec 1977.
[6] P. Winokur, H. Boesch, J. McGarrity, and F. McLean, “Field and time-
dependent radiation effects at the sio2/si interface of hardened mos
capacitors,” Nuclear Science, IEEE Transactions on, vol. 24, pp. 2113–
2118, Dec 1977.
[7] F. McLean, “A framework for understanding radiation-induced interface
states in sio2 mos structures,” Nuclear Science, IEEE Transactions on,
vol. 27, pp. 1651–1657, Dec 1980.
[8] G. Baccarani and M. Wordeman, “Transconductance degradation in
thin-oxide mosfet’s,” Electron Devices, IEEE Transactions on, vol. 30,
pp. 1295–1304, Oct 1983.
89
90 BIBLIOGRAPHY
[9] J. Schwank, F. Sexton, M. Shaneyfelt, and D. Fleetwood, “Total ionizing
dose hardness assurance issues for high dose rate environments,” Nuclear
Science, IEEE Transactions on, vol. 54, pp. 1042–1048, Aug 2007.
[10] N. Saks, M. Ancona, and J. Modolo, “Radiation effects in mos capacitors
with very thin oxides at 80K,” Nuclear Science, IEEE Transactions on,
vol. 31, pp. 1249–1255, Dec 1984.
[11] D. Fleetwood, “Total ionizing dose effects in mos and low-dose-rate-
sensitive linear-bipolar devices,” Nuclear Science, IEEE Transactions on,
vol. 60, pp. 1706–1730, June 2013.
[12] N. S. Saks, M. Ancona, and J. Modolo, “Generation of interface states
by ionizing radiation in very thin mos oxides,” Nuclear Science, IEEE
Transactions on, vol. 33, pp. 1185–1190, Dec 1986.
[13] P. Dodd, “Device simulation of charge collection and single-event upset,”
Nuclear Science, IEEE Transactions on, vol. 43, pp. 561–575, Apr 1996.
[14] M. Baze, S. Buchner, and D. McMorrow, “A digital cmos design technique
for seu hardening,” Nuclear Science, IEEE Transactions on, vol. 47,
pp. 2603–2608, Dec 2000.
[15] P. Dodd, O. Musseau, M. Shaneyfelt, F. Sexton, C. D’hose, G. Hash,
M. Martinez, R. Loemker, J.-L. Leray, and P. Winokur, “Impact of ion
energy on single-event upset,” Nuclear Science, IEEE Transactions on,
vol. 45, pp. 2483–2491, Dec 1998.
[16] C. Guenzer, E. Wolicki, and R. Allas, “Single event upset of dynamic
rams by neutrons and protons,” Nuclear Science, IEEE Transactions on,
vol. 26, pp. 5048–5052, Dec 1979.
[17] C. Rusu, A. Bougerol, L. Anghel, C. Weulerse, N. Buard, S. Benhammadi,
N. Renaud, G. Hubert, F. Wrobel, T. Carriere, and R. Gaillard, “Multiple
event transient induced by nuclear reactions in cmos logic cells,” in On-
Line Testing Symposium, 2007. IOLTS 07. 13th IEEE International,
pp. 137–145, July 2007.
[18] P. Dodd, J. Schwank, M. Shaneyfelt, J. Felix, P. Paillet, V. Ferlet-
Cavrois, J. Baggio, R. Reed, K. Warren, R. Weller, R. Schrimpf, G. Hash,
S. Dalton, K. Hirose, and H. Saito, “Impact of heavy ion energy and
BIBLIOGRAPHY 91
nuclear interactions on single-event upset and latchup in integrated
circuits,” Nuclear Science, IEEE Transactions on, vol. 54, pp. 2303–2311,
Dec 2007.
[19] A. Javanainen, T. Malkiewicz, J. Perkowski, W. Trzaska, A. Virtanen,
G. Berger, W. Hajdas, R. Harboe-Sorensen, H. Kettunen, V. Lyapin,
M. Mutterer, A. Pirojenko, I. Riihimaki, T. Sajavaara, G. Tyurin, and
H. Whitlow, “Linear energy transfer of heavy ions in silicon,” Nuclear
Science, IEEE Transactions on, vol. 54, pp. 1158–1162, Aug 2007.
[20] S. Diehl, A. Ochoa, P. Dressendorfer, R. Koga, and W. Kolasinski, “Error
analysis and prevention of cosmic ion-induced soft errors in static cmos
rams,” Nuclear Science, IEEE Transactions on, vol. 29, pp. 2032–2039,
Dec 1982.
[21] F. Wang and V. Agrawal, “Soft error considerations for computer web
servers,” in System Theory (SSST), 2010 42nd Southeastern Symposium
on, pp. 269–274, March 2010.
[22] A. Paccagnella, “Single event effects: Introduction,” in Scuola Nazionale
di Legnaro, 2007.
[23] M. Karnaugh, “The map method for synthesis of combinational logic
circuits,” American Institute of Electrical Engineers, Part I: Communi-
cation and Electronics, Transactions of the, vol. 72, pp. 593–599, Nov
1953.
[24] V. Ciriani, L. Frontini, V. Liberali, S. Shojaii, A. Stabile, and G. Trucco,
“Radiation-tolerant standard cell synthesis using double-rail redundant
approach,” in Electronics, Circuits and Systems (ICECS), 2014 21st
IEEE International Conference on, pp. 626–629, Dec 2014.
[25] S. Bonacini, P. Valerio, R. Avramidou, R. Ballabriga, F. Faccio, K. Klouk-
inas, and A. Marchioro, “Characterization of a commercial 65 nm cmos
technology for slhc applications,” Journal of Instrumentation, vol. 7,
no. 01, p. P01015, 2012.
[26] B. Narasimham, B. Bhuva, R. Schrimpf, L. Massengill, M. Gad-
lage, O. Amusan, W. Holman, A. Witulski, W. Robinson, J. Black,
J. Benedetto, and P. Eaton, “Characterization of digital single event
92 BIBLIOGRAPHY
transient pulse-widths in 130-nm and 90-nm cmos technologies,” Nuclear
Science, IEEE Transactions on, vol. 54, pp. 2506–2511, Dec 2007.
[27] G. Abadir, W. Fikry, H. Ragai, and O. Omar, “A new semi-empirical
model for funneling assisted drain currents due to single events,” in
Microelectronics, 2003. ICM 2003. Proceedings of the 15th International
Conference on, pp. 391–394, Dec 2003.
[28] G. Messenger, “Collection of charge on junction nodes from ion tracks,”
Nuclear Science, IEEE Transactions on, vol. 29, pp. 2024–2031, Dec
1982.
[29] A. Stabile, “Design metodologies for radiation-hardened memories in
cmos technology,” Ph.D. dissertation.
[30] T. Barnes, “Skill: a cad system extension language,” in Design Automa-
tion Conference, 1990. Proceedings., 27th ACM/IEEE, pp. 266–271, Jun
1990.