Register with Parallel Load
• Register: Group of Flip-Flops
• Ex: D Flip-Flops
• Holds a Word (Nibble) of Data
• Loads in Parallel on ClockTransition
• Asynchronous Clear (Reset)
Register with Load Control
• Load Control = 1– New data loaded
on next positiveclock edge
• Load Control = 0– Old data reloaded
on next positiveclock edge
Shift Registers
• Cascade chain of Flip-Flops
• Bits travel on Clock edges (Bucket Brigade)
• Serial in – Serial out, can also have parallel load / read
Serial Addition (D Flip-Flop)
• Slower than parallel
• Low cost• Share fast
hardware onslow data
• Good for multiplexed data
Designing a JK Serial Adder
• JQ = xy, KQ = xy = (x+y), S = xyQFlip_Flop
Inputs JQ KQ
0 x0 x0 x1 xx 1x 0x 0x 0
Inputsx y
0 00 11 01 10 00 11 01 1
NextState
Q
00010111
PresentState
Q
00001111
OutputS
01101001
Table 6-2
Binary Ripple Counter
• Asynchronouscounter
• Changes “ripple”through the stages
A3
000000001
A2
000011110
A1
001100110
A0
010101010
Table 6-4
Synchronous Binary Counter
• All transitions occur onclock pulse edges inparallel
• Faster results than ripplecounters
Designing a SynchronousBCD Counter
Present StateQ8 Q4 Q2 Q1
0 0 0 00 0 0 1
0 0 1 0 0 0 1 10 1 0 00 1 1 00 1 0 10 1 1 11 0 0 01 0. 0 1
Outputy
0000000001
Next State Q8 Q4 Q2 Q1
0 0 0 10 0 1 0 0 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0. 0 10 0 0 0
Next State TQ8 TQ4 TQ2 TQ1
0 0 0 10 0 1 1 0 0 0 10 1 1 10 0 0 10 0 1 10 0 0 11 1. 1 10 0 0 11 0 0 1
TQ1 = 1, TQ2 = Q8Q1 , TQ4 = Q2Q1 , TQ8 = Q8Q1 + Q4Q2Q1 , y = Q8Q1
4-bit Synchronous Counterwith Parallel Load
Clear
0111
Clk
x
Load
x100
Count
xx10
Function
ClearLoadCount
No Change
Table 6-6
Counters with Unused States
• If in unused state– Ensure automatic
return to a validstate
– “Self-correcting”