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DIGITAL ELECTRONIC DEVICES
Basic Operation Characteristics and Parameters
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COMPARING LOGIC FAMILIES
Family Propagation delay
(ns)
Power dissipation
(mW)
Speed-power
product (pWs)
74 10 10 100
74S 3 20 60
74LS 9 2 18
74ALS 4 1 4
74F 2.7 4 11
4000B(CMOS) 105 1 @ 1MHz 105
74HC (CMOS) 10 1.5 @ 1MHz 15
100K (ECL) 0.8 40 32
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DC SUPPLY VOLTAGE
TTL
Vcc = +5V 10%
CMOS
VDD = +3 ~ +15V
ECL
VEE = -5.2V
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LOGIC LEVEL
TTL5V
2V
0.8V
OV
5V
2.4V
0.4V
OV
LOGIC 1 LOGIC 1
LOGIC 0 LOGIC 0
VIH
VIL
VOH
VOL
VIH(max)
VIH(min)
VIL(max)
VIL(min)
VOH(max)
VOH(min)
VOL(max)
VOL(min)Input Output
unpredictable
unpredictable
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LOGIC LEVEL (CONT.)
CMOS5V
3.5V
1.5V
OV
5V
4.9V
0.1V
OV
LOGIC 1 LOGIC 1
LOGIC 0
LOGIC 0
VIH
VIL
VOH
VOL
VIH(max)
VIH(min)
VIL(max)
VIL(min)
VOH(max)
VOH(min)
VOL(max)
VOL(min)Input Output
unpredictableunpredictable
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NOISE IMMUNITY
Noise is unwanted voltage that is induced in
electrical signal and can be present as a threat
to the proper operation of the circuit
The ability of a gate to ignore voltage noise is
its noise immunity.
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NOISE IMMUNITY (CONT.)
.
VIH
VIH(min)
2V
Noise riding on VIH level
Unpredictable region
If excessive noise causes
input to go below 2V
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NOISE IMMUNITY (CONT.)
.
VIL
VIL(min)0.8V
Noise riding on VIL level
Unpredictable region
If excessive noise causes
input to go below 2V
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NOISE MARGIN
A measure of a circuits immunity to noise is
specified by a noise margin voltage
The greater of the noise margin, the better ofthe circuit is able to ignore or be immune to
noise signal
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NOISE MARGIN (CONT.)
.5V
0V
VIH(min)
VIL(max)
VOH(min)
VOL(max)
Input Output
Ideal HIGH level
HIGH level
noise margin
LOW level
noise margin
Ideal LOW level
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NOISE MARGIN (CONT.)
LOW level noise margin
The difference between the maximum LOW level
output and input voltage.
VNL = VIL(max) VOL(max)
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NOISE MARGIN (CONT.)
HIGH level noise margin
The difference between the minimum HIGH level
output and input voltage.
VNH = VOH(min) VIH(min)
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NOISE MARGIN (CONT.)
Example:
A TTL gates has the following actual voltage level
values: VIH(min) = 1.5V and VIL(max) = 0.6V. Assuming
its being driven by a gate with VOH(min) = 2.6V and
VOL(max) = 0.4V, determine the high and low level
noise margin?
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NOISE MARGIN (CONT.)
Solution:
High level noise margin
VNH = VOH(min) VIH(min)
= 2.6V 1.5V = 1.1V
Low level noise margin
VNL = VIL(max) VOL(max)
= 0.6V 0.4V
= 0.2V
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POWER DISSIPATION
Power dissipation = dc supply voltage x average
supply current
PD
= VCC
x ICC
LOW HIGHHIGH LOW
+VCC +VCC
ICCH ICCL
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POWER DISSIPATION (CONT.)
So, average power dissipation
PD(avg) = VCC ICCL + ICCH mW
2
The average power dissipated by each gate
PD = PD(avg) mW
N
Where; N = the number of gates inside theparticular IC
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POWER DISSIPATION (CONT.)
Example:
An IC operating from VCC = 5V having six inverters
draws a current of ICCH = 1mA and ICCL = 3mA.
Determine the average power dissipation of a single
inverter circuit.
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POWER DISSIPATION (CONT.)
Solution:
PD(avg) = VCC * [(ICCL + ICCH) / 2]
= 5V * [(3mA + 1mA) / 2]
= 10mW
PD(gate) = PD(avg) / N
= 10mW / 6
= 1.67mW
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PROPAGATION DELAY TIME
Important characteristics of logic circuits
because it limits the switching speed
(frequency)
When signal passes (propagates) through a
logic circuit, it always experiences a time delay
A change in the output level always occurs a
short time, called propagation delay time.
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PROPAGATION DELAY TIME (CONT.)
If shorter propagation delay, the speed of the
circuit become higher
tDelay
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SPEED POWER PRODUCT
A measure of the performance of a logic circuit
SPP = propagation delay time x power
dissipationUnit = Joule
The smaller of the speed power product, the
performance is more better.
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FAN OUT
There is a limit to the number of load gate
inputs that a given gate can drive. This limit is
called the fan-out of the gate.
The number of gate that may be driven by
single gate output.
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FAN OUT (CONT.)
Fan out = driver gate current capacity = IOL(max)
current drawn per gate IIL(max)
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FAN OUT (CONT.)
Example:
Determine fan-out if a driver gate can sink a
maximum of 30mA and load gates provide a
maximum sink of current of 6mA/gate?
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FAN OUT (CONT.)
Solution:
Fan-out = driver gate current capacity / currentdrawn per gate
= IOL(max) / IIL (max)
= 30mA / 6mA
= 5
Under these condition, 5 gates each provide6mA, can be connected to one output, whichcapacity is 30mA.