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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Digital and Electronic Circuits for
Computer Systems
MSIT 123 Computer Architecture and Operating Systems
Lecture 0
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Signals, Logic Operators, and Gates
Some basic elements of digital logic circuits, with operator signs
used in this book highlighted.
x| y
AND Name X RRNOT
raphicals mbol
x y
Operatorsi andalternate(s)
x yx yxy
x y
xd
xorx_
xvy or xyArithmeticexpression x y2xyx y xy1x
Outputis 1 iff:
Input is 0Both inputs
are1sAt least one
input is 1Inputs arenot equal
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Variations in Gate Symbols
Gates with more than two inputs and/or with inverted
signals at input or output.
NN NDND N
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Gates as Control Elements
An A gate and a tristate buffer act as controlled switches or valves.
An inverting buffer is logically the same as a OT gate.
Enable/Pass signale
ata inata out
orata in
Enable/Pass signale
ata outor high im edance
(a) A gate for controlled trans fer (b) Tristate buffer
(c) odel for A switch.
e
o dataor
e
ex
(d) odel for tristate buffer.
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Wired O and us Connections
Wired O allows tying together of several controlled signals.
e
e
e Data out(x, y, z,
or highimpedance)
(b) Wired O of t ristate outputs
e
e
e
Data out(x, y, z, or 0)
(a) Wired O of product terms
z
x
y
z
x
y
z
x
y
z
x
y
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Control/ ata Signals and Signal undles
Arrays of logic gates represented by a single gate symbol.
/8
/8
/
8
Compl
/ /
k
/
En
able
/
k
/k/k
(b) AN gates (c) k gates(a) 8 N gates
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Boolean Functions and Expressions
Ways of specifying a logic function
y Truth table: 2n row, dont-care in input or output
y Logic expression: wd (x y z), product-of-sums,
sum-of-products, equivalent expressions
y Word statement: Alarm will sound if the door
is opened while the security system is engaged,or when the smoke detector is triggered
y Logic circuit diagram: Synthesis vs analysis
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Laws (basic identities) ofB
oolean algebra.
Name of law OR version AND version
Identity x 0 =x x1 =x
One/Zerox 1 = 1 x0 = 0
Idempotent xx= x x x =x
Inverse xxd = 1 x xd = 0
Commutative x y= yx x y = y x
Associative (x y) z=x (y z) (x y) z=x(y z)
istributive x (y z) = (x y) (x z) x(y z) = (x y) (x z)
eMorgans (x y)d =xd yd (x y)d =xd yd
Manipulating Logic Expressions
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Proving the Equivalence of Logic Expressions
Example 1.1
y Truth-table method: Exhaustive verification
yArithmetic substitutionx y=x+ yxy
x y=x+ y 2xy
y Case analysis: two cases,x=0 orx= 1
y Logic expression manipulation
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, OxfordUniversity Press.
Designing Gate etworks
yA D-O , A D- A D, O -A D, O - O
y Logic optimization: cost, speed, power dissipation
(a AD
-O circ it
z
x
y
x
y
z
( i i i ( N ND N ND i l
z
x
y
x
y
z
z
x
y
x
y
z
wo l l ND O i i wo i l i i s.
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
BCD-to-Seven-SegmentDecoder
Example 1.2
The logic circuit that generates the enable signal for the lowermost
segment (number 3) in a seven-segment display unit.
x3
x2
x1
x0
Signals toenable orturn on thesegments
4-bit input in [0, 9]
e0
e5
e6
e4
e2
e1
e3
1
24
5
0
3
6
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Useful Combinational
Parts
y High-level building blocks
y Much like prefab parts used in building a house
yArithmetic components will be covered in Part III
(adders, multipliers, ALUs)
y Here we cover three useful parts:multiplexers, decoders/demultiplexers, encoders
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Decoders/Demultiplexers
A decoder allows the selection of one of 2a options using an a-bit
address as input. A demultiplexer(demux) is a decoder that only
selects an output if its enable signal is asserted.
y y
x
x
x2
x2
y y
x
x
x2
xe
2
y y
x
xx2
x
(a) 2-to- decoder (b) Decoder symbol
(c) Demultiplexer ordecoder with enable
( nable)
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Encoders
A 2a-to-a encoder outputs an a-bit binary number equal to the
index of the single 1 among its 2a inputs.
(a) 4-to-2 encoder (b) Encoder symbol
x0
x
x2
x1
y1
y0
1
0
2
x0
x
x2
x1
y1
y0
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Programmable Combinational Parts
y Programmable OM (PROM)
y Programmable array logic (
PAL)
y Programmable logic array (PLA)
A programmable combinational part can do the job of
many gates or gate networks
Programmed by cutting existing connections (
fuses)or establishing new connections (antifuses)
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
PROMs
Programmable connections and their use in a PROM.
. . .
.
.
.
n uts
Out uts
(a Programmable
OR gates
w
x
(
w
x
(
(
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
PALs and PLAs
Programmable combinational logic: general structure and two classes
known as PAL and PLA devices. ot shown is PROM with fixed A D
array (a decoder) and programmable OR array.
A Darray(A D
plane)
ORarray(OR
plane)
. . .
. . .
.
.
.
nputs
Outputs
(a) eneral programmablecombinational logic
(b) PAL: programmableA D array fixed OR array
inputA Ds
(c) PLA: programmableA D and OR arrays
inputA Ds
inputORs
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Timing and Circuit Considerations
y Gate delay H: a fraction of, to a few, nanoseconds
y Wire delay, previously negligible, is now important
(electronic signals travel about 1 cm per ns)
y Circuit simulation to verify function and timing
Changes in gate/circuit output, triggered by changes in its
inputs, are not instantaneous
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Glitching
Timing diagram for a circuit that exhibits glitching.
x=
y
z
a = xy
f= a z
2H 2H
UsingthePALinFig.1.13btoimplementf=x y z
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
CMOS Transmission Gates
A CMOS transmission gate and its use in building a 2-to-1 mux.
z
0
1
a CMOS transmission gate
ir uit and s mbol
b T o-input mux built o t o
transmission gates
TG
TGTG
P
N
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Latches, Flip-Flops, and Registers
Latches, flip-flops, and registers.
RQ
QdS
D
Q
Qd
C
Q
Qd
D
C
(a) SRlatch (b) D latch
Q
C Q
DQ
C Q
D
(e) k-bit regi ter(d) D flip-flop sy bol(c) Master-slave D flip-flop
Q
C Q
D
FF
/ /k k
Q
C Q
D
FF
R
S
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Latches vs Flip-Flops
Operations ofD latch and negative-edge-triggered D flip-flop.
D
C
D latch: Q
D FF: Q
et ptime
et ptime
oldtime
oldtime
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Reading and Modifying FFs in the Same Cycle
Register-to-register operation with edge-triggered flip-flops.
/ /k k
Q
C Q
D
FF
/ /k k
Q
C Q
D
FF
Comp tation mod le(com inational logic)
ClocPropagation delay
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Finite-State Machines
Example 2.1
State table and state diagram for a vending machine coin
reception unit.
DimeDimeuarter
Dime
uarter
Dime
uarter
Dime
uarter
ResetReset
Reset
Reset
Reset
Startuarter
S00
S10
S20
S25
S0
S5
S10
S25
S00
S00
S00
S00
S00
S00
S20
S5
S5
S5
S5
S5
S5
S0
S5
S5
------- Input -------
Dime
uarter
Reset
Currentstate
S00S5
is the initial stateis the final state
Next state
Dimeuarter
S00
S10
S20
S25
S 0S 5
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Sequential Machine Implementation
Hardware realization of Moore and Mealy sequential
machines.
Ne t statelo ic
State re ister
n m
l
Inputs utputs
Ne t statee citationsi nals
Presentstate
utputlo ic
nly for Mealy machine
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Designing Sequential Circuits
Example 2.3
Hardware realization of a coin reception unit (Example 2.3).
utput
C
De
nputs
C
D
C
D
2
q
d
uarter in
Dime in
inal
state
is xx
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Shift Register
Register with single-bit left shift and parallel load capabilities. For
logical left shift, serial data in line is connected to 0.
arallel data in
kk
k
Shift
FF
0
Serial data in
k1 LSBs
Load
Parallel data out
Serial data outMSB
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
SRAM
SRAM memory is simply a large, single-port register file.
ol mn m
Ro
e
o
er
/h
A ress
S are or almost s arememory matri
Ro ffer
Ro
ol mn
g its ata o t
/g
/h
rite ena le
/g
Data in
A ress
Data o t
tp tena le
ipsele t
.
.
.
. . .
. . .
(a) SR AM lo iagram ( ) SRAM rea me anism
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Binary Counter
Synchronous binary counter with initialization capability.
Count re ister
u
ncre enter
nput
oa
ncrdnit
x+ 1
x
0 1
1c
inc
out
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Programmable Sequential Parts
y Programmable array logic (PAL)
yField-programmable gate array (F
PGA)
y Both types contain macrocells and interconnects
A programmable sequential part contain gates and
memory elements
Programmed by cutting existing connections (fuses)
or establishing new connections (antifuses)
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
PAL and FPGA
Examples of programmable sequential logic.
(a) Portion ofP AL it storable output (b) Generic structure of an FPGA
8-input
ANDs
D
FF
ux
ux
I/ bloc s
onfigurable
logic bl oc
Programmable
connections
L
L
L
L
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Binary Counter
Synchronous binary counter with initialization capability.
Count re ister
u
ncre enter
nput
oa
ncrdnit
x+ 1
x
0 1
1c
inc
out
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Clocks and Timing of Events
Clock is a periodic signal: clock rate = clock frequencyThe inverse of clock rate is the clock period: 1 GHz m 1 ns
Constraint: Clock period u tprop + tcomb + tsetup + tskew
Determining the required length of the clock period.
Other inputs
Combinational
logic
Clock period
FF1 begins
to change
FF1 change
observed
Must be wide enough
to accommodate
worst-case delays
Clock1 Clock2C
D
FF2C
D
FF1
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Synchronization
Synchronizers are used to prevent timing problems arising from
untimely changes in asynchronous signals.
Asynchinput AsynchinputSynchversion Synchversion
Asynchinput
Synch
version
Clock
(a) Simple synchronizer (b) T o-FF synchronizer
(c) Input and output aveforms
C
DFF
C
DFF2
C
DFF1
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Adapted from: Parhami, Behrooz (2005), Computer Architecture: From Microprocessors to Supercomputers, Oxford
University Press.
Level-Sensitive Operation
Two-phase clocking with nonoverlapping clock signals.
Combi-
national
logic1J
1
Clock period
J C
D
Latch
1J
C
D
Latch
Other inputs
Combi -
national
logic2J
2J
Clocks with
nonoverlapping
highs
Other inputs
C
LatchD