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SYLLABUS
1. Design and implementation of Adders and Subtractors using logic
gates.
2. Design and implementation of code converters using logic gates
(i) BCD to excess- code and voice versa
(ii) Binar! to gra! and vice-versa
. Design and implementation of " bit binar! Adder# subtractor and
BCD adder using $C %"&
". Design and implementation of 2Bit 'agnitude Comparator using
logic gates & Bit 'agnitude Comparator using $C %"&
. Design and implementation of 1 bit odd#even parit! c*ec+er
#generator using $C%"1&,.
. Design and implementation of 'ultiplexer and De-multiplexer using
logic gates and stud! of $C%"1, and $C %"1"
%. Design and implementation of encoder and decoder using logic
gates and stud! of $C%"" and $C%"1"%
&. Construction and verification of " bit ripple counter and 'od-1, #
'od-12 ipple counters
. Design and implementation of -bit s!nc*ronous up#do/n counter
1,. $mplementation of S$S0 S$0 $S0 and $0 s*ift registers using
3lip- flops.
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LIST OF EXPERIMENTS
1. Stud! of logic gates.
2. Design and implementation of adders and subtractors using logic
gates.
. Design and implementation of code converters using logic gates.
". Design and implementation of "-bit binar! adder#subtractor and
BCD adder using $C %"&.
5. Design and implementation of 2-bit magnitude comparator
using logic gates &-bit magnitude comparator using $C %"&.
. Design and implementation of 1-bit odd#even parit! c*ec+er#
generator using $C %"1&,.
%. Design and implementation of multiplexer and demultiplexer
using logic gates and stud! of $C %"1, and $C %"1".
&. Design and implementation of encoder and decoder using logic
gates and stud! of $C %"" and $C %"1"%.
. Construction and verification of "-bit ripple counter and 'od-
1,#'od-12 ripple counter.
1,. Design and implementation of -bit s!nc*ronous up#do/n
counter.
11. $mplementation of S$S0 S$0 $S0 and $0 s*ift
registers using flip-flops.
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INDEX
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2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 4
EXP.
NO
DATE NAME OF THE EXPERIMENT PAGE
NO
MARKS SIGNATURE
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EXPT NO. : T!D" O# LO$IC $%TE
D%TE :
%IM:To study about logic gates and verify their truth tables.
%PP%&%T! &E'!I&ED:
T(EO&":
Circuit that takes the logical decision and the process are called logic
gates. Each gate has one or more input and only one output.
OR, A! and OT are basic gates. A!, OR and "#OR are
kno$n as universal gates. %asic gates form these gates.
%ND $%TE:
The A! gate performs a logical multiplication commonly kno$n as
A! function. The output is high $hen both the inputs are high. The outputis lo$ level $hen any one of the inputs is lo$.
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 5
&' o. CO()OET &)EC*+*CAT*O T-
. A! /ATE *C 0123
4. OR /ATE *C 014
. OT /ATE *C 0121
1. A! /ATE 4 *6) *C 0122 5. OR /ATE *C 0124
7. "#OR /ATE *C 0137
0. A! /ATE *6) *C 012
3. *C TRA*ER 8*T #
9. )ATC: COR! # 1
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O& $%TE:
The OR gate performs a logical addition commonly kno$n as OR
function. The output is high $hen any one of the inputs is high. The output
is lo$ level $hen both the inputs are lo$.
NOT $%TE:
The OT gate is called an inverter. The output is high $hen the
input is lo$. The output is lo$ $hen the input is high.
N%ND $%TE:
The A! gate is a contraction of A!#OT. The output is high
$hen both inputs are lo$ and any one of the input is lo$ .The output is lo$
level $hen both inputs are high.
NO& $%TE:
The OR gate is a contraction of OR#OT. The output is high $hen
both inputs are lo$. The output is lo$ $hen one or both inputs are high.
X-O& $%TE:
The output is high $hen any one of the inputs is high. The output is
lo$ $hen both the inputs are lo$ and both the inputs are high.
P&OCED!&E:
;i< Connections are given as per circuit diagram.
;ii< 'ogical inputs are given as per circuit diagram.
;iii< Observe the output and verify the truth table.
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%ND $%TE:
"M*OL: PIN DI%$&%M:
O& $%TE:
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NOT $%TE:
"M*OL: PIN DI%$&%M:
X-O& $%TE :
"M*OL : PIN DI%$&%M :
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2-INP!T N%ND $%TE:
"M*OL: PIN DI%$&%M:
3-INP!T N%ND $%TE :
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NO& $%TE:
&E!LT:
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EXPT NO. : DEI$N O# %DDE& %ND !*T&%CTO&
D%TE :
%IM:
To design and construct half adder, full adder, half subtractor and full
subtractor circuits and verify the truth table using logic gates.
%PP%&%T! &E'!I&ED:
&l.o. CO()OET &)EC*+*CAT*O T-.
. A! /ATE *C 0123
4. "#OR /ATE *C 0137 . OT /ATE *C 0121
1. OR /ATE *C 014
. *C TRA*ER 8*T #
1. )ATC: COR!& # 4
T(EO&":
(%L# %DDE&:
A half adder has t$o inputs for the t$o bits to be added and t$o
outputs one from the sum = &> and other from the carry = c> into the higher
adder position. Above circuit is called as a carry signal from the addition of
the less significant bits sum from the "#OR /ate the carry out from the
A! gate.
#!LL %DDE&:
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A full adder is a combinational circuit that forms the arithmetic sum of
input? it consists of three inputs and t$o outputs. A full adder is useful to add
three bits at a time but a half adder cannot do so. *n full adder sum output
$ill be taken from "#OR /ate, carry output $ill be taken from OR /ate.
(%L# !*T&%CTO&:
The half subtractor is constructed using "#OR and A! /ate. The
half subtractor has t$o input and t$o outputs. The outputs are difference and
borro$. The difference can be applied using "#OR /ate, borro$ output can
be implemented using an A! /ate and an inverter.
#!LL !*T&%CTO&:
The full subtractor is a combination of "#OR, A!, OR, OT /ates.
*n a full subtractor the logic circuit should have three inputs and t$o outputs.
The t$o half subtractor put together gives a full subtractor .The first half
subtractor $ill be C and A %. The output $ill be difference output of full
subtractor. The e@pression A% assembles the borro$ output of the half
subtractor and the second term is the inverted difference output of first "#
OR.
LO$IC DI%$&%M:
(%L# %DDE&
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T&!T( T%*LE:
% * C%&&" !M
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
,-Ma o !M: ,-Ma o C%&&":
!M %* %* C%&&" %*
LO$IC DI%$&%M:
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#!LL %DDE&
#!LL %DDE& !IN$ TO (%L# %DDE&
T&!T( T%*LE:
% * C C%&&" !M
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
,-Ma o !M:
!M %*C %*C %*C %*C
,-Ma o C%&&":
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C%&&" %* *C %C
LO$IC DI%$&%M:
(%L# !*T&%CTO&
T&!T( T%*LE:% * *O&&O DI##E&ENCE
0
0
1
1
0
1
0
1
0
1
0
0
0
1
1
0
,-Ma o DI##E&ENCE:
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DI##E&ENCE %* %*
,-Ma o *O&&O:
*O&&O %*
LO$IC DI%$&%M:
#!LL !*T&%CTO&
#!LL !*T&%CTO& !IN$ TO (%L# !*T&%CTO&:
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 1)
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T&!T( T%*LE:
% * C *O&&O DI##E&ENCE
0
00
0
1
1
1
1
0
01
1
0
0
1
1
0
10
1
0
1
0
1
0
11
1
0
0
0
1
0
11
0
1
0
0
1
,-Ma o Deene:
Deene %*C %*C %*C %*C
,-Ma o *oo6:
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*oo6 %* *C %C
P&OCEED!&E:
;i< Connections are given as per circuit diagram.
;ii< 'ogical inputs are given as per circuit diagram.
;iii< Observe the output and verify the truth table.
&E!LT:
EXPT NO. :
D%TE :
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DEI$N %ND IMPLEMENT%TION O# CODE CONVE&TO&
%IM:
To design and implement 1#bit
;i< %inary to gray code converter
;ii< /ray to binary code converter
;iii< %C! to e@cess# code converter
;iv< E@cess# to %C! code converter
%PP%&%T! &E'!I&ED:
&l.o. CO()OET &)EC*+*CAT*O T-.
. "#OR /ATE *C 0137
4. A! /ATE *C 0123
. OR /ATE *C 014 1. OT /ATE *C 0121
5. *C TRA*ER 8*T #
7. )ATC: COR!& # 5
T(EO&":
The availability of large variety of codes for the same discrete
elements of information results in the use of different codes by different
systems. A conversion circuit must be inserted bet$een the t$o systems if
each uses different codes for same information. Thus, code converter is a
circuit that makes the t$o systems compatible even though each uses
different binary code.
The bit combination assigned to binary code to gray code. &ince each
code uses four bits to represent a decimal digit. There are four inputs and
four outputs. /ray code is a non#$eighted code.
The input variable are designated as %, %4, %, %2 and the output
variables are designated as C, C4, C, Co. from the truth table,
combinational circuit is designed. The %oolean functions are obtained from
8#(ap for each output variable.
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A code converter is a circuit that makes the t$o systems compatible
even though each uses a different binary code. To convert from binary code
to E@cess# code, the input lines must supply the bit combination of
elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A t$o#level logic diagram may be obtained directly from the %oolean
e@pressions derived by the maps. These are various other possibilities for a
logic diagram that implements this circuit. o$ the OR gate $hose output is
C! has been used to implement partially each of three outputs.
LO$IC DI%$&%M:
*IN%&" TO $&%" CODE CONVE&TO&
,-Ma o $3:
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$3 *3,-Ma o $2:
,-Ma o $1:
,-Ma o $0:
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T&!T( T%*LE:
*na n9 $a o;e o99
*3 *2 *1 *0 $3 $2 $1 $0
0
0
0
0
0
0
0
0
1
1
1
1
1
11
1
0
0
0
0
1
1
1
1
0
0
0
0
1
11
1
0
0
1
1
0
0
1
1
0
0
1
1
0
01
1
0
1
0
1
0
1
0
1
0
1
0
1
0
10
1
0
0
0
0
0
0
0
0
1
1
1
1
1
11
1
0
0
0
0
1
1
1
1
1
1
1
1
0
00
0
0
0
1
1
1
1
0
0
0
0
1
1
1
10
0
0
1
1
0
0
1
1
0
0
1
1
0
0
11
0
LO$IC DI%$&%M:
$&%" CODE TO *IN%&" CONVE&TO&
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,-Ma o *3:
*3 $3
,-Ma o *2:
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,-Ma o *1:
,-Ma o *0:
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T&!T( T%*LE:
$a Co;e *na Co;e
$3 $2 $1 $0 *3 *2 *1 *0
0
00
0
0
0
0
0
1
1
1
11
1
1
1
0
00
0
1
1
1
1
1
1
1
10
0
0
0
0
01
1
1
1
0
0
0
0
1
11
1
0
0
0
11
0
0
1
1
0
0
1
1
00
1
1
0
0
00
0
0
0
0
0
1
1
1
11
1
1
1
0
00
0
1
1
1
1
0
0
0
01
1
1
1
0
01
1
0
0
1
1
0
0
1
10
0
1
1
0
10
1
0
1
0
1
0
1
0
10
1
0
1
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,-Ma o E2:
,-Ma o E1:
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,-Ma o E0:
T&!T( T%*LE:
*CD n9 E>e?? @ 3 o99
*3 *2 *1 *0 $3 $2 $1 $0
0
00
0
0
0
0
0
1
1
11
1
1
1
1
0
00
0
1
1
1
1
0
0
00
1
1
1
1
0
01
1
0
0
1
1
0
0
11
0
0
1
1
0
10
1
0
1
0
1
0
1
01
0
1
0
1
0
00
0
0
1
1
1
1
1
>>
>
>
>
>
0
11
1
1
0
0
0
0
1
>>
>
>
>
>
1
00
1
1
0
0
1
1
0
>>
>
>
>
>
1
01
0
1
0
1
0
1
0
>>
>
>
>
>
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LO$IC DI%$&%M:
EXCE-3 TO *CD CONVE&TO&
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,-Ma o %:
% X1 X2 X3 X4 X1
,-Ma o *:
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,-Ma o C:
,-Ma o D:
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T&!T( T%*LE:
E>e?? @ 3 In9 *CD O99
*3 *2 *1 *0 $3 $2 $1 $0
0
0
0
0
0
1
1
1
11
0
1
1
1
1
0
0
0
01
1
0
0
1
1
0
0
1
10
1
0
1
0
1
0
1
0
10
0
0
0
0
0
0
0
0
11
0
0
0
0
1
1
1
1
00
0
0
1
1
0
0
1
1
00
0
1
0
1
0
1
0
1
01
P&OCED!&E:
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;i< Connections $ere given as per circuit diagram.
;ii< 'ogical inputs $ere given as per truth table
;iii< Observe the logical output and verify $ith the truth tables.
&E!LT:
EXPT NO. : DEI$N O# 4-*IT %DDE& %ND !*T&%CTO&
D%TE :
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%IM:
To design and implement 1#bit adder and subtractor using *C 013.
%PP%&%T! &E'!I&ED:
&l.o. CO()OET &)EC*+*CAT*O T-.
. *C *C 013
4. E"#OR /ATE *C 0137
. OT /ATE *C 0121
. *C TRA*ER 8*T #
1. )ATC: COR!& # 12
T(EO&":
4 *IT *IN%&" %DDE&:
A binary adder is a digital circuit that produces the arithmetic sum of
t$o binary numbers. *t can be constructed $ith full adders connected in
cascade, $ith the output carry from each full adder connected to the input
carry of ne@t full adder in chain. The augends bits of =A> and the addend bits
of =%> are designated by subscript numbers from right to left, $ith subscript
2 denoting the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C 2 and it ripples
through the full adder to the output carry C1.
4 *IT *IN%&" !*T&%CTO&:
The circuit for subtracting A#% consists of an adder $ith inverters,
placed bet$een each data input =%> and the corresponding input of full adder.
The input carry C2must be eBual to $hen performing subtraction.
4 *IT *IN%&" %DDE&/!*T&%CTO&:
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The addition and subtraction operation can be combined into one
circuit $ith one common binary adder. The mode input ( controls the
operation. hen (D2, the circuit is adder circuit. hen (D, it becomes
subtractor.
4 *IT *CD %DDE&:
Consider the arithmetic addition of t$o decimal digits in %C!,
together $ith an input carry from a previous stage. &ince each input digit
does not e@ceed 9, the output sum cannot be greater than 9, the in the sum
being an input carry. The output of t$o decimal digits must be represented in
%C! and should appear in the form listed in the columns.
A%C! adder that adds 4 %C! digits and produce a sum digit in %C!.
The 4 decimal digits, together $ith the input carry, are first added in the top
1 bit adder to produce the binary sum.
PIN DI%$&%M #O& IC 7483:
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LO$IC DI%$&%M:
4-*IT *IN%&" %DDE&
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 3)
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LO$IC DI%$&%M:
4-*IT *IN%&" !*T&%CTO&
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LO$IC DI%$&%M:
4-*IT *IN%&" %DDE&/!*T&%CTO&
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T&!T( T%*LE:
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 3+
In9 Daa % In9 Daa * %;;on 9Aaon
%4 %3 %2 %1 *4 *3 *2 *1 C 4 3 2 1 * D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
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LO$IC DI%$&%M:
*CD %DDE&
, M%P
" 4
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T&!T( T%*LE:
*CD !M C%&&"
4 3 2 1 C
0 0 0 0 0
0 0 0 1 00 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
P&OCED!&E:
;i< Connections $ere given as per circuit diagram.
;ii< 'ogical inputs $ere given as per truth table
;iii< Observe the logical output and verify $ith the truth tables.
&E!LT:
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EXPT NO. :
D%TE :
DEI$N %ND IMPLEMENT%TION O# M%$NIT!DE
COMP%&%TO&
%IM:
To design and implement
;i< 4 bit magnitude comparator using basic gates.
;ii< 3 bit magnitude comparator using *C 0135.
%PP%&%T! &E'!I&ED:
&l.o. CO()OET &)EC*+*CAT*O T-.
. A! /ATE *C 0123 4
4. "#OR /ATE *C 0137
. OR /ATE *C 014
1. OT /ATE *C 0121
5. 1#%*T (A/*TF!E
CO()ARATOR
*C 0135 4
7. *C TRA*ER 8*T #
0. )ATC: COR!& # 2
T(EO&":
The comparison of t$o numbers is an operator that determine one
number is greater than, less than ;or< eBual to the other number. A magnitude
comparator is a combinational circuit that compares t$o numbers A and %
and determine their relative magnitude. The outcome of the comparator is
specified by three binary variables that indicate $hether AG%, AD% ;or