DRAM Tutorial
18-447 Lecture
Vivek Seshadri
Vivek Seshadri – Thesis Proposal
DRAM Module and Chip
2
Vivek Seshadri – Thesis Proposal
Goals
• Cost
• Latency
• Bandwidth
• Parallelism
• Power
• Energy
3
Vivek Seshadri – Thesis Proposal
DRAM Chip
4
Row Decoder
Array o
f Sen
se A
mp
lifiers
Ce
ll Array
Ce
ll Array
Row Decoder
Array o
f Sen
se A
mp
lifiers
Ce
ll Array
Ce
ll Array
Ban
k I/O
Vivek Seshadri – Thesis Proposal
Sense Amplifier
5
enable
top
bottom
Inverter
Vivek Seshadri – Thesis Proposal
Sense Amplifier – Two Stable States
6
1 1
0
0VDD
VDD
Logical “1” Logical “0”
Vivek Seshadri – Thesis Proposal
Sense Amplifier Operation
7
0
VT
VB
VT > VB1
0
VDD
Vivek Seshadri – Thesis Proposal
DRAM Cell – Capacitor
8
Empty State Fully Charged State
Logical “0” Logical “1”
1
2
Small – Cannot drive circuits
Reading destroys the state
Vivek Seshadri – Thesis Proposal
Capacitor to Sense Amplifier
9
1
0
VDD
1
VDD
0
Vivek Seshadri – Thesis Proposal
DRAM Cell Operation
10
½VDD
½VDD
01
0
VDD½VDD+δ
Vivek Seshadri – Thesis Proposal
DRAM Subarray – Building Block for DRAM Chip
11
Ro
w D
eco
de
r
Cell Array
Cell Array
Array of Sense Amplifiers (Row Buffer) 8Kb
Vivek Seshadri – Thesis Proposal
DRAM Bank
12
Ro
w D
eco
de
r
Array of Sense Amplifiers (8Kb)
Cell Array
Cell Array
Ro
w D
eco
de
r
Array of Sense Amplifiers
Cell Array
Cell Array
Bank I/O (64b)
Ad
dre
ss
AddressData
Vivek Seshadri – Thesis Proposal
DRAM Chip
13
Row Decoder
Array o
f Sen
se
Am
plifie
rs
Ce
ll Array
Ce
ll Array
Row Decoder
Array o
f Sen
se
Am
plifie
rs
Ce
ll Array
Ce
ll Array
Ban
k I/O
Row Decoder
Array o
f Sen
se
Am
plifie
rs
Ce
ll Array
Ce
ll Array
Row Decoder
Array o
f Sen
se
Am
plifie
rs
Ce
ll Array
Ce
ll Array
Ban
k I/O
Row Decoder
Array o
f Sense
Am
plifiers
Cell A
rray
Cell A
rray
Row Decoder
Array o
f Sense
Am
plifiers
Cell A
rray
Cell A
rray
Ban
k I/O
Row Decoder
Array o
f Sense
Am
plifie
rs
Ce
ll Array
Cell A
rray
Row Decoder
Array o
f Sense
Am
plifie
rs
Ce
ll Array
Cell A
rray
Ban
k I/O
Row Decoder
Arr
ay o
f Se
nse
A
mp
lifie
rs
Ce
ll A
rray
Ce
ll A
rray
Row Decoder
Arr
ay o
f Se
nse
A
mp
lifie
rs
Ce
ll A
rray
Ce
ll A
rray
Ban
k I/
O
Row Decoder
Arr
ay o
f Se
nse
A
mp
lifie
rs
Cel
l Arr
ay
Cel
l Arr
ay
Row Decoder
Arr
ay o
f Se
nse
A
mp
lifie
rs
Cel
l Arr
ay
Cel
l Arr
ay
Ban
k I/
O
Row Decoder
Arr
ay o
f Se
nse
A
mp
lifie
rs
Ce
ll A
rray
Ce
ll A
rray
Row Decoder
Arr
ay o
f Se
nse
A
mp
lifie
rs
Ce
ll A
rray
Ce
ll A
rray
Ban
k I/
O
Row Decoder
Arr
ay o
f Se
nse
A
mp
lifie
rs
Ce
ll A
rray
Ce
ll A
rray
Row Decoder
Arr
ay o
f Se
nse
A
mp
lifie
rs
Ce
ll A
rray
Ce
ll A
rray
Ban
k I/
O
Shared internal bus
Memory channel - 8bits
Vivek Seshadri – Thesis Proposal
DRAM Operation
14
Ro
w D
eco
de
rR
ow
De
cod
er
Array of Sense Amplifiers
Cell Array
Cell Array
Bank I/O
Data
1
2
ACTIVATE Row
READ/WRITE Column
3 PRECHARGE
Ro
w A
dd
ress
Column Address
RowCloneFast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization
Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu,
P. B. Gibbons, M. A. Kozuch, T. C. Mowry
Vivek Seshadri
Vivek Seshadri – Thesis Proposal
Memory Channel – Bottleneck
Core
Core
Cac
he
MC
Me
mo
ry
Channel
Limited Bandwidth
High Energy
Vivek Seshadri – Thesis Proposal
Goal: Reduce Memory Bandwidth Demand
Core
Core
Cac
he
MC
Me
mo
ry
Channel
Reduce unnecessary data movement
Vivek Seshadri – Thesis Proposal
Bulk Data Copy and Initialization
Bulk Data Copy
Bulk Data Initialization
src dst
dstval
Vivek Seshadri – Thesis Proposal
Bulk Data Copy and Initialization
Bulk Data Copy
Bulk Data Initialization
src dst
dstval
Vivek Seshadri – Thesis Proposal
Bulk Copy and Initialization –Applications
Forking
00000
00000
00000
Zero initialization(e.g., security)
VM CloningDeduplication
Checkpointing
Page Migration
Many more
Vivek Seshadri – Thesis Proposal
Shortcomings of Existing Approach
Core
Core
Cac
he
MC Channelsrc
dst
High latency(1046ns to copy 4KB)
Interference
High Energy(3600nJ to copy 4KB)
Vivek Seshadri – Thesis Proposal
Our Approach: In-DRAM Copy with Low Cost
Core
Core
Cac
he
MC Channeldst
High latency
Interference
High Energy
src
XX
X
?
RowClone: In-DRAM Copy
23
Vivek Seshadri – Thesis Proposal
Two Key Observations
24
Ro
w D
eco
de
r
Any operation on one senseamplifier can be easilyperformed in bulk
Many DRAM cellsshare the samesense amplifier
1
2
Vivek Seshadri – Thesis Proposal
Bulk Copy in DRAM – RowClone
25
½VDD
½VDD
01
0
VDD½VDD +δ
Data getscopied
Vivek Seshadri – Thesis Proposal
Fast Parallel Mode – Benefits
26
Latency Energy
Bulk Data Copy (4KB across a module)
1046ns to 90ns 3600nJ to 40nJ
No bandwidth consumption
Very little changes to the DRAM chip
11X 74X
Vivek Seshadri – Thesis Proposal
Fast Parallel Mode – Constraints
• Location constraint
– Source and destination in same subarray
• Size constraint
– Entire row gets copied (no partial copy)
27
1
2
Can still accelerate many existing primitives(copy-on-write, bulk zeroing)
Alternate mechanism to copy data across banks(pipelined serial mode – lower benefits than Fast Parallel)
Vivek Seshadri – Thesis Proposal
End-to-end System Design
• Software interface
– memcpy and meminit instructions
• Managing cache coherence
– Use existing DMA support!
• Maximizing use of Fast Parallel Mode
– Smart OS page allocation
28
Vivek Seshadri – Thesis Proposal
Applications Summary
29
0
0.2
0.4
0.6
0.8
1
bootup compile forkbench mcached mysql shell
Fra
cti
on
of
Me
mo
ry T
raff
ic
Zero Copy Write Read
Vivek Seshadri – Thesis Proposal
Results Summary
30
0%
10%
20%
30%
40%
50%
60%
70%
bootup compile forkbench mcached mysql shell
Co
mp
are
d t
o B
aselin
e
IPC Improvement Memory Energy Reduction