DSP/BIOS System Integration Workshop
Copyright © 2004 Texas Instruments. All rights reserved. T TO
Technical Training Organization 1
1. Introduction2. Real-Time System Design Considerations3. Hardware Interrupts (HWI)4. Software Interrupts (SWI)5. Task Authoring (TSK)6. Data Streaming (SIO) 7. Multi-Threading (CLK, PRD)8. BIOS Instrumentation (LOG, STS, SYS, TRC)9. Static Systems (GCONF, TCONF)10. Cache (BCACHE)11. Dynamic Systems (MEM, BUF)12. Flash Programming (HexAIS, Flashburn)13. Inter-Thread Communication (MSGQ, ...) 14. DSP Algorithm Standard (XDAIS)15. Input Output Mini-Drivers (IOM) 16. Direct Memory Access (DMA)17. Review
Learning Objectives
Describe the basic concepts of SWIs Demonstrate how to post a SWI Describe the SWI object List other SWI post options Show how QUEues pass data between threads Add a SWI to an HWI-based system
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Organization 2
HWI
SWI 2
SWI 1
IDL
time
Highest Priority
Lowest Priority
RunningReady
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Organization
Software Interrupts
Concepts Posting a SWI SWI Object Other SWI Posts Queues - QUE Lab
3
New Paradigm: DSP/BIOS Scheduler main()
{initwhile(1)
if(flag=1)
processprintf()
other...}
SWI_post is equivalent to setting ISR flag Scheduler replaces the while loop SWI manager is like ‘if’ test with no overhead
ISRget buffer
flag =1
main(){
init}
SWIfilterLOG_printf()
HWIget bufferSWI_post
IDLother
+ instrumentation
BIO
S Scheduler
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Organization 4
Hardware and Software Interrupt System
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Organization
HWI Fast response to
interrupts Minimal context
switching High priority for CPU Limited number of HWI
possible
SWI Latency in response time Context switch
performed Selectable priority levels Execution managed by
scheduler
DSP/BIOS provides for HWI and SWI management DSP/BIOS allows the HWI to post an SWI to the ready queue
Execution flow for flexible real-time systems:
INT ! Hard R/T Process Post SWI Cleanup, RETURN
Continue Soft R/T Processing ...SWI Ready
HWI
SWI{*buf++ = *SPRR;count--;if (count = = 0) {
SWI_post(&swiFir);count = COUNT;buf = &buf2;}
}
5
DSP/BIOS Preemptive SchedulerHardware Interrupts (HWI) Urgent response time Often at “sample rate” Microseconds duty cycle Preemptive or non-preemptive
Software Interrupts (SWI) Flexible processing time Often at “frame rate” Milliseconds duty cycle Preemptive
Idle (IDL) Best Effort Sequential Execution
SWI_ post()
Foreground
Background
Hard Real-time
Soft Real-time
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Organization 6
HWI
SWI
IDL
BIOS: Prioritized Scheduling
Highest Priority
Lowest Priority
HWI Collect data into frame/buffer, perform minimum processing SWI Process each datum in buffer IDL Runs when no real-time events are active HWI preempt SWI - new data is not inhibited by processing of frame
RunningReady
Legend
Collect Samples Post SWI Process Buffer
time
8 9 1 2 3
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Organization 7
State Diagrams: IDL, HWI, SWI IDL
Lowest priority - soft real-time - no deadline Idle functions executes sequentially Priority at which real-time analysis is passed to host
HWI & SWI Encapsulations of functions with priorities managed by DSP/BIOS kernel Run to completion (cannot be suspended or terminated prior to completion) Runs only once regardless of how many times posted prior to execution
Return from main( )Inactive Ready Runnin
gStartedResume
Preempted
StartedResumeInactive Ready Runnin
g
Completed
Posted
Preempted
Created
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Organization 8
HWI
SWI 2
SWI 1
IDL
time
Highest Priority
Lowest Priority
RunningReady
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Organization
Software Interrupts
Concepts Posting a SWI SWI Object Other SWI Posts Queues - QUE Lab
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HWI
SWI_a (p1)
IDL
SWI_b (p2)
Scheduling RulesHighest Priority
Lowest Priority
RunningReady
Legend
SWI_post(&mySwi) : Unconditionally post a software interrupt (in the ready state) If a higher priority thread becomes ready, the running thread is preempted SWI priorities from 1 to 14 Automatic context switch (uses system stack)
time
SWI_post(&SWI_b)
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Organization 10
HWI
SWI_a (p1)
IDL
SWI_b (p1)
Scheduling RulesHighest Priority
Lowest Priority
RunningReady
Legend
Processes of same priority are scheduled first-in first-out
time
SWI_post(&SWI_b)
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Organization 11
HWI
SWI_a (p1)
IDL
SWI_b (p2)
Posting a SWI from an HWIHighest Priority
Lowest Priority
Problem: Scheduler not aware of interrupt! If ISR posts a higher priority SWI, the scheduler will run that
SWI in the context of the HWI - not usually desired
RunningReady
Legend
SWI_post(&SWI_b)
time
?
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Organization 12
HWI
SWI_a (p1)
IDL
SWI_b (p2)
Using the Dispatcher with HWIHighest Priority
Lowest Priority
Solution: Use the Dispatcher Some APIs that may affect scheduling: SWI_post,
SWI_andn, SWI_dec, SWI_inc, SWI_or, SEM_post,PIP_alloc, PIP_free, PIP_get, PIP_put, PRD_tick
RunningReady
Legend
SWI_post()
time
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Organization 13
Scheduling Strategies Most important “Deadline Monotonic”
Assign higher priority to the most important process Rate monotonic analysis
Assign higher priority to higher frequency events Events that execute at the highest rates are assigned
highest priority An easy way to assign priorities in a system! Systems under 69% loaded guaranteed to run
successfully (proofs for this in published papers) Also allows you to determine scheduling bounds
Dynamic priorities Raise process priority as deadline approaches
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Organization 14
DSP/BIOS: Priority-Based Scheduling
HWI 1
HWI 2
SWI 3
SWI 2
SWI 1
MAIN
IDLE
SWI_post(&swi_name);
int2
rtn
post2 rtn
int1
post3 rtn
post1 rtn
rtn
rtn
Click here to skip animationT TOTechnical Training
Organization 15
Another Scheduling Example
HWI 1
HWI 2
SWI 3
SWI 2
SWI 1
MAIN
IDLE
rtn
int1
post2 rtn
post1 rtn
rtn
int2
int2
rtn
rtn
post2 rtn
rtn
rtn
post3
post1
The BIOS Execution Graph provides this kind of information to assist in temporal debugging
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Organization 17
HWI
SWI 2
SWI 1
IDL
time
Highest Priority
Lowest Priority
RunningReady
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Organization
Software Interrupts
Concepts Posting a SWI SWI Object Other SWI Posts Queues - QUE Lab
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Creation of SWI with Configuration Tool
Creating a new SWI1. right click on SWI mgr2. select “Insert SWI”3. type SWI name4. right click on new SWI5. select “Properties”6. indicate desired • function• priority• mailbox value
SWI_Obj...fxnprioritymailboxarg0arg1...T TO
Technical Training Organization 19
SWI Attributes : Manage SWI Properties
Allows programmer to inspect and modify key SWI object values
Do not modify fields on preempted or ready to run SWIrecommended: implement during lower priority thread
Priority range is 1 to 14, inclusive Example - changing a SWI’s priority to 5 :
extern SWI_Obj swiProcBuf; SWI_Attrs attrs; SWI_getattrs (&swiProcBuf, &attrs); attrs.priority = 5; SWI_setattrs (&swiProcBuf, &attrs);
fxnarg0arg1
prioritymailbox
SWI_Attrs SWI_Obj...fxnprioritymailboxarg0arg1...
get
set
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SWI Structures (from swi.h and fxn.h)typedef struct SWI_Attrs {
SWI_Fxn fxn; Arg arg0;Arg arg1;Int priority;Uns mailbox;
} SWI_Attrs;typedef struct SWI_Obj {Int lock; Ptr ready; Uns mask; priority Ptr link; Uns initkey; reset value for SWI mailboxUns mailbox; SWI mailbox - used with SWI_or, etcFXN_Obj fxnobj;Int stslock; STS_Obj *sts; implicit SWI statistical object
} SWI_Obj;
typedef struct FXN_Obj {Fxn fxn;Arg arg1;Arg arg0;
} FXN_Obj;
SWI_Attrs contains the most commonly used SWI object elements
SWI_getattrs and SWI_setattrs allow well defined access to these elements
SWI object can be directly access also, if desired, as per these examples:
myValue = mySwi.fxnobj.arg1;mySwi.fxnobj.arg0 = 7;
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Organization 21
Managing Thread Priorities via GCONF Drag-and-drop SWIs in list to vary priority Priorities range from 1–14
Scheduler is invoked when SWI is posted When scheduler runs, control is passed to the highest priority thread Equal priority SWIs run in the order postedT TO
Technical Training Organization 22
HWI
SWI 2
SWI 1
IDL
time
Highest Priority
Lowest Priority
RunningReady
T TOTechnical Training
Organization
Software Interrupts
Concepts Posting a SWI SWI Object Other SWI Posts Queues - QUE Lab
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SWI Post and SWI Mailbox Overview
If the value of the mailbox is needed by the SWI, use SWI_getmbox() which returns the value of the mailbox when the SWI was posted.
Note: this is a ‘shadow’ value for use within the SWI – BIOS manages a second mailbox for the next posting of the SWI
After each posting, the mailbox is reset to the initial condition specified in the SWI object
Mailbox function Bitmask Counter Not Used
Always Post SWI_or SWI_inc SWI_post
Post on mailbox = 0 SWI_andn SWI_dec
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Organization
API Allows you to :SWI_inc Know how many times the SWI was posted before it ranSWI_dec Post N times before the SWI is scheduled – a countdownSWI_or Send a single value to the SWI when posting - signatureSWI_andn Only post the SWI when multiple posters all have posted
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SWI API Summary
SWI_post Post a software interrupt SWI_andn Clear bits from SWI's mailbox; post if becomes 0 SWI_or Or mask with value contained in SWI's mailbox field SWI_inc Increment SWI's mailbox value SWI_dec Decrement SWI's mailbox value; post if becomes 0 SWI_getattrs Copy SWI attribute from SWI object to a structure SWI_setattrs Update SWI object attributes from specified structure SWI_getmbox Obtain the value in the mailbox prior to SWI run
SWI API Description
SWI_create Create a SWI SWI_delete Delete a SWI SWI_disable Disable software interrupts SWI_enable Enable software interrupts SWI_getpri Return a SWI’s priority mask SWI_raisepri Raise a SWI’s priority SWI_restorepri Restore a SWI’s priority SWI_self Return current SWI’s object handle
Mod 11
Mod 7
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Organization 25
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Organization
Software Interrupts
Concepts Posting a SWI SWI Object Other SWI Posts Queues - QUE Lab
26
msg1 msg2 msg3QUE_Obj
struct MyMessage { QUE_Elem elem; first field for QUE Int x[1000]; array/structure sent not copy based!} Message1;
typedef struct QUE_Elem { struct QUE_Elem *next; struct QUE_Elem *prev;} QUE_Elem;
Queue Concepts QUE message is anything you like, starting with QUE_Elem QUE_Elem is a set of pointers that BIOS uses to manage a double linked list Items queued are NOT copied – only the QUE_Elem ptrs are managed!
QUE_put(hQue,*msg3) add message to end of queue (writer)
*elem = QUE_get(hQue) get message from front of queue (reader)
msg1 msg2 msg3QUE_Obj
How do you synchronize reader and writer?T TO
Technical Training Organization 27
Queue Usage
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Organization
QUE Properties any number of messages can be passed atomic API assure correct sequencing no intrinsic semaphore
Using QUE Declare the QUE via the config tool Define (typedef) the structure to queue – 1st element must be “QUE_Elem” Fill the message(s) to QUE with the desired data Send the data to the queue via QUE_put(&myQue, msg); Acquire data from the queue via info=QUE_get(&myQue);
Application Considerations Two queues are needed to circulate messages between two threads
typedef struct MsgObj { QUE_Elem elem; short *pInBuf; short *pOutBuf; } MsgObj, *Msg;
toDevQ
toProcQSWI
put
get
get
put
HWI
Main(init)
putput1
2
3
5
4
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Queue Lab Steps
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Organization 28
GCONF: 1. Declare 2 QUEues called toDev and toProcABOVE MAIN: 2. Declare 2 Input Buffers and 2 Output Buffers
3. Define a message structure to send over the QUEs:- first element of a QUE message must be of type QUE_Elem- 'payload' in this lab will be 2 pointers ( *pIn, *pOut )
4. Declare, as globals, an array of two messages of the type created aboveIN MAIN: 5. Initialize the pointers in message 1 to point to in/out buffers 1
6. Initialize the pointers in message 2 to point to in/out buffers 27. "Prime" the toDev QUE with the two messages
HWI CODING: 8. At the top of the HWI, if the current buffer size drops to 0:- get a new message from the toDev QUE- extract the input buffer pointer from the message - extract the output buffer pointer from the message- as before, each time the HWI is posted:
- fill 1 new input buffer word- output 1 output buffer word
9. At the bottom of the HWI, if the current buffer is full:- send the message with the current pointer set to the SWI via the toProc QUE- zero the buffer size counter
SWI CODING: 10. At the top of the SWI, get a message from the toProc QUE- extract the input buffer pointer from the message - extract the output buffer pointer from the message- as before, FIR filter the input buffer & store results to the output buffer
11. At the end of the SWI, return the message to the HWI via the toDev QUE
QUE API Summary
QUE_put Add a message to end of queue – atomic write QUE_get Get message from front of queue – atomic read
QUE_enqueue Non-atomic QUE_put QUE_dequeue Non-atomic QUE_get QUE_head Returns ptr to head of queue (no de-queue performed) QUE_empty Returns TRUE if queue has no messages QUE_next Returns next element in queue QUE_prev Returns previous element in queue QUE_insert Inserts element into queue in front of specified element QUE_remove Removes specified element from queue QUE_new ….
QUE API Description
QUE_create Create a queue QUE_delete Delete a queue
Mod 11
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Organization 29
HWI
SWI 2
SWI 1
IDL
time
Highest Priority
Lowest Priority
RunningReady
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Organization
Software Interrupts
Concepts Posting a SWI SWI Object Other SWI Posts Queues - QUE Lab
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Block FIR Filter Overview Read block of data to input buffer
A/D
SP
HWI
0000012345......9596979899
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Organization 31
x c0 +x c1 +x c2 +x c3 +x c4 =
Block FIR Filter Overview Read block of data to input buffer Convolve 1st N samples with coefficients Store result to 1st location of output buffer
A/D
SP
HWI0
0000012345......9596979899
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Organization 32
x c0 +x c1 +x c2 +x c3 +x c4 =
Block FIR Filter Overview Read block of data to input buffer Convolve 1st N samples with coefficients Store result to 1st location of output buffer Repeat convolution advanced by 1 sample Store result to 2nd location of output buffer
A/D
SP
HWI01
0000012345......9596979899
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Organization 33
x c0 +x c1 +x c2 +x c3 +x c4 =
Block FIR Filter Overview Read block of data to input buffer Convolve 1st N samples with coefficients Store result to 1st location of output buffer Repeat convolution advanced by 1 sample Store result to 2nd location of output buffer Repeat for BLOCKSIZE iterations
A/D
SP
HWI012
0000012345......9596979899
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Organization 34
x c0 +x c1 +x c2 +x c3 +x c4 =
Block FIR Filter Overview Read block of data to input buffer Convolve 1st N samples with coefficients Store result to 1st location of output buffer Repeat convolution advanced by 1 sample Store result to 2nd location of output buffer Repeat for BLOCKSIZE iterations
A/D
SP
HWI0123
0000012345......9596979899
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Organization 35
x c0 +x c1 +x c2 +x c3 +x c4 =
Block FIR Filter Overview Read block of data to input buffer Convolve 1st N samples with coefficients Store result to 1st location of output buffer Repeat convolution advanced by 1 sample Store result to 2nd location of output buffer Repeat for BLOCKSIZE iterations
A/D
SP
HWI01234
0000012345......9596979899
45......9596979899
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Organization 36
x c0 +x c1 +x c2 +x c3 +x c4 =
Block FIR Filter Overview Read block of data to input buffer Convolve 1st N samples with coefficients Store result to 1st location of output buffer Repeat convolution advanced by 1 sample Store result to 2nd location of output buffer Repeat for BLOCKSIZE iterations Send output buffer to DAC
A/D
SP
HWI012345......9596979899
SP
D/A
HWI
0000012345......9596979899
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Organization 38
x c0 +x c1 +x c2 +x c3 +x c4 =
Block FIR Filter Overview Read block of data to input buffer Convolve 1st N samples with coefficients Store result to 1st location of output buffer Repeat convolution advanced by 1 sample Store result to 2nd location of output buffer Repeat for BLOCKSIZE iterations Send output buffer to DAC Copy last N-1 samples to history pre-buffer
SP
HWI012345......9596979899
SP
D/A
HWI
96979899012345......9596979899
A/D
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Organization 39
Block FIR Filter Overview Read block of data to input buffer Convolve 1st N samples with coefficients Store result to 1st location of output buffer Repeat convolution advanced by 1 sample Store result to 2nd location of output buffer Repeat for BLOCKSIZE iterations Send output buffer to DAC Copy last N-1 samples to history pre-buffer Repeat above steps...
SP
HWI
SP
D/A
HWI
96979899100101102103104105......
195196197198199
A/D
x c0 +x c1 +x c2 +x c3 +x c4 = 100
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Organization 40
4
46
Double Buffer Management
processBufferFIR
DataInDataIn
12
2
3
1. Get block of data2. Start collecting next block
while processing data3. Prime for next block4. Start collecting next block
while processing data5. Prime for next block6. ...
Make data buffers size of block plus history
Collect data in last ‘blocksize’ locations
After buffer is processed, copy last ‘history’ values to top of other buffer
123...910
111213..1920
910
5
1920212223...2930
313233...3940
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Organization 41
Interlaced Stereo Double Buffers
0000
L1R1L2R2. . .L8R8L9R9L10R10
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Organization
L9R9L10R10L11R11L12R12. . .L18R18L19R19L20R20
#define FIRSZ64#define HIST (2*FIRSZ-2)
short in[2][2*BUF+HIST];short out[2][2*BUF];
for ( i = 0; i < HIST; i++ )pIn[i-HIST]= pPriorIn[i+2*BUF-HIST];
pPriorIn = pIn;
fir(pIn-HIST , &coeffs[cSet][0], pOut , FIRSZ, BUF);
fir(pIn+1-HIST, &coeffs[cSet][0], pOut+1, FIRSZ, BUF);
Note: the driver will be passed the address where new data is to be collected. Only the SWI will be aware of the history segment that precedes it.
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Lab 4: Software Interrupts - SWI
Create project using given SWI-based code Build, download, and test on the EVM Add QUEs to pass buffers between HWI and SWI Build, load, test, note differences
BIOS\Labs\WorkHWI 4
swiProcBufprocBuf procBufs=QUE_get(&qProc); pIn = procBufs->pInBuf; for (i =0, i<HIST; i ++) pIn][i]=pPriorIn][2*BUF-HIST]; if( sw0 == 1 ) FIR(in[pIn-HIST],out[pOut]) else {pOut[i]=pIn[i]}
AudioOut
(48 KHz)
ADCAIC33
AudioIn
(48 KHz)McBSP
DRR
FIR.cFIR Code
DACAIC33
McBSPDXR
mcbsp.c
coeffs.cCoefficients
BIOS\Labs\HW
BIOS\Labs\Algos
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Organization
isrAudioin[buf][i]=MCBSP1_DRRMCBSP1_DXR = out[buf][i])if(bkCount==BKSZ) QUE_put(&qProc,intBufs); SWI_post(&swiProcBuf);
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Lab 4a : procBuf() as a SWI
44
void procBuf (short i; // loop index counterstatic short *pPriorIn=&in[1][0]; // points to buf with hist datafor ( i = 0; i < HIST; i++ ) // for all values in history,
pIn[i-HIST]= pPriorIn[i+2*BUF-HIST]; // copy end old buf to top newpPriorIn = pIn; // cur.buf. is next 'old' bufif( sw0 == 1 ){ // if SW0 down
fir(pIn-HIST, &coeffs[sw1][0], pOut, FIRSZ, BUF); // FIR – Lfir(pIn+1-HIST, &coeffs[sw1][0], pOut+1, FIRSZ, BUF); // FIR – R
}else { // if SW0 is up, copy in to out
for( i = 0; i < 2*BUF; i++ ) // for all new L&R data,pOut[i] = pIn[i]; // copy in buf to out buf
}}
void isrAudio (void){static int dataIn, dataOut; // for read/write to McBSP CSLstatic short bkCnt = 0; // monitors # samples collectedstatic short *pInBuf, *pOutBuf; // ptr to avail. in/out bufsstatic Bool N=0;if( bkCnt == 0 ) { // if there is no current buf
pInBuf = &in[N][HIST]; // get in buf addresspOutBuf = &out[N][0]; } // get out buf address
dataIn = MCBSP1_DRR_32BIT; // get a stereo sample pInBuf[ bkCnt] = (short)dataIn; // add L sample to L blockpInBuf[ bkCnt+1] = (short)(dataIn>>16); // R sample to R blockdataOut = 0x0000FFFF & pOutBuf[bkCnt]; // get L result dataOut |= 0xFFFF0000 & (pOutBuf[bkCnt+1]<<16); // append R resultMCBSP1_DXR_32BIT = dataOut; // send stereo value to DACbkCnt+=2; // inc.bk.ctr. by TWO samplesif( bkCnt >= 2*BUF ) {
pIn = &in[N][HIST]; // get in buf addresspOut = &out[N][0]; // get out buf addressN^=1;SWI_post(&swiProcBuf); // schedule SWI to process bufsbkCnt = 0; } // reset bk.ctr. for new buf's
}
Lab 4b : Adding QUEues
45
void isrAudio (void){static int dataIn, dataOut; // for read/write to McBSP CSLstatic short bkCnt = 0; // monitors # samples collectedstatic short *pInBuf, *pOutBuf; // ptr to avail. in/out bufsstatic Msg intBufs; // ptr to struc of type MsgObjif( bkCnt == 0 ){ // if there is no current buf
intBufs = QUE_get(&qDev); // get set of buf ptrs from QpInBuf = intBufs->pInBuf; // get in buf addresspOutBuf = intBufs->pOutBuf; } // get out buf address
dataIn = MCBSP1_DRR_32BIT; // get a stereo sample pInBuf[ bkCnt] = (short)dataIn; // add L sample to L blockpInBuf[ bkCnt+1] = (short)(dataIn>>16); // R sample to R blockdataOut = 0x0000FFFF & pOutBuf[bkCnt]; // get L result dataOut |= 0xFFFF0000 & (pOutBuf[bkCnt+1]<<16); // append R resultMCBSP1_DXR_32BIT = dataOut; // send stereo value to DACbkCnt+=2; // inc.bk.ctr. by TWO samplesif( bkCnt >= 2*BUF ){ // when the dbl block is full
QUE_put(&qProc, intBufs); // get out buf addressSWI_post(&swiProcBuf); // schedule SWI to process bufsbkCnt = 0; } // reset bk.ctr. for new buf's
}void procBuf(){
short i; // loop index counterstatic short *pPriorIn=&in[1][0]; // points to buf with hist datastatic Msg procBufs; // ptr to struc of type MsgObjprocBufs = QUE_get(&qProc); // get a pair of bufs from HWIpIn = procBufs->pInBuf; // get in buf addresspOut = procBufs->pOutBuf; // get out buf addressfor ( i = 0; i < HIST; i++ ) // for all values in history,
pIn[i-HIST]= pPriorIn[i+2*BUF-HIST]; // copy end old buf to top newpPriorIn = pIn; // cur.buf. is next 'old' bufif( sw0 == 1 ) { // if SW0 down
fir(pIn-HIST, &coeffs[sw1][0], pOut, FIRSZ, BUF); // FIR – Lfir(pIn+1-HIST, &coeffs[sw1][0], pOut+1, FIRSZ, BUF); } // FIR - R
else { // if SW0 is up, copy in to outfor( i = 0; i < 2*BUF; i++ ) // for all new L&R data,
pOut[i] = pIn[i]; } // copy in buf to out bufQUE_put(&qDev, procBufs); // send bufs back to HWI
}
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Technical TrainingOrganization
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Lab Details
Filter Debug ReleaseOff 18% 4.7%On 61% 6.5%
HWI – based lab 3
Filter Debug ReleaseOff 3.8% 2.3%On 45% 3.7%
SWI – based lab 4
Observations: Adding SWI dropped CPU load in all casesIn addition, it greatly increases HWI response time, reduces interrupt latency, spreads instantaneous demand into average demand, lowering required processor speed greatly in most systems !
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