The George Washington UniversitySchool of Engineering and Applied Science
Department of Electrical and Computer Engineering
ECE122 – 30
Lab 2: NAND gate design using CMOS
Ritu Bajpai
September 11, 2008
Propagation Delay
• Propagation Delay is the amount of time it takes a change of input to appear as a change on the output.
• Propagation Delay is measured from the 50% point on the input signal to the 50% point on the output.
Input
Output
tpHL
Transition time
• High-low and low high transition times at the output of a gate are defined as tHL and tLH between the 10% and 90% points.
tLH
10%90%
tHL
10%90%
Gate Delay
• The load capacitance severely affects the gate delay.
Inv1
Inv2
Objective for our simulation
• Create a NAND gate using p and n MOSFET and testing its performance.
• Testing the performance of a NAND gate from SCMOS library.
• Comparing the performance of the two NAND gates.
Note parameters W=2.50u and L=0.25u
NAND GATE
TEST BENCH FOR THE NAND GATE
NAND GATE
TEST BENCH FOR NAND GATE
NAND GATE
TEST BENCH FOR NAND GATE
tpHL
Record the propagation delay
• Record tpHL and tpLH for the NAND gate.
• Record the waveform for the same.
• Next we will use the same test bench for the NAND gate from the LogicGates library
• Record the values of tpHL and tpLH in 2 cases.
Replace your NAND gate by the NAND gate in the library LogicGates
Analysis/Result
• Is the rise time and fall time of each gate same, if no then why?
• Is the rise time and fall time of both the gates similar to each other, if no then what could be the probable reasons for the difference?
Analysis/Result
• Repeat the simulation to create a NOR gate using CMOS.
• In the test circuit, replace your NOR gate by the NOR gate in SCMOS library.
• Record the waveform in the two cases and make the similar observations as you made for NAND gate.