1
2009
ELT2034: Digital DesignLecture 1: Course OverviewSpring 2012
Xuan-Tu Tran, PhD
Faculty of Electronics and Telecommunication (FET)
Key Laboratory for Smart Integrated Systems (SIS Lab)
VNU University of Engineering and Technology
Email: [email protected]
www.uet.vnu.edu.vn/~tutx
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General Information
� Instructor� Xuan-Tu Tran, PhD
� Office: Room 314, Building G2 (by appointment)
� Tel.: +84-4-3754 9664 (Office)
� Email: [email protected] (recommended)
� Home page: http://www.uet.vnu.edu.vn/~tutx
� Course Web Page� BBC system + homepage (please visit my homepage first)
� http://www.bbc.vnu.edu.vn
� Teaching Assistants� Ngoc-Mai Nguyen, MSc., Research engineer, PhD stude nt (SIS Lab)
� Van-Mien Nguyen, Research engineer, M.Sc. student ( SIS Lab)
� Duy-Hieu Bui, Research engineer, MSc. (SIS Lab)
� Van-Huan Tran, Research engineer (SIS Lab)
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Administrative Details
� Grading
� Take-Home Entry ExamPass condition
� Project Exams 40%
� Final Exam (writing) 60%
� Students have to be present:
� at least 80% of the course meetings
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Administrative
� Office: � Room 314, G2 building, UET campus
� Office hours� By appointment
� Sending e-mails is a good way to reach me
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Ressources
� IEEE Standard 1076-1993� Find using search engines on WWW (Google)
� Use my homepage’s resources, too much digest
� Xilinx FPGA� EDA/CAD tools: ISE foundation suite, EDK (student edition); ModelSim
(Mentor Graphics – student edition)
� Development Kit: Spartan-3E development kits (Xilinx), DE2 (Altera), or Actel
� Schematic, FSM, VHDL…
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Honor
� You are encouraged to collaborate with other studen ts in projects
� Final VHDL code, project report for each homework s hould be done by your self
� Exams are closed book, closed notes… (only pen, blan k paper, and a prepared computer are allowed)
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Administration
� Text books
� Digital Design: Principles and Practices (4th edition), ISBN 0-13-186389-4
� By John F. Wakerly, Prentice Hall, June 2010
� Available at Laboratory for Smart Integrated Systems
� References
� Digital Design Fundamentals
� By Kenneth J. Breeding, 2nd Ed., Prentice Hall, 1992
� Available at Laboratory on Smart Integrated Systems
� VHDL: Programming by Example
� By Douglas L. Perry, McGraw-Hill, ISBN: 0-071-40070-2
� Available at the Smart Integrated Systems Laboratory
� Wai-Kai Cheng (Editor). Logic Design. CRC Press, ISBN: 0-8493-1734-7,
2003.
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Course objectives
� Students should be able to…
� Analyzing digital systems
� Understanding numbering systems, Boolean Algebra (conversion,
calculation)
� Designing, analyzing combinational circuits (adders, multiplexers…)
� Designing, analyzing sequential circuits (flip-flops, registers, counters,
FSM, ALU, processors…)
� Hardware description languages and EDA/CAD tools
� Build their own projects and report related matters
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Course outline
� Introduction
� Numbering Systems and Codes
� Digital Circuits
� Boolean and Switching Algebra
� Combinational logic design principles
� Hardware description languages
� Combinational logic design practices
� Sequential logic design principles
� Sequential logic design practices
� Memory, CPLD, and FPGAs
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Introduction to Digital Systems
� What is a digital system?
� Why are digital systems so pervasive ( to be present
everywhere)?
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Microelectronics / VLSI Circuits Design
� Why is Microelectronics / VLSI Circuits Design impo rtant?
� Integrated Circuits (ICs) can be found in any applications
� High income 33 973M US$
20 137M US$
8 137M US$
[LaPedus - EETimes]
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Examples
WiFi routers(Communication)
VLSI Systems(Systems-on-Chip)
Digital TVs(Multimedia)
MP3 Players(Multimedia)
Mobile phone(Telecoms, Multimedia) Washing machine
(Customer Electronics)
Automobile applications
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IC products
� Processors
� CPU, DSP, Controllers
� Memory chips
� RAM, ROM, EEPROM
� Analog
� Mobile communication,
audio/video processing
� Programmable
� PLA, FPGA
� Embedded systems
� Used in cars, factories
� Network cards
� System-on-chip (SoC)
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- What is a digital system?
� A system that processes discrete information
� Discrete entities may represent anything
� from simple arithmetic integers, letters of the alphabet, or other abstract
symbols … to values for a voltage, a pressure, or any other physical
quantities.
� What these entities represent is not important in processing of the
information.
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- What is a digital system?
“A digital system is one that accepts as input digital information representing numbers, symbols, or physical quantities,
processes this input information in some specific manner,
and produces a digital output.”
Digital SystemDigitalinputs
Digitaloutputs
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- What is a digital system? (cont’.)
� Computer applications� The computer is required to process information related to physical
quantities (pressure or temperature).
� Physical quantities & computer
Computer Nature: physical quantities
Discrete (digital) quantities Continuous variables (analog quantities)
Nature(analog)
Nature(analog)
??? ???
Computer (digital)
Physical quantities must be converted to a digital f orm !!!
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- What is a digital system? (cont’.)
� Thermocouple in an analog system
How does this thermocouple be used in a digital sys tem?
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- What is a digital system?
� Converting a physical quantity to a digital form� Physical quantity � voltage/current (by a transducer)
(coming energy in one form to going energy in another form)� Ex.: thermocouple (temperature transducer)
� Output voltage is proportional to the temperature
� Voltage/Current � Digital form (by an analog-to-digital converter)
ADCADC Computer DACDACAnalog
quantities(voltage, current…)
Analogquantities
(voltage, current…)
(‘0’ & ‘1’)
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Parallel-comparator ADC converter
� 2-bit parallel-comparator ADC use 3 parallel
comparators
� Use resistors to divide voltage in order to
provide reference voltages to comparators
� Full-scale voltage equals V Max (the voltage
at the top resistor)
� Incoming voltage is provided to non-invert
input of comparators
� Outgoing value at the output of a
comparator gets ‘high’ when its incoming
voltage is higher than its reference voltageEx.: VIN = 2.6 Volt �
A3: Low
A2: High
A1: High
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Examples
� Monitoring the environment for the developer used o n a
photographic processing lab
� We must to measure the temperature of the developer
� Then, use the results to turn on/off a heating element
Photographicprocessing
Lab
H2
H1
SS
SSMonitoring & Control
System
SensorsHeater
Heater
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Examples (cont’.)
� ATM (Automatic Teller Machine)
� We must to measure the temperature of the environment surrounding
ATMs
� Then, use the results to turn on/off air-conditioners
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- Why are digital systems so pervasive?
� Flexibility
� Reliability
� Cost
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Design and fabricating ICs
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Design: history and jobs
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The VLSI Design Process
� Move from higher to lower levels of abstraction
� Use CAD tools to automate parts of the process
� Use hierarchy to manage complexity
� Different design styles trade off:
� Design time
� Non-recurring engineering (NRE) cost
� Unit cost
� Performance
� Power Consumption
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VLSI Levels of Abstraction
Specification(what the chip does, inputs/outputs)
Architecturemajor resources, connections
Register-Transferlogic blocks, FSMs, connections
Circuittransistors, parasitics, connections
Layoutmask layers, polygons
Logicgates, flip-flops, latches, connections
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VLSI / ASIC design flow
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Designers – Tasks – Tools
Define Overall Chip
C/RTL Model
Initial Floorplan
Cell Libraries
Circuit Schematics
Megacell BlocksCircuit Simulation
Layout and Floorplan
Place and Route
Parasitics Extraction
DRC/LVS/ERC
Behavioral Simulation
Logic Simulation
Synthesis
Datapath Schematics
RTL Simulator
Synthesis Tools
Timing AnalyzerPower Estimator
Text EditorC Compiler
Schematic Editor
Circuit SimulatorRouter
Designer Tasks Tools
Architect
LogicDesigner
DesignerCircuit
PhysicalDesigner
Place/Route ToolsPhysical Design and Evaluation Tools
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VLSI Design Tradeoffs
� Non-Recurring Engineering (NRE) Costs
� Design Costs
� Mask “Tooling” costs
� Unit Cost - related to chip size
� Amount of logic
� Current technology
� Performance
� Clock speed
� Implementation
� Power consumption
� Power supply voltage
� Clock speed
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Design Methodologies
� Top-Down Design Method
� High level functions are defined first
� Lower level implementation details are filled in later
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Design Methodologies (cont’.)
� Bottom-Up Design Method
� Low level functions are defined and finished first
� High level implementation are completed in later
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VLSI Trends: Moore’s Law
� In 1965, Gordon Moore predicted that transistors would
continue to shrink, allowing:
� Doubled transistor density every 18-24 months
� Doubled performance every 18-24 months
� History has proven Moore right
� But, is the end is in sight?
� Physical limitations
� Economic limitations
No exponentialis forever,
BUT
Gordon MooreIntel Co-Founder and Chairmain Emeritus
Image source: Intel Corporation www.intel.com
Your job isto postpone“forever”!
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Moore law
- Feature sizes are getting smaller :- 0.25 µm, 0.18 µm, 0.12µm, 90nm, 65nm, 45nm, 32nm
- Gates counts and memory sizes are increasing :- 10M, 20M, 100M, …1 G!
- Clock speeds are increasing : - 100Mhz, 400Mhz, 1 GHz, 3 GHz,…
- Power cannot increase at the same pace :
- 10W, 20W, 50W, 100W, …- Design time cannot increase :
- 3m, 6m, 12m… !!!
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Microprocessor Trends (Intel)
Source: http://www.intel.com/pressroom/kits/quickreffam.htm, media reports
Year Chip L transistors
1971 4004 10µm 2.3K
1974 8080 6µm 6.0K
1976 8088 3µm 29K
1982 80286 1.5µm 134K
1985 80386 1.5µm 275K
1989 80486 0.8µm 1.2M
1993 Pentium® 0.8µm 3.1M
1995 Pentium® Pro 0.6µm 15.5M
1999 Mobile PII 0.25µm 27.4
2000 Pentium® 4 180nm 42M
2002 Pentium® 4 (N) 130nm 55M
2003 Itanium® 2 (M) 130nm 410M
2004 Pentium® 4 (P) 90nm 125M
2006 Core 2 Duo® 65nm 291M
“DeepSubmicron”
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Microprocessor Trends
0
10
20
30
40
50
60
70
80
90
100
1970 1980 1990 2000
Tra
nsis
tors
(M
illio
ns)
IntelMotorolaDEC/Compaq
Alpha (R.I.P)
P4
G4
Sources: http://www.intel.com/pressroom/kits/quickreffam.htm
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DRAM Memory Trends (Log Scale)
Source: Textbook, Industry Reports
0.0625
0.25
1
4
16
64128
256512
0.01
0.1
1
10
100
1000
1975 1980 1985 1990 1995 2000 2005
Size (Mb)
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Processor Performance Trends
Source: Hennesy & Patterson Computer Architecture:A Quantitative Approach, 3rd Ed., Morgan-Kaufmann, 2002.
Vax 11/780
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Summary - Technology Trends
� Processor
� Logic capacity increases ~ 30% per year
� Clock frequency increases ~ 20% per year
� Cost per function decreases ~20% per year
� Memory
� DRAM capacity: increases ~ 60% per year
(4x every 3 years)
� Speed: increases ~ 10% per year
� Cost per bit: decreases ~25% per year
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Technology Directions: SIA Roadmap
Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic trans/cm2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) 1.735 .580 .255 .110 .049 .022 #pads/chip 1867 2553 3492 4776 6532 8935 Clock (MHz) 1250 2100 3500 6000 10000 16900 Chip size (mm2) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf pow (W) 90 130 160 170 175 183
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Gallery - Early Processors
Mos Technology 6502
Intel 4004 (1971)First µP - 2300 xtors
L=10µm
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Intel 4004
� Introduction date:
November 15, 1971
� Clock speed: 108 KHz
� Number of transistors: 2,300
(10 microns)
� Bus width: 4 bits
� Addressable memory: 640 bytes
� Typical use:
calculator, first microcomputer
chip, arithmetic manipulation
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Gallery - Current Processors
Pentium® 442M transistors / 1.3-1.8GHz
49-55WL=180nm
Pentium® 4 “Northwood”55M transistors / 2-2.5GHz
55WL=130nm Area=131mm 2
Process Shrinks
Pentium® 4 “Prescott”125M transistors / 2.8-3.4GHz
115WL=90nm Area=112mm 2
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Pentium 4
� 0.18-micron process technology(2, 1.9, 1.8, 1.7, 1.6, 1.5, and 1.4 GHz)
� Introduction date: August 27, 2001 (2, 1.9 GHz); ...; November 20, 2000 (1.5, 1.4 GHz)
� Level Two cache: 256 KB Advanced Transfer Cache (Integrated)
� System Bus Speed: 400 MHz
� SSE2 SIMD Extensions
� Transistors: 42 Million
� Typical Use: Desktops and entry-level workstations
� 0.13-micron process technology(2.53, 2.2, 2 GHz)
� Introduction date: January 7, 2002
� Level Two cache: 512 KB Advanced
� Transistors: 55 Million
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Gallery - Current Processors
Intel Core 2 Duo “Conroe” 291M transistors / 2.67GHz / 65W
L=65nm Area=143mm 2 Image courtesy Intel Corporations All Rights Reserved
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Gallery - Current Processors
� Multi-core processors
� Increase performance
� Power consumption
� Challenges
� Complexity
� Tasks management
� On-chip communication
� Chip temperature
� etc.
Athlon 64 X2 4800+ and 4400+46
Gallery - Current Processors
Image courtesy International Business Machines All Rights Reserved
IBM Cell Processor234M transistors / 2GHz / ??W
L=90nm Area=221mm 2
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Gallery - Current Processors
� Intel Polaris (80 cores)
� Trillion operations/second
� Area: 275mm2
� Consumption: 62W
� IEEE SOC Conference (2006)
� Teraflop ASCI Red at Sandia
National Lab (1996)
� 104 cabinets housing 10,000 Pentium
Processors
� spread out over 2500 square feet
� It consumed a mere 500kw
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Gallery - Current FPGA
Xilinx Virtex FPGA
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Gallery - Graphics Processor
nVidia GeForce457M transistors / 300MHz / ??W
L=0.15µm
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FAUST chip
TX Units
RX Units
AHB System
ETH
DART
RAC
ARM
� Year: 2005
� 130 nm CMOS (STMicroelectronics)
� 20-node asynchronous NoC
� 23 NoC units
� AHB subsystem including an ARM946 core
� 24 clocks (DFS to save power)
� 8 M Gates (including 81 RAM blocks)
� Area : core ð 70 mm2 - chip ðððð 80 mm2
� 275 functional I/Os - Package : TBGA 420
� Power supplies: core ðððð 1.2 V – I/Os ð 3.3 V D. Lattard, et al. – ISSCC’07
Flexible Architecture of a Unified System for Telecoms
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FAUST Architecture
RAM IF
58 Pads
ETHERNET IF
17 Pads
Async/Sync IF
Async node
NOC2 IF
83 Pads
LIST
NoC
HouseKeeping
LETI
FT R&D
MITSUB-ITE
LETI
OFDMMOD.
ALAM.MOD.
CDMAMOD. MAPP.
BITINTER.
TURBOCODER
RAM CPU RAMEXT.RAMCTRL
AHB
ROTOR EQUAL.CHAN.EST.
CONV.DEC.
ETHERNET
FRAMESYNC.
ODFMDEM.
CDMADEM.
DE-MAPP.
DE-INTER.
DART
EXP
SPort
APort
NOC1 IF
84 PadsSPort
APort
RAC
NoCPerf.
EXP
CONV.CODER
Clk & Test CTRL
RAM IF
58 Pads
ETHERNET IF
17 Pads
Async/Sync IF
Async node
NOC2 IF
83 Pads
LIST
NoC
HouseKeeping
LETI
FT R&D
MITSUB-ITE
LETI
OFDMMOD.
ALAM.MOD.
CDMAMOD. MAPP.
BITINTER.
TURBOCODER
RAM CPU RAMEXT.RAMCTRL
AHB
ROTOR EQUAL.CHAN.EST.
CONV.DEC.
ETHERNET
FRAMESYNC.
ODFMDEM.
CDMADEM.
DE-MAPP.
DE-INTER.
DART
EXP
SPort
APort
NOC1 IF
84 PadsSPort
APort
RAC
NoCPerf.
EXP
CONV.CODER
Clk & Test CTRL