eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 1
eMMC5.1 PHY - Linux SW Guide
Version: 0.3
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 2
Contents 1 Introduction .......................................................................................................................................... 3
1.1 Purpose ......................................................................................................................................... 3
1.2 Scope ............................................................................................................................................. 3
1.3 Audience ....................................................................................................................................... 3
2 eMMC5.1 PHY Introduction .................................................................................................................. 3
3 eMMC5.1 PHY Internal Register Set ..................................................................................................... 4
4 eMMC5.1 PHY SDHC Registers ............................................................................................................ 25
5 eMMC5.1 PHY Programming Sequence .............................................................................................. 26
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 3
1 Introduction Arasan eMMC5.1 PHY provides an interface to the Arasan’s eMMC5.1 Host Controller to provide a seamless support for eMMC supporting HS400 data rates. The eMMC5.1 PHY also supports the HS200, DDR52 and legacy data
rates. The eMMC5.1 PHY includes the PADs for the CMD line, DAT[0..7] lines and the STRB line.
1.1 Purpose This document talks about the SW Programming sequence required in Linux
for the eMMC5.1 PHY to be interfaced with eMMC devices.
1.2 Scope This scope of the document is limited to describing the PHY register sets and programming details of the PHY. The design of PHY in the controller is out of
the scope of this document.
1.3 Audience The primary target audience would be Linux driver developers/application developers who use Arasan eMMC-PHY controller across PCI platform in Linux.
2 eMMC5.1 PHY Introduction
The Arasan eMMC5.1 PHY is a fully compliant PHY layer (with IO PADs) for JEDEC
eMMC5.1 specification and is also backward compliant to eMMC5.0, eMMC 4.51 and earlier versions of the specifications. This allows the designers of the SOC to easily support the eMMC Interface and optimize the performance and power while
maintaining interoperability with eMMC 5.0/eMMC5.1 devices.
The Arasan eMMC5.1 PHY got to be introduced in Linux to support eMMC5.1 devices that uses Arasan controllers. Above all, it requires programming of PHY register sets
for eMMC Initialization/functionalities to happen.
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 4
3 eMMC5.1 PHY Internal Register Set
Offset: 0x00: eMMC PHY DLL Controls/Status
Bit Name Access Default Description
0
Reserved RO 3'b000 Reserved for future use 1
2
3 DLL_EN RW 1'b0 DLL Enable 0: Disable
1: Enable
4 DLL_RDY RO 1'b0
DLL Ready
0: DLL Not Ready 1: DLL Ready
Usually this takes only few clocks and is ready within one Next Register Access
time.
5
FREQ_SEL[2:0] RW 3'b000
FREQ Select 3’b000: 200 MHz
3’b001: 100 MHz 3’b010: 50 MHz
3’b011-3’b111: Reserved
6
7
Table 1 eMMC PHY DLL Control/Status
Offset: 0x01: eMMC PHY IOPAD Controls#1
Bit Name Access Default Description
0 EXR_NINST
RW 1'b0
External Register Not Inserted
0: External Resist0r inserted
1: External Resistor not Inserted
1
PDB
RW 1'b0
Power Down from SOC
0: Power Down 1: Power Up
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 5
2
DR_TYPE[2:0] RW 3'b000
Drive Type
3’b000: 50 Ohm 3’b001: 33 Ohm
3’b010: 66 Ohm 3’b011: 100 Ohm
3’b100: 40 Ohm 3’b101 – 3’b111: Reserved
3
4
5 RET_EN RW 1'b0
Retention Enable 0: Retention Not enable
1: Retention Enable
This is used only when IO Retention is required. NA for normal SD/eMMC operation.
6 RET_Enb
RW 1'b1
Retention Enable#
1: Retention Not enable 0: Retention Enable
This is used only when IO Retention is required. NA for normal SD/eMMC
operation.
To overcome hardware default value, software will have to write to 1’b1 to this bit. Once written, this is not used until
next power cycle.
7 Reserved RO 1'b0 Reserved for Future Use
Table 2 eMMC PHY IO PAD Controls#1
Offset: 0x02: eMMC PHY IOPAD Controls#2
Bit Name Access Default Description
0 RETRIM RW 1'b0
Retrim
0: No Retrim 1: Retrim
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 6
(For Diagnostic only)
1 EN_RTRIM
RW 1'b0
Enable CALIO PAD
0: Do not Enable CALIO Pad 1: Enable CALIO Pad
2 Reserved RO 1'b0 Reserved for Future Use
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 3 eMMC PHY IO PAD Controls#2
Offset: 0x03: eMMC PHY IOPAD Status
Bit Name Access Default Description
0
RTRIM[3:0] RO 4'b0000 State Machine Calib Result
(For Diagnostic only)
1
2
3
4 CALDONE RO 1'b0
Calibration Done
0: Calibration Not Done. 1: Calibration Done.
(For Diagnostic only)
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 4 eMMC PHY IO PAD status
Offset: 0x04: eMMC PHY IO ODEN Controls#1
Bit Name Access Default Description
0 ODEN_STRB
RW 1'b0
Open Drain Enable on STRB Line
0: Do not Enable Open Drain on STRB Line
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 7
1: Enable Open Drain on STRB Line.
1 ODEN_CMD
RW 1'b0
Open Drain Enable on CMD Line 0: Do not Enable Open Drain on CMD Line
1: Enable Open Drain on CMD Line.
2 Reserved RO 1'b0 Resrved for Future Use
3 Reserved RO 1'b0 Resrved for Future Use
4 Reserved RO 1'b0 Resrved for Future Use
5 Reserved RO 1'b0 Resrved for Future Use
6 Reserved RO 1'b0 Resrved for Future Use
7 Reserved RO 1'b0 Resrved for Future Use
Table 5 eMMC PHY IO ODEN Controls#1
Offset: 0x05: eMMC PHY IO ODEN Controls#2
Bit Name Access Default Description
0
ODEN_DAT0
RW
1'b0
Open Drain Enable on DAT0 Line
0: Do not Enable Open Drain on DAT0 Line
1: Enable Open Drain on DAT0 Line.
1
ODEN_DAT1
RW 1'b0
Open Drain Enable on DAT1 Line
0: Do not Enable Open Drain on DAT0 1ine
1: Enable Open Drain on STRB Line.
2 ODEN_DAT2 RW 1'b0
Open Drain Enable on DAT2 Line
0: Do not Enable Open Drain on STRB
Line 1: Enable Open Drain on STRB Line.
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 8
3 ODEN_DAT3 RW 1'b0
Open Drain Enable on DAT3 Line
0: Do not Enable Open Drain on STRB Line 1: Enable Open Drain on STRB Line.
4 ODEN_DAT4 RW 1'b0
Open Drain Enable on DAT4 Line
0: Do not Enable Open Drain on DAT4
Line 1: Enable Open Drain on STRB Line.
5 ODEN_DAT5 RW 1'b0
Open Drain Enable on DAT5 Line
0: Do not Enable Open Drain on DAT5 Line
1: Enable Open Drain on DAT5 Line.
6 ODEN_DAT6 RW 1'b0
Open Drain Enable on DAT6 Line
0: Do not Enable Open Drain on DAT6
Line 1: Enable Open Drain on DAT6 Line.
7
ODEN_DAT7
RW
1'b0
Open Drain Enable on DAT7 Line
0: Do not Enable Open Drain on DAT7 Line
1: Enable Open Drain on DAT7 Line.
Table 6 eMMC PHY IO ODEN Controls#2
Offset: 0x06: eMMC PHY IO REN Controls#1
Bit Name Access Default Description
0 REN_STRB RW 1'b0
REN Enable on STRB Line
0: Do not Enable REN on STRB LINE 1: Enable REN on STRB LINE
1 REN_CMD RW 1'b0 REN Enable on CMD Line
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 9
0: Do not Enable REN on CMD LINE
1: Enable REN on CMD LINE
2 Reserved RO 1'b0 Reserved for Future Use
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 7 eMMC PHY IO REN Controls#1
Offset: 0x07: eMMC PHY IO REN (Resister Enable) Controls#2
Bit Name Access Default Description
0 REN_DAT0 RW 1’b0
REN Enable on DAT0 Line
0: Do not Enable REN on DAT0 Line 1: Enable REN on Dat0 Line
1 REN_DAT1 RW 1’b0
REN Enable on DAT1 Line 0: Do not Enable REN on DAT1 Line
1: Enable REN on Dat1 Line
2 REN_DAT2 RW 1’b0
REN Enable on DAT2 Line 0: Do not Enable REN on DAT2 Line
1: Enable REN on Dat2 Line
3 REN_DAT3 RW 1’b0
REN Enable on DAT3 Line
0: Do not Enable REN on DAT3 Line
1: Enable REN on Dat3 Line
4 REN_DAT4 RW 1’b0
REN Enable on DAT4 Line
0: Do not Enable REN on DAT4 Line 1: Enable REN on Dat4 Line
5 REN_DAT5 RW 1’b0 REN Enable on DAT5 Line 0: Do not Enable REN on DAT5 Line
1: Enable REN on Dat5 Line
6 REN_DAT6 RW 1’b0 REN Enable on DAT6 Line
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 10
0: Do not Enable REN on DAT6 Line
1: Enable REN on Dat6 Line
7 REN_DAT7 RW 1’b0
REN Enable on DAT7 Line
0: Do not Enable REN on DAT7 Line 1: Enable REN on Dat7 Line
Table 8 eMMC PHY IO REN Controls#2
Offset: 0x08: eMMC PHY IO PU Controls#1
Bit Name Access Default Description
0 PU_STRB RW 1'b0
Pullup Enable on STRB Line
0: Do not Enable Pullup on STRB Line 1: Enable Pullup on STRB Line
1 PU_CMD RW 1'b0
Pullup Enable on CMD Line
0: Do not Enable Pullup on CMD Line 1: Enable Pullup on CMD Line
2 Reserved RO 1'b0 Resrved for Future Use
3 Reserved RO 1'b0 Resrved for Future Use
4 Reserved RO 1'b0 Resrved for Future Use
5 Reserved RO 1'b0 Resrved for Future Use
6 Reserved RO 1'b0 Resrved for Future Use
7 Reserved RO 1'b0 Resrved for Future Use
Table 9 eMMC PHY IO PU Controls#1
Offset: 0x09: eMMC PHY IO PU Controls#2
Bit Name Access Default Description
0 PU_DAT0 RW 1'b0
Pullup Enable on DAT0 Line
0: Do not Enable Pullup on DAT0 Line 1: Enable Pullup on DAT0 Line
1 PU_DAT1 RW 1'b0
Pullup Enable on DAT1 Line 0: Do not Enable Pullup on DAT1 Line
1: Enable Pullup on DAT1 Line
2 PU_DAT2 RW 1'b0
Pullup Enable on DAT2 Line
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 11
0: Do not Enable Pullup on DAT2 Line
1: Enable Pullup on DAT2 Line
3
PU_DAT3 RW 1'b0
Pullup Enable on DAT3 Line
0: Do not Enable Pullup on DAT3 Line 1: Enable Pullup on DAT3 Line
4
PU_DAT4 RW 1'b0
Pullup Enable on DAT4 Line
0: Do not Enable Pullup on DAT4 Line 1: Enable Pullup on DAT4 Line
5
PU_DAT5 RW
1'b0
Pullup Enable on DAT5 Line
0: Do not Enable Pullup on DAT5 Line 1: Enable Pullup on DAT5 Line
6
PU_DAT6 RW
1'b0
Pullup Enable on DAT6 Line
0: Do not Enable Pullup on DAT6 Line
1: Enable Pullup on DAT6 Line
7 PU_DAT7 RW 1'b0
Pullup Enable on DAT7 Line
0: Do not Enable Pullup on DAT7 Line 1: Enable Pullup on DAT7 Line
Table 10 eMMC PHY IO PU Controls#2
Offset: 0x0A: eMMC PHY IO OD_REL Controls#1
Bit Name Access Default Description
0 OD_REL_STRB RW 1'b0
OD Release Enable on STRB Line
0: Do not enable OD Release on STRB Line 1: Enable OD Release on STRB Line
1 OD_REL_CMD RW 1'b0
OD Release Enable on CMD Line 0: Do not enable OD Release on CMD Line
1: Enable OD Release on CMD Line
2 Reserved RO 1'b0 Resrved for Future Use
3 Reserved RO 1'b0 Resrved for Future Use
4 Reserved RO 1'b0 Resrved for Future Use
5 Reserved RO 1'b0 Resrved for Future Use
6 Reserved RO 1'b0 Resrved for Future Use
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 12
7 Reserved RO 1'b0 Resrved for Future Use
Table 11 eMMC PHY IO OD_REL Controls#1
Offset: 0x0B: eMMC PHY IO OD_REL Controls#2
Bit Name Access Default Description
0 OD_REL_DAT0 RW 1'b0
OD Release Enable on DAT0 Line
0: Do not enable OD Release on CMD Line
1: Enable OD Release on CMD Line
1 OD_REL_DAT1 RW 1'b0
OD Release Enable on DAT1 Line
0: Do not enable OD Release on CMD Line 1: Enable OD Release on CMD Line
2 OD_REL_DAT2 RW 1'b0
OD Release Enable on DAT2 Line
0: Do not enable OD Release on CMD Line 1: Enable OD Release on CMD Line
3 OD_REL_DAT3 RW 1'b0
OD Release Enable on DAT3 Line 0: Do not enable OD Release on CMD Line
1: Enable OD Release on CMD Line
4 OD_REL_DAT4 RW 1'b0
OD Release Enable on DAT4 Line
0: Do not enable OD Release on CMD Line
1: Enable OD Release on CMD Line
5 OD_REL_DAT5 RW 1'b0
OD Release Enable on DAT5 Line
0: Do not enable OD Release on CMD Line 1: Enable OD Release on CMD Line
6 OD_REL_DAT6 RW 1'b0
OD Release Enable on DAT6 Line
0: Do not enable OD Release on CMD Line 1: Enable OD Release on CMD Line
7 OD_REL_DAT7 RW 1'b0
OD Release Enable on DAT7 Line
0: Do not enable OD Release on CMD Line 1: Enable OD Release on CMD Line
Table 12 eMMC PHY IO OD_REL Controls#2
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 13
Offset: 0x0C: eMMC PHY ITAPDLY Controls
Bit Name Access Default Description
0 ITAP_DLY_EN RW 1'b0
Input Tap Delay Enable
Overwrite the Host Controllers Tap Delay by setting this bit to 1. Used in
Lower speeds, determined by the Lab results.
1
ITAP_DLY_SEL[4:0] RW 5'b0
Input Tap Delay Select
Overwrite the Host Controllers Tap Delay by setting this bit to 1. Used in
Lower speeds, determined by the Lab results for each mode.
2
3
4
5
6 ITAP_DLY_CHG_WIN RW 1'b0
Input Tap Delay Change Window
Overwrite the Host Controllers Tap Delay by setting this bit to 1. Used only
for Diagnostic purpose.
7 SEL_DLY_RXCLK RW 1'b0
Select DLY Chain based RX_CLK
This should be set to zero. Diagnostic purpose only.
Table 13 eMMC PHY ITAPDLY Controls
Offset: 0x0D: eMMC PHY OTAPDLY Controls
Bit Name Access Default Description
0 OTAP_DLY_EN RW 1'b0
Output Tap Delay Enable
0: Disables the Output Tap Delay 1: Enables the Output Tap Delay.
1
OTAP_DLY_SEL RW 4'b0
Output Tap Delay Select
4’b0000 to 4’b1111 Taps to be selected
for Output Tap Delay. The value is based on Lab Results for each mode.
2
3
4
5 SEL_DLY_TXCLK RW 1'b0 Select DLY Chain based TX_CLK
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 14
This should be set to zero. Diagnostic
purpose only.
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 14 eMMC PHY OTAPDLY Controls
Offset: 0x0E eMMC STRB_SEL Controls
Bit Name Access Default Description
0
STRB_SEL RW 4'b0000
Strobe Select
Selects the phase of STRB_90 and
STRB_180. Should be set to 4’b1111 for ideal STRB_90 and STRB_180 when HS400 is used. All other values are for
diagnostic purpose only.
1
2
3
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 15 eMMC PHY STRB_SEL Controls
Offset: 0x0F eMMC PHY CLK BUF_SEL Controls
Bit Name Access Default Description
0
CLKBUF_SEL RW 3'b000 Clock Buffer Select
Used for Diagnostic Purpose only. 1
2
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 16 eMMC PHY CLKBUF_SEL Controls
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 15
Offset: 0x10 eMMC PHY TEST Controls
Bit Name Access Default Description
0
TEST_CTRL[7:0] RW 8'h00
Test Controls.
Used for Diagnostic purpose only
1
2
3
4
5
6
7
Table 17 eMMC PHY TEST Controls
Offset: 0x11: eMMC PHY MODE Controls
Bit Name Access Default Description
0 ENH_STRB RW 1'b0
Enhanced Strobe Mode. Valid only when HS400 Mode is selected
0: Disabled Enhanced Mode 1: Enables Enhanced Mode.
1 HS400_MODE RW 1'b0
HS400 Mode
0: Disables HS400 mode 1: Enables HS400 Mode.
2 DEFAULT_SPEED RW 1'b1
Default Speed
0: Non-Default Mode 1: Default Mode
3 DDR50_MODE RW 1'b0
DDR50 Mode 0: Disables DDR50 mode
1: Enables DDR50 Mode.
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 16
Table 18 eMMC PHY Controller Controls
Offset: 0x12 eMMC PHY DLL TRIM bits register
Bit Name Access Default Description
0
Phyctrl_dll_trm_icp RW 4'b0000
DLL trim bits
One time programmable for different modes. The value is determined based on lab results and chip configuration.
1
2
3
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 19 eMMC PHY DLL TRIM bits register
Offset: 0x13: eMMC PHY BIST Controls register
Bit Name Access Defaul
t Description
0 phyctrl_bistenable RW 1'b0 BIST Enable bit
For Diagnostic purpose only
1
Phyctrl_bistmode RW 4'b0 select one of the bist modes
For Diagnostic purpose only
2
3
4
5 Phyctrl_biststart RW 1'b0 Start bist operation
For Diagnostic purpose only
6 Phyctrl_bistdone RO 1'b0
status denoting BIST operation
completed
For Diagnostic purpose only
7 Reserved RO 1'b0 Reserved for Future Use
Table 20 eMMC PHY BIST Controls register
Offset: 0x14 eMMC PHY BIST status registers#1
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 17
Bit Name Access Default Description
0
Phyctrl_biststatus [7:0]
RO 8'h00
BIST result for iterations 1-8, with each
corresponding to one iteration
For Diagnostic purpose only
1
2
3
4
5
6
7
Table 21 eMMC PHY BIST status register#1
Offset: 0x15 eMMC PHY BIST status registers#2
Bit Name Access Default Description
0
Phyctrl_biststatus [15:8]
RO 8'h00
BIST result for iterations 9-16, with each
corresponding to one iteration
For Diagnostic purpose only
1
2
3
4
5
6
7
Table 22 eMMC PHY BIST status register#2
Offset: 0x16 eMMC PHY BIST status registers#3
Bit Name Access Default Description
0
Phyctrl_biststatus 16:23]
RO 8'h00
BIST result for iterations 17-24, with each
corresponding to one iteration
For Diagnostic purpose only
1
2
3
4
5
6
7
Table 23 eMMC PHY BIST status registers#3
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 18
Offset: 0x17 eMMC PHY BIST status registers#4
Bit Name Access Default Description
0
Phyctrl_biststatus [24:31]
RO 8'h00
BIST result for iterations 25-32, with each corresponding to one
iteration
For Diagnostic purpose only
1
2
3
4
5
6
7
Table 24 eMMC PHY BIST status registers#3
Offset: 0x18: eMMC PHY IOMUX Control
Bit Name Access Default Description
0 IOMUX_Enable RW 1'b0
Enable IO mux
For Diagnostic purpose only
1 Reserved RO 1'b0 Reserved for Future Use
2 Reserved RO 1'b0 Reserved for Future Use
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 15 eMMC PHY IOMUX Control
Offset: 0x19: eMMC PHY IOMUX CMD Control
Bit Name Access
Defaul
t Description
0 IOMUX_ENA_CMD RW 1'b0
DR_EN CMD
For Diagnostic purpose only
1 IOMUX_DIN_CMD RO 1'b0 DIN CMD
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 19
For Diagnostic purpose only
2 IOMUX_DOUT_CMD RW 1'b0
DOUT CMD For Diagnostic purpose only
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 26 eMMC PHY IOMUX CMD Control
Offset: 0x1A: eMMC PHY IOMUX STRB Control
Bit Name Access Default Description
0 IOMUX_ENA_STRB RW 1'b0
DR_EN STRB For Diagnostic purpose only
1 IOMUX_DIN_STRB RO 1'b0
DIN STRB
For Diagnostic purpose only
2 IOMUX_DOUT_STRB RW 1'b0
DOUT STRB
For Diagnostic purpose only
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 27 eMMC PHY IOMUX STRB Control
Offset: 0x1B: eMMC PHY IOMUX CLK Control
Bit Name Access Defaul
t Description
0 IOMUX_ENA_CLK RW 1'b0
DR_EN CLK
For Diagnostic purpose only
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 20
1 IOMUX_DIN_CLK RO 1'b0
DIN CLK
For Diagnostic purpose only
2 IOMUX_DOUT_CLK RW 1'b0
DOUT CLK For Diagnostic purpose only
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 28 eMMC PHY IOMUX CLK Control
Offset: 0x1C: eMMC PHY IOMUX ENA DAT Control
Bit Name Access Default Description
0 IOMUX_ENA_DAT0 RW 1'b0
DR_EN DAT0 For Diagnostic purpose only
1 IOMUX_ENA_DAT1 RW 1'b0
DR_EN DAT1
For Diagnostic purpose only
2 IOMUX_ENA_DAT2 RW 1'b0
DR_EN DAT2
For Diagnostic purpose only
3
IOMUX_ENA_DAT3 RW 1'b0 DR_EN DAT3
For Diagnostic purpose only
4 IOMUX_ENA_DAT4 RW 1'b0
DR_EN DAT4
For Diagnostic purpose only
5 IOMUX_ENA_DAT5 RW
1'b0
DR_EN DAT5 For Diagnostic purpose only
6
IOMUX_ENA_DAT6 RW
1'b0
DR_EN DAT6
For Diagnostic purpose only
7 IOMUX_ENA_DAT7 RW 1'b0
DR_EN DAT7
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 21
For Diagnostic purpose only
Table 29 eMMC PHY IOMUX ENA DAT Control
Offset: 0x1D: eMMC PHY IOMUX DIN DAT Control
Bit Name Access Default Description
0 IOMUX_DIN_DAT0 RW 1'b0
DIN DAT0
For Diagnostic purpose only
1 IOMUX_DIN_DAT1 RW 1'b0
DIN DAT1 For Diagnostic purpose only
2 IOMUX_DIN_DAT2
RW 1'b0 DIN DAT2
For Diagnostic purpose only
3 IOMUX_DIN_DAT3 RW 1'b0
DIN DAT3
For Diagnostic purpose only
4
IOMUX_DIN_DAT4 RW 1'b0 DIN DAT4
For Diagnostic purpose only
5 IOMUX_DIN_DAT5 RW
1'b0
DIN DAT5
For Diagnostic purpose only
6 IOMUX_DIN_DAT6 RW
1'b0
DIN DAT6 For Diagnostic purpose only
7 IOMUX_DIN_DAT7 RW 1'b0
DIN DAT7
For Diagnostic purpose only
Table 30 eMMC PHY IOMUX DIN DAT Control
Offset: 0x1E: eMMC PHY IOMUX DOUT DAT
Bit Name Access Default Description
0 IOMUX_DOUT_DAT0 RO 1'b0
DOUT DAT0
For Diagnostic purpose only
1 IOMUX_DOUT_DAT1 RO 1'b0
DOUT DAT1
For Diagnostic purpose only
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 22
2 IOMUX_DOUT_DAT2 RO 1'b0
DOUT DAT2
For Diagnostic purpose only
3 IOMUX_DOUT_DAT3 RO 1'b0
DOUT DAT3 For Diagnostic purpose only
4
IOMUX_DOUT_DAT4 RO 1'b0 DOUT DAT4
For Diagnostic purpose only
5 IOMUX_DOUT_DAT5 RO
1'b0
DOUT DAT5
For Diagnostic purpose only
6 IOMUX_DOUT_DAT6 RO
1'b0
DOUT DAT6 For Diagnostic purpose only
7 IOMUX_DOUT_DAT7 RO 1'b0
DOUT DAT7
For Diagnostic purpose only
Table 31 eMMC PHY IOMUX DOUT DAT
Offset: 0x1F: eMMC PHY LDO Control
Bit Name Access Default Description
0 phyLDOrdyb RW 1'b0
Enable phy LDO
Enables PHY’s LDO.
Should be set to 1’b0 for normal operation
1 Reserved RO 1'b0 Reserved for Future Use
2 Reserved RO 1'b0 Reserved for Future Use
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 32 eMMC PHY LDO Control
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 23
Offset: 0x20: eMMC PHY CMD Control
Bit Name Access Default Description
0 phypdbCMD RW 1'b0
Enable CMD Pad power Down
Should be set to 1’b1 for normal operation
For Diagnostic purpose only
1 Reserved RO 1'b0 Reserved for Future Use
2 Reserved RO 1'b0 Reserved for Future Use
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 33 eMMC PHY CMD Control
Offset: 0x21 eMMC PHY DAT Control
Bit Name Access Default Description
0
phypdbdat RO 8'h00
Enable DAT Pads Power Down
Should be set to 1’b1 for normal
operation
For Diagnostic purpose only
1
2
3
4
5
6
7
Table 34 eMMC PHY DAT Control
Offset: 0x22: eMMC PHY STRB Control
Bit Name Access Default Description
0 phypdbstrb RW 1'b0
Enable STRB Pad Power Down.
Should be set to 1’b1 for normal operation
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 24
For Diagnostic purpose only
1 Reserved RO 1'b0 Reserved for Future Use
2 Reserved RO 1'b0 Reserved for Future Use
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 35 eMMC PHY STRB Control
Offset: 0x23: eMMC PHY CLK Control
Bit Name Access Default Description
0 phypdbclk RW 1'b0
Enable CLK Pad Power Down
Should be set to 1’b1 for normal
operation
For Diagnostic purpose only
1 Reserved RO 1'b0 Reserved for Future Use
2 Reserved RO 1'b0
Reserved for Future Use
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 36 eMMC PHY CLK Control
Offset: 0x24: eMMC PHY Control
Bit Name Access Default Description
0 phyCONTROL_sel RW 1'b0 Select phy operation mode 4bit or 8bit For Diagnostic purpose only
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 25
1 Reserved RO 1'b0 Reserved for Future Use
2 Reserved RO 1'b0 Reserved for Future Use
3 Reserved RO 1'b0 Reserved for Future Use
4 Reserved RO 1'b0 Reserved for Future Use
5 Reserved RO 1'b0 Reserved for Future Use
6 Reserved RO 1'b0 Reserved for Future Use
7 Reserved RO 1'b0 Reserved for Future Use
Table 37 eMMC PHY Control
4 eMMC5.1 PHY SDHC Registers
eMMC PHY register access is done by writing to 2 newly added SDHC registers
in the Arasan Host controller as vendor registers. These registers are not part of
standard SDHC register space. These registers are 32bit wide.
reg_phy_register_addr_ctrl – offset 0x300
reg_phy_regsiter_data – offset 0x304
1. reg_phy_register_addr_ctrl[15:0]
• [7:0] – address offset of the phy register to be written/read.
• [8] – R/W, Indicates if the phy register is to be written or read
1 – write; 0 – read.
• [9] – busy, Indicates if phy register operation (read/write) has
finished
• [15:10] – Reserved
2. reg_phy_regsiter_data [15:0]
• [7:0] – 8 bit data to be written or read from phy register
• [15:8] – Reserved
For writing to any PHY register:
1. Write the register value to be programmed to the PHY register to
reg_phy_regsiter_data.
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 26
2. Write the address offset of the phy register to address field of
reg_phy_register_addr_ctrlregister and 1’b1 to R/W bit
ofreg_phy_register_addr_ctrlregister.
3. Poll for the busy bit of reg_phy_register_addr_ctrl register to go low.
4. E.g. to write E8 to phy register offset 0x10, write 16’h00E8 to
reg_phy_regsiter_dataand 16’h0110 to reg_phy_register_addr_ctrland
poll for the busy bit to check if the programming is complete.
For reading from any PHY register:
1. Write the address offset of the phy register to address field of
reg_phy_register_addr_ctrlregister and 1’b0to R/W bit
ofreg_phy_register_addr_ctrlregister
2. Poll for the busy bit of reg_phy_register_addr_ctrlregister to go low
3. Read the data registerreg_phy_regsiter_datato get the value read fromPHY
register
4. E.g. to read from phy register offset 0x20, write 16’h0020 to
reg_phy_register_addr_ctrlregister. After the busy bit goes low, read from
reg_phy_regsiter_datato get the data read from phy register
5 eMMC5.1 PHY Programming Sequence
All the internal PHY registers are accessible through the PHY SDHC registers.
Points to be noted:
Before writing to power control register i.e. enabling bus power following PHY
register programming is required
1. If operating in 4 bit PHY mode, write 1’b1 to phyCONTROL_select (bit 0)
bit of reg_phyCONTROL_ctrl register (offset 0x24).If operating in 8 bit
mode this register write is NOT required.
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 27
2. Enable DLL by writing to 1’b1 to phyDLLctrlsts_dllen(bit 3) of
reg_phyDLL_ctrlsts register (offset 0x00).
3. Enable PDB by writing 1’b1 to phyIOpadsctrl_PDB(bit 1) of
reg_phyIOpads_ctrl_1register(offset 0x01).
4. Enable phypdbcmd by writing 1’b1 to bit 0 of reg_phyCMD_ctrl register
(offset 0x20)
5. Enable phypdbdat by writing 8’b11111111 to reg_phyDAT_ctrl register
(offset 0x21)
6. Enable phypdbstrbby writing 1’b1 to bit 0 of reg_phySTRB_ctrl register
(offset 0x22)
7. Enable phypdbclk by writing to 1’b1 bit 0 of reg_phyCLK_ctrlregister
(offset 0x23)
Write to host power control register to enable bus power and bus voltage.
Before writing to clock control register, following PHY register programming is
required.
8. Make phyLDOrdyb– bit 0 of reg_phyLDO_ctrl register (offset 0x1F) low by
writing 1’b0.
9. Write 8’h04 to reg_phyMODEctrl(offset 0x11) register to enable default
speed mode. phyMODECTRL_DEFAULT_SPEED bit is enabled.
PHY Initialization Sequence:
Register Offset Access Value Comments
IOPAD_CONTROL1 0x01 Rd and Wr BIT(6)
BIT(1)
RETB and PDB_Enable
IOPAD_CONTROL2 0x02 Rd and Wr 0x2 RTRIM Enable
IOPAD_STATUS 0x03 Rd 0x10 Wait till Calibration is done
IO_REN_CONTROL1 0x06 Rd and Wr BIT(0)
BIT(1)
CMD/Strobe IO Retention
IO_PU_CONTROL1 0x08 Rd and Wr BIT(1) CMD Pullup
CMD_CONTROL 0x20 Rd and Wr BIT(0) PDB Cmd
IO_REN_CONTROL2 0x07 Rd and Wr 0xFF Data IO Retention
IO_PU_CONTROL2 0x09 Rd and Wr 0xFF Data Pull up
DATA_CONTROL 0x21 Rd and Wr 0xFF PDB Data
STROBE_CONTROL 0x22 Rd and Wr BIT(0) PDB Strobe
CLK_CONTROL 0x23 Rd and Wr BIT(0) PDB Clk
CLK_BUF_SEL_CTRL 0x0F Rd and Wr 0x7 Max Clk buffer
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 28
MODE_CTRL 0x11 Rd and Wr BIT(2) Set to default legacy mode
PHY Setting sequence for different modes:
Clk bit in DLL_CONTROL_STS has to be chosen w.r.t clock as follows:
200000000 0
100000000 1
50000000 2
Others 0
Register Offset Access Enh Mode Legacy HS
IOPAD_CONTROL1 0x01 Rd&Wr - - -
OTAP_DELAY 0x0D Wr (1 << 1) | 0x1
0 (3 << 1) | 0x1
ITAP_DELAY 0x0C 0 0 (2 << 1) | 0x1
DLL_TRIM 0x12 Wr 0x8 - 0x8
DLL_CONTROL_STS 0x00 WR 0x0 0 0
DLL_CONTROL_STS 0x00 WR (clk << 5) | (1 << 3)
- (clk << 5) | (1 << 3)
DLL_CONTROL_STS 0x00 RD Chk DLL Sts Chk DLL Sts
Chk DLL Sts
MODE_CONTROL 0x11 Wr 0x1 0x4 0x0
Register Offset Access HS200 DDR52 HS400
IOPAD_CONTROL1 0x01 Rd&Wr (drv_type << 2)
- (drv_type << 2)
OTAP_DELAY 0x0D Wr (2 << 1) | 0x1
(3 << 1) | 0x1
(1 << 1) | 0x1
eMMC5.1 PHY in Linux
Copyright © Arasan Chip Systems Inc 29
ITAP_DELAY 0x0C 0 (2 <<
1) | 0x1
(0xa << 1)
| 0x1
DLL_TRIM 0x12 Wr 0x8 0x8 0x8
DLL_CONTROL_STS 0x00 WR 0x0 0 0
DLL_CONTROL_STS 0x00 WR (clk << 5) |
(1 << 3)
(clk <<
5) | (1 << 3)
(clk << 5)
| (1 << 3)
DLL_CONTROL_STS 0x00 RD Chk DLL Sts Chk DLL Sts
Chk DLL Sts
MODE_CONTROL 0x11 Wr 0x0 0x8 0x2