FABRICATION of
MOSFETsCMOS fabrication sequence -p-type silicon substrate wafer-creation of n-well regions for pMOStransistors, -impurity implantation into the substrate. -thick oxide is grown in the regions -surrounding the nMOS and pMOS active regions. -creation of n+ and p+ regions -final metallization & interconnects.
CMOS Process
• PMOS transistors created in an n-well• Typically substrate has lower doping on
the surface
Fabrication –Patterning of
SiO2
• Grow SiO2 on Si by exposing to O2– high temperature accelerates
this process• Cover surface with
photoresist (PR)– Sensitive to UV light
(wavelength determines feature size)
– Positive PR becomes soluble after exposure
– Negative PR becomes insoluble after exposure
Fabrication –Patterning of
SiO2
• PR removed with a solvent
• SiO2 removed by etching (HF)
• Remaining PR removed with another solvent
Summary
• The result of a single lithographic patterning sequence on silicon dioxide, without showing the intermediate steps.
• unpatternedstructure (top)
• patterned structure (bottom)
Fabrication of nMOSTransistor
• Thick field oxide grown
• Field oxide etched to create area for transistor
• Gate oxide (high quality) grown
Fabrication of NMOS Transistor
• Polysilicon deposited (doped to reduce R)• Polysilicon etched to form gate• Gate oxide etched from source and drain
– Self-aligned process because source/drain aligned by gate
• Si doped with donors to create n+ regions
NMOS Transistor Fabrication
• Insulating SiO2 grown to cover surface/gate• Source/Drain regions opened• Aluminum evaporated to cover surface• Aluminum etched to form metal1 interconnects
Metallization
Device Isolation Techniques
• To prevent unwanted conduction• To avoid creation of inversion layers
outside channel regions• To reduce leakage currents
devices are made into Active areas…Surrounded by field oxide (thick oxide barrier)
CMOS n-well process
• P-type substrate• n-well region for PMOS• thin gate oxide is grown on
top of the active regions • thick field oxide is grown in
the areas surrounding the transistor active regions
• gate oxide thickness and quality affect the operational characteristics of the MOS transistor and reliability.
-polysilicon layer -deposited by chemical vapor deposition (CVD) -patterned by etching. -polysilicon lines will function as the gate of MOS - act as self-aligned masks for source and drain
• Masks • n+ and p+
regions implanted in its locations
• ohmiccontacts to substrate and to n-well
Contacts to Silicon needs toBe through heavily doped regionsTo avoid them as junctions
• Metal (aluminum) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability
• Complete
mask sequence applied to create desired structures
Inverter Fabrication
• Inverter– Logic symbol– CMOS inverter circuit– CMOS inverter layout (top view of lithographic masks)
Inverter layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
Inverter Fabrication
• N-wells created• Thick field oxide grown surrounding active
regions• Thin gate oxide grown over active regions
Inverter Fabrication
• Polysilicon deposited– Chemical vapor deposition– Dry plasma etch
Inverter Fabrication
• N+ and P+ regions created using two masks– Source/Drain regions– Substrate contacts
Inverter Fabrication
• Insulating SiO2 deposited using CVD• Source/Drain/Substrate contacts exposed
Inverter Fabrication
• Metal (Al) deposited using evaporation• Metal patterned by etching
Layout Design Rulesspecifyspecify• minimum allowable widths for physical objects
e.g. metal and polysilicon interconnects or diffusion areas. For the line not to break
• minimum feature dimensions. To avoid open circuit
• minimum allowable separations between two such features. To avoid unwanted short circuit
•main objectivemain objective
To increase possibility of successful product
Design rules
• Micron rules– Effitient Layout– Non-Scalable, non-transfareble to other
technology• Lambda (λ) rules
– Scalled to any technology– Ineffetient layout: depends on worst case
can make design bigger than needed
Lambda (Lambda (λλ))• Is the integer fraction half the
minimum fabrication feature size of technology.–1µm technology λ = 0.5 µm
• Assume W=3 λ and L= 2λ– λ = 0.5 µm W=1.5 µm & L =1 µm– λ= 0.3 µm W=.9 µm & L =.6 µm
Even if technology can give 0.5 µm, L = 0.6 µm because of λ rules
Lambda (Lambda (λλ) Rules) Rules• R1 Minimum active area width 3 λλ• R2 Minimum active area spacing 3 λλ
• R3 Minimum poly width 2 λλ• R4 Minimum poly spacing 2 λλ• R5 Minimum gate extension of poly over
active 2 λλ• R6 Minimum poly-active edge spacing 1 λλ
(poly outside active area)• R7 Minimum poly-active edge spacing 3 λλ
(poly inside active area)
• R8 Minimum metal width 3 λλ• R9 Minimum metal spacing 3 λ
• R10 Poly contact size 2 λλ• R11 Minimum poly contact spacing 2 λλ• R12 Minimum poly contact to poly edge
spacing 1 λλ• R13 Minimum poly contact to metal edge
spacing 1 λλ• R14 Minimum poly contact to active
edge spacing 3 λλ• R15 Active contact size 2 λλ• R16 Minimum active contact spacing 2 λλ
(on the same active region) • R17 Minimum active contact to active
edge spacing 1 λλ• R18 Minimum active contact to metal
edge spacing 1 λλ• R19 Minimum active contact to poly
edge spacing 3 λλ• R20 Minimum active contact spacing 6 λλ
(on different active regions)
λ
Stick diagrams showing various CMOS inverter layout options