1
LTC1698
1698f
APPLICATIO SU
DESCRIPTIO
U
FEATURES
TYPICAL APPLICATIO
U
The LTC®1698 is a precision secondary-side forwardconverter controller that synchronously drives externalN-channel MOSFETs. It is designed for use with theLT®3781 primary-side synchronous forward convertercontroller to create a completely isolated power supply.The LT3781 synchronizes the LTC1698 through a smallpulse transformer and the LTC1698 drives a feedbackoptocoupler to close the feedback loop. Output accuracyof ±0.8% and high efficiency over a wide range of loadcurrents are obtained.
The LTC1698 provides accurate secondary-side currentlimit using an external current sense resistor. The inputvoltage at the MARGIN pin provides ±5% output voltageadjustment. A power good flag and overvoltage input areprovided to ensure proper power supply conditions. Anauxiliary 3.3V logic supply is included that supplies up to10mA of output current.
Isolated SecondarySynchronous Rectifier Controller
High Efficiency Over Wide Load Current Range ±0.8% Output Voltage Accuracy Dual N-Channel MOSFET Synchronous Drivers Pulse Transformer Synchronization Optocoupler Feedback Driver Programmable Current Limit Protection ±5% Margin Output Voltage Adjustment Adjustable Overvoltage Fault Protection Power Good Flag Auxiliary 3.3V Logic Supply Available in 16-Lead SSOP and SO Packages
48V Input Isolated DC/DC Converters Isolated Telecommunication Power Systems Distributed Power Step-Down Converters Industrial Control Systems Automotive and Heavy Equipment
Figure 1. Simplified 2-Transistor Isolated Forward Converter
, LTC and LT are registered trademarks of Linear Technology Corporation.
+
+
CGVDD PWRGD
LTC1698
PGND GND
2 8
CFB
CC
CCILM
RC
VOUT
RCILM
R2
R5
R4
R1
L1
6
13
9
7
14
COUT
1 10
Q4
VIN36V to 72V
Q3
T1
••
Q1
D1
Q2
RPRISEN
T2
FG16
ISNS
RSECSEN
12
ISNSGND11
SYNC
VFB
VCOMP
VAUX
ICOMP
OVPIN
MARGIN VMARGIN
O.1µF
1681 F01
VAUX3.3V10mA
15
OPTODRV
PLEASE REFER TO FIGURE 12 IN THE TYPICAL APPLICATIONSSECTION FOR THE COMPLETE 3.3V/15A APPLICATION SCHEMATIC
5
3 4
RSYNC
RK
RE
ISOLATIONBOUNDARY
RF
REFVFB
SGTG BG
LT3781
VC
CSYNC
CK
CF
VDD BIAS
CSG
+–
D2
••
2
LTC1698
1698f
(Note 1)VDD, PWRGD ....................................................... 13.2VInput Voltage
MARGIN, VFB, OVPIN, ISNSGND, ISNS ... –0.3V to 5.3VSYNC ..................................................... –14V to 14V
Output VoltageVCOMP, ICOMP (Note 2) ......................... –0.3V to 5.3V
Power Dissipation .............................................. 500mWOperating Temperature Range
LTC1698E (Note 3) ............................ – 40°C to 85°CLTC1698I ........................................... – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°CLead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE MAXIMUM RATINGS
W WW U
PACKAGE/ORDER INFORMATION
W UU
ORDER PARTNUMBER
LTC1698EGNLTC1698ESLTC1698IGNLTC1698IS
TJMAX = 125°C, θJA = 130°C/W (GN)TJMAX = 125°C, θJA = 110°C/W (SO)
GN PACKAGE16-LEAD PLASTIC SSOP
S PACKAGE16-LEAD PLASTIC SO
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
VDD
CG
PGND
GND
OPTODRV
VCOMP
MARGIN
VFB
FG
SYNC
VAUX
ICOMP
ISNS
ISNSGND
PWRGD
OVPIN
The indicates specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VDD = 8V, unless otherwise noted. (Note 4)ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 6 8 12.6 VVUVLO Undervoltage Lockout 4 V
IVDD VDD Supply Current VFB, OVPIN, VISNS, VISNSGND = 0V,CFG = CCG = 1000pF, CVAUX = 0.1µF,VSYNC = 0V 1.8 4 mA
fSYNC = 100kHz (Note 5) 5.0 mAMARGIN and Error Amplifier
VFB Feedback Voltage MARGIN = Open, VCOMP = 1V (Note 7) 1.223 1.233 1.243 V 1.215 1.233 1.251 V
IVFB Feedback Input Current VFB = 1.233V 0.05 1 µA
VMARGIN MARGIN Voltage MARGIN = Open 1.65 V
RMARGIN MARGIN Input Resistance 16.5 kΩ∆VFB Feedback Voltage Adjustment VMARGIN = 3.3V 4 5 6 %
VMARGIN = 0V –6 –5 –4 %GERR Error Amplifier Open-Loop DC Gain VCOMP = 0.8V to 1.2V, Load = 2kΩ, 100pF 65 90 dB
BWERR Error Amplifier Unity-Gain Bandwidth No Load (Note 6) 2 MHz
VCLAMP Error Amplifier Output Clamp Voltage VFB = 0V 2 VIVCOMP Error Amplifier Source Current VFB = 0V – 25 – 10 mA
Error Amplifier Sink Current VFB = 5V, VCOMP = 1.233V 3 7 mA
OPTODRVGOPTO Opto Driver DC Gain OVPIN, VISNS, VISNSGND = 0V 4.75 5 5.25 V/V
BWOPTO Opto Driver Unity-Gain Bandwidth No Load (Note 6) 1 MHz
VOPTOHIGH Opto Driver Output High Voltage VFB, OVPIN, VISNSGND = 0V, VISNS = –50mV,IOPTODRV = –10mA 4 5 V
IOPTOSC Opto Driver Output Short-Circuit Current OVPIN, VISNSGND, VISNS = 0V, VFB = 1.233V – 50 – 25 – 10 mA
GN PART MARKING
16981698I
3
LTC1698
1698f
The indicates specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VDD = 8V, unless otherwise noted. (Note 4)ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the lifeof a device may be impaired. All voltages refer to GND.Note 2: The LTC1698 incorporates a 5V linear regulator to power internalcircuitry. Driving these pins above 5.3V may cause excessive current flow.Guaranteed by design and not subject to test.Note 3: The LTC1698E is guaranteed to meet performance specificationsfrom 0°C to 70°C. Specifications over the –40°C to 85°C operatingtemperature range are assured by design, characterization and correlationwith statistical process controls. For guaranteed performance tospecifications over the –40°C to 85°C range, the LTC1698I is available.Note 4: All currents into device pins are positive; all currents out of thedevice pins are negative. All voltages are referenced to ground unlessotherwise specified. For applications with VDD < 7V, refer to the TypicalPerformance Characteristics.
Note 5: Supply current in active operation is dominated by the currentneeded to charge and discharge the external FET gates. This will vary withthe LTC1698 operating frequency, supply voltage and the external FETsused.Note 6: This parameter is guaranteed by correlation and is not tested.Note 7: VFB is tested in an op amp feedback loop which servos VFB to theinternal bandgap voltage.Note 8: The current comparator output current varies linearly withtemperature.Note 9: The PWRGD and OVP comparators incorporate 10mV ofhysteresis.Note 10: The driver disable time-out is proportional to the SYNC periodwithin the frequency synchronization range.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSVAUX
VAUX Auxiliary Supply Voltage CVAUX = 0.1µF, ILOAD = 0mA to 10mA, VDD = 7V to 12.6V 3.135 3.320 3.465 VCurrent Limit AmplifierIISNSGND ISNSGND Input Current VISNSGND = 0V 0.05 1 µAIISNS ISNS Input Current VISNS = 0V 0.05 1 µAVILIMTH Current Limit Threshold VICOMP = 2.5V, VISNSGND = 0V – 27.0 – 25 – 23.0 mV
(VISNS – VISNSGND) – 27.5 – 25 – 22.5 mVIICOMP ICOMP Source Current VISNSGND = 0V, VISNS = – 0.3V, VICOMP = 2.5V (Note 8) –280 –200 –120 µA
–370 –200 – 80 µAICOMP Sink Current VISNSGND = 0V, VISNS = 0.3V, VICOMP = 2.5V (Note 8) 120 200 280 µA
80 200 370 µAgmILIM Current Limit Amplifier VISNSGND = 0V, VICOMP = 2.5V, IICOMP = ±10µA 2.2 3.5 5 millimho
TransconductanceGICOMP Current Limit Amplifier VICOMP = 2.5V, No Load 48 60 dB
Open-Loop DC GainPWRGD and OVP ComparatorsVPWRGD Percent Below VFB VFB ↓, MARGIN = Open (Note 9) –9 –6 –3 %IPWRGD Power Good Sink Current VFB = 2V 10 µA
VFB = 0V 10 mAVOL Power Good Output Low Voltage IPWRGD = 3mA, VFB = 0V 0.4 VVOVPREF OVPIN Threshold VFB = VISNS = VISNSGND = 0V, OVPIN ↑ (Note 9) 1.18 1.233 1.28 VIOVPIN OVPIN Input Bias Current VOVPIN = 1.233V 0.1 1 µAtPWRGD Power Good Response Time VFB ↑ 1 2 5 ms
Power Bad Response Time VFB ↓ 0.5 1 2.5 mstOVP Overvoltage Response Time VOVPIN ↑, COPTODRV = 0.1µF 5 20 µsSYNC and DriversVPT SYNC Input Positive Threshold 1 1.6 2.2 VVNT SYNC Input Negative Threshold –2.2 –1.6 –1 VISYNC SYNC Input Current VSYNC = ±10V 1 50 µAfSYNC SYNC Frequency Range CFG = CCG = 1000pF, VSYNC = ±5V 50 400 kHztd SYNC Input to Driver Output Delay CFG = CCG = 1000pF, fSYNC = 100kHz, VSYNC = ±5V 40 90 nstSYNC Minimum SYNC Pulse Width fSYNC = 100kHz, VSYNC = ±10V (Note 6) 75 nstr, tf Driver Rise and Fall Time CFG = CCG = 1000pF, fSYNC = 100kHz, VSYNC = ±5V, 10 40 ns
10% to 90%tDDIS Driver Disable Time-Out CFG = CCG = 1000pF, fSYNC = 100kHz, VSYNC = ±5V
Measured from CG ↑ (Note 10) 10 15 20 µs
4
LTC1698
1698f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VFB vs Temperature
TEMPERATURE (°C)–50
V FB
(V)
1.236
1.242
1.248
25 75 150
1698 G01
1.230
1.224
1.218–25 0 50 100 125
VDD = 8V
VDD (V)5
1.218
V FB
(V)
1.224
1.236
1.242
1.248
7 9 10 14
1698 G02
1.230
6 8 11 12 13
TA = 25°C
VMARGIN (V)0
V FB
(V)
∆VFB (%
)
1.245
1.270
1.295
2.64
1698 G03
1.221
1.196
1.233
1.258
1.282
1.208
1.184
1.171
1
3
5
–1
–3
0
2
4
–2
–4
–50.660.33 1.320.99 1.98 2.31 2.971.65 3.3
VDD = 8VTA = 25°C
VFB vs VDD VFB vs VMARGIN
ISNS Threshold vs Temperature ISNS Threshold vs VDD
Current Limit Amplifier gmvs Temperature
TEMPERATURE (°C)–50
–27.5
I SNS
THR
ESHO
LD (m
V)
–27.0
–26.0
–25.5
–25.0
–22.5
–24.0
0 50 75
1698 G04
–26.5
–23.5
–23.0
–24.5
–25 25 100 125 150
VDD = 8V
VDD (V)5
–27.5
I SNS
THR
ESHO
LD (m
V)
–27.0
–26.0
–25.5
–25.0
–22.5
–24.0
87 10 11
1698 G05
–26.5
–23.5
–23.0
–24.5
6 9 12 13 14
TA = 25°C
TEMPERATURE (°C)–50
g mIL
IM (m
illim
ho)
3.8
4.2
4.6
100 125
1698 G06
3.4
3.0
–25 250 50 75 150
2.6
2.2
5.0VDD = 8V
OVPIN Threshold vs Temperature OVPIN Threshold vs VDDPower Good Thresholdvs Temperature
TEMPERATURE (°C)–50
OVPI
N TH
RESH
OLD
(V)
1.24
1.26
1.28
25 75 150
1698 G07
1.22
1.20
1.18–25 0 50 100 125
VDD = 8V
VDD (V)5
1.18
OVPI
N TH
RESH
OLD
(V)
1.20
1.24
1.26
1.28
7 9 10 14
1698 G08
1.22
6 8 11 12 13
TA = 25°C
TEMPERATURE (°C)–50
POW
ER G
OOD
THRE
SHOL
D (V
)
∆VFB (%
)
1.166
1.181
1.196
25 75 150
1698 G09
1.152
1.137
1.122
–5.4
–4.2
–3.0
–6.6
–7.8
–9.0–25 0 50 100 125
VDD = 8V
5
LTC1698
1698f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VAUX vs Temperature VAUX vs Line Voltage VAUX vs Load Current
VAUX Short-Circuit Currentvs Temperature
VAUX Short-Circuit Currentvs VDD Opto Driver Load Regulation
Opto Driver Short-Circuit Currentvs Temperature
TEMPERATURE (°C)–50
V AUX
(V)
3.300
3.383
150
1698 G10
3.218
3.1350 50 100–25 25 75 125
3.465
3.259
3.341
3.176
3.424
VDD = 8VILOAD = 0mA
VDD (V)5
V AUX
(V)
3.300
3.383
14
1698 G11
3.218
3.1357 8 10 126 9 11 13
3.465
3.259
3.341
3.176
3.424
VDD = 8VILOAD = 0mA
LOAD CURRENT (mA)0
V AUX
(V)
3.300
3.383
109
1698 G12
3.218
3.1352 3 5 71 4 6 8
3.465
3.259
3.341
3.176
3.424
VDD = 8VTA = 25°C
TEMPERATURE (°C)–50
V AUX
SHO
RT-C
IRCU
IT C
URRE
NT (m
A)
–20
–10
0
25 75 150
1698 G13
–30
–40
–50–25 0 50 100 125
VDD = 8V
VDD (V)5
V AUX
SHO
RT-C
IRCU
IT C
URRE
NT (m
A)
–20
–10
0
8 10 14
1698 G14
–30
–40
–506 7 9 11 12 13
TA = 25°C
LOAD CURRENT (mA)0
OPTO
DRI
VER
OUTP
UT V
OLTA
GE (V
)
PERCENT (%)
3.006
3.018
3.030
8
1698 G15
2.994
2.982
3.000
3.012
3.024
2.988
2.976
2.970
0.2
0.6
1.0
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.021 43 6 7 95 10
VDD = 8VTA = 25°C
TEMPERATURE (°C)–50
OPTO
DRI
VER
SHOR
T-CI
RCUI
T CU
RREN
T (m
A)
–30
–20
150
1698 G16
–40
–500 50 100–25 25 75 125
–10
–35
–25
–45
–15
VDD = 8VVOPTODRV = 1.233V
Maximum OPTO Driver OutputVoltage vs Load Current
Maximum OPTO Driver OutputVoltage vs Temperature
LOAD CURRENT (mA)0
MAX
IMUM
OPT
O DR
IVER
OUT
PUT
VOLT
AGE
(V)
4
6
8
1698 G22
2
02 4 5 10
8
61 3 97
VDD = 10V
VDD = 8V
VDD = 7V
VDD = 6V
VDD = 5V
TA = 25°CVCOMP = 0V
TEMPERATURE (°C)–50
0MAX
IMUM
OPT
O DR
IVER
OUT
PUT
VOLT
AGE
(V)
2
4
6
8
–25 0 25 50
1698 G23
75 100 125 150
VDD = 10V
VDD = 8V
VDD = 6V
VDD = 5V
VCOMP = 0VIOPTODRV = –10mA
VDD = 7V
6
LTC1698
1698f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
IVDD vs SYNC Frequency
fSYNC (kHz)50
I VDD
(mA) 30
40
50
450
1698 G19
20
10
25
35
45
15
5
0150100 250200 350 400300 500
VDD = 8VTA = 25°C
CFG = CCG = 4700pF
CFG = CCG = 3300pF
CFG = CCG = 2200pF
CFG = CCG = 1000pF
TEMPERATURE (°C)–50
SYNC
POS
ITIV
E TH
RESH
OLD
(V)
2.00
2.25
25 75 150
1698 G20
1.75
1.50
1.25
1.00–25 0 50 100 125
VDD = 8V
VDD (V)5
1.00
SYNC
POS
ITIV
E TH
RESH
OLD
(V)
1.24
1.72
1.96
2.20
7 9 10 14
1698 G21
1.48
6 8 11 12 13
TA = 25°C
SYNC Positive Thresholdvs Temperature
SYNC Positive Thresholdvs VDD
Undervoltage Lockout Thresholdvs Temperature
TEMPERATURE (°C)–50
V UVL
O (V
) 3
4
5
25 75 150
1698 G24
2
1
0–25 0 50 100 125
IVDD vs VDD
Opto Driver Short-Circuit Currentvs VDD
VDD (V)5
OPTO
DRI
VER
SHOR
T-CI
RCUI
T CU
RREN
T (m
A)
–20
–10
0
8 10 14
1698 G17
–30
–40
–506 7 9 11 12 13
TA = 25°CVOPTODRV = 1.233V
VDD (V)5
I VDD
(mA) 12
16
20
13
1698 G18
8
4
10
14
18
6
2
076 98 11 1210 14
TA = 25°CfSYNC = 100kHz CFG = CCG = 4700pF
CFG = CCG = 3300pF
CFG = CCG = 2200pF
CFG = CCG = 1000pF
DRIVER LOAD (pF)0
TIM
E (n
s)
4000 8000 10000
90
80
70
60
50
40
30
20
10
0
1698 G25
2000 6000
VDD = 8VTA = 25°C
CG, FG tPHL
tf tr
CG, FG tPLH
TEMPERATURE (°C)–50 –25 0 25 50 75 100 125 150
t d (n
s)
90
80
70
60
50
40
30
20
10
0
1698 G26
VDD = 8VCCG = CFG = 1000pFfSYNC = 100kHz
CG, FG tPLH
CG, FG tPHL
fSYNC (kHz)50
DRIV
ER D
ISAB
LE T
IME-
OUT
t DIS
S (µ
s)
150 250 300 500
1698 G27
100 200 350 400 450
30
25
20
15
10
5
0
NORMALIZED DRIVER DISABLE TIM
E-OUTtDISS × fSYNC
2.2
2.0
1.8
1.6
1.4
1.2
1.0
VDD = 8VTA = 25°C
tDISS × fSYNC
tDISS
Driver Rise, Fall and PropagationDelay vs Driver Load
SYNC Input to Driver Output Delayvs Temperature
Driver Disable Time-Out vs SYNCFrequency
7
LTC1698
1698f
UUU
PI FU CTIO SVDD (Pin 1): Power Supply Input. For isolated applica-tions, a simple rectifier from the power transformer isused to power the chip. This pin powers the opto driver,the VAUX supply and the FG and CG drivers. An internal 5Vregulator powers the remaining circuitry. VDD requires anexternal 4.7µF bypass capacitor.
CG (Pin 2): Catch Gate Driver. If SYNC slews positive, CGpulls high to drive an external N-channel MOSFET. CGdraws power from the VDD pin and swings between VDDand PGND.
PGND (Pin 3): Power Ground. Connect PGND to a lowimpedance ground plane in close proximity to the groundterminal of the external current sensing resistor.
GND (Pin 4): Logic and Signal Ground. GND is referencedto the internal low power circuitry. Careful board layouttechniques must be used to prevent corruption of signalground reference. Connect GND and PGND together di-rectly at the LTC1698.
OPTODRV (Pin 5): Optocoupler Driver Output. This pindrives a ground referenced optocoupler through an exter-nal resistor. If VFB is low, OPTODRV pulls low. If VFB ishigh, OPTODRV pulls high. This optocoupler driver has aDC gain of 5. During overvoltage or overcurrent condi-tions, OPTODRV pulls high. The output is capable ofsourcing 10mA of current and will drive an external 0.1µFcapacitive load and is short-circuit protected.
VCOMP (Pin 6): Error Amplifier Output. This error amplifieris able to drive more than 2kΩ and 100pF of load. Theinternal diode connected from VFB to VCOMP reducesOPTODRV recovery time under start-up conditions.
MARGIN (Pin 7): Current Input to Adjust the OutputVoltage Linearly. The MARGIN pin connects to an internal16.5k resistor. The other end of this resistor is regulatedto 1.65V. Connecting MARGIN to a 3.3V logic supplysources 100µA of current into the chip and moves theoutput voltage 5% higher. Connecting MARGIN to 0Vsinks 100µA out of the pin and moves the regulated outputvoltage 5% lower. The MARGIN pin voltage does not affectthe PWRGD and OVPIN trip points.
VFB (Pin 8): Feedback Voltage. VFB senses the regulatedoutput voltage through an external resistor divider. TheVFB pin is servoed to the reference voltage of 1.233V underclosed-loop conditions. An RC network from VFB to VCOMP
compensates the feedback loop. If VFB goes low, VCOMPpulls high and OPTODRV goes low.
OVPIN (Pin 9): Overvoltage Input. OVPIN is a high imped-ance input to an internal comparator. The threshold of thiscomparator is set to 1.233V. If the OVPIN potential ishigher than the threshold voltage, OPTODRV pulls highimmediately. Use an external RC lowpass filter to preventnoisy signals from triggering this comparator.
PWRGD (Pin 10): Power Good Output. This is an open-drain output. PWRGD floats if VFB is above 94% of thenominal value for more than 2ms. PWRGD pulls low if VFBis below 94% of the nominal value for more than 1ms. ThePWRGD threshold is independent of the MARGIN pinpotential.
ISNSGND (Pin 11): Current Sense Ground. Connect to thepositive side of the sense resistor, normally grounded.
ISNS (Pin 12): Current Sense Input. Connect to the nega-tive side of the sense resistor through an external RClowpass filter. This pin normally sees a negative voltage,which is proportional to the average load current. Ifcurrent limit is exceeded, OPTODRV pulls high.
ICOMP (Pin 13): Current Amplifier Output. An RC networkat this pin compensates the current limit feedback loop.Referencing the RC to VOUT controls output voltage over-shoot on start-up. This pin can float if current limit loopcompensation is not required.
VAUX (Pin 14): Auxiliary 3.3V Logic Supply. This pinrequires a 0.1µF or greater bypass capacitor. This auxiliarypower supply can power external devices and sources10mA of current. Internal current limiting is provided.
SYNC (Pin 15): Drivers Synchronization Input. A negativevoltage slew at SYNC forces FG to pull high and CG to pulllow. A positive voltage slew at SYNC resets the FG pin andCG pulls high. If SYNC loses its synchronization signal formore than the driver disable time-out interval, both theforward and catch drivers output are forced low. The SYNCcircuit accepts pulse and square wave signals. The mini-mum pulse width is 75ns. The synchronization frequencyrange is between 50kHz to 400kHz.
FG (Pin 16): Forward Gate Driver. If SYNC slews negative,FG goes high. FG draws power from VDD and swingsbetween VDD and PGND.
8
LTC1698
1698f
BLOCK DIAGRA
W
I-TO-V CONVERTERRMARGIN
20k
ROVP3k
100k
VFB 0.94VREF
MPWRGD
RILIM3k
MILIM
MARGIN7
SYNC15
OPTODRV5
±5% VREFVREFBANDGAP
SYNC INVCC
VDD
VAUX14
–
+–
+
– +
ERR
–
+ILIM 25mV
–
+OVP
VREF
1698 BD
+
OPTO
PWRGD10
OVPIN9
ICOMP13
ISNS12
ISNSGND11
VCOMP6
VFB8
CG2
FG16
PWRGD
AUX GEN VCC GEN
1
OPERATIOU
The LTC1698 is a secondary-side synchronous rectifiercontroller designed to work with the LT3781 primary-sidesynchronous controller chip to form an isolated synchro-nous forward converter. This chip set uses a dual transis-tor forward topology that is predominantly used in distrib-uted power supply systems where isolated low voltagesare needed to power complex electronic equipment. Theprimary stage is a current mode, fixed frequency forwardconverter and provides the typical PWM operation. Apower transformer is used to provide the functions ofinput/output isolation and voltage step-down to achievethe required low output voltage. Instead of using typical
Schottky diodes, synchronous rectification on the sec-ondary offers isolation with high efficiency. It supplieshigh power without the need of bulky heat sinks, which isoften a problem in any space constrained application.
The LTC1698 not only provides synchronous drivers forthe external MOSFETs, it comes with other housekeepingfunctions performed on the secondary side of the powersupply, all within a single integrated controller. Figure 1shows the typical chip-set application. Upon power up, theLTC1698’s VDD input is low, the gate drivers TG and BG areboth at the ground potential. The secondary forward and
(Refer to Block Diagram)
9
LTC1698
1698f
catch MOSFETs Q3 and Q4 are off. As soon as transistorsQ1 and Q2 turn on, the flux in the power transformer T1forces the body diodes of Q3 and Q4 to conduct, and thewhole circuit starts like a conventional forward converter.At the same time, the LTC1698 VDD potential ramps upquickly through the VDD bias circuitry. Once the VDDvoltage exceeds 4.0V, the LTC1698 enables its drivers andenters synchronous operation.
The pulse transformer T2 synchronizes the primary andsecondary MOSFET drivers. In a typical conversion cycle,the primary MOSFETs Q1 and Q2 turn on simultaneously.SG goes low and generates a negative spike at the LTC1698SYNC input through the pulse transformer. The LTC1698forces FG to turn on and CG to turn off. Power is deliveredto the load through the transformer T1 and the inductor L1.At the beginning of the next phase in which Q1 and Q2 turnoff, SG goes high, SYNC sees a positive spike, the MOSFETQ3 shuts off, Q4 conducts and allows continuous currentto flow through the inductor L1. The capacitor COUT filtersthe switching waveform to provide a steady DC outputvoltage for the load.
The LTC1698 error amplifier ERR senses the output volt-age through an external resistor divider and regulates theVFB pin potential to the 1.233V internal bandgap voltage.An external RC network across the VFB and VCOMP pinsfrequency compensates the error amplifier feedback. Theopto driver amplifies the voltage difference between theVCOMP pin and the bandgap potential, driving the externaloptocoupler diode with an inverting gain of 5. Theoptocoupler feeds the amplified output error signal to theprimary controller and closes the forward converter volt-age feedback loop. Under start-up conditions, the internaldiode across the LTC1698 error amplifier clamps theVCOMP pin. This speeds up the opto driver recovery time byreducing the negative slew rate excursion at the COMP pin.
The forward converter output voltage can be easily ad-justed. The potential at the MARGIN pin is capable of
forcing the error amplifier reference voltage to movelinearly by ±5%. The internal RMARGIN resistor convertsthe MARGIN voltage to a current and linearly controls theoffset of the error amplifier. Connecting the MARGIN pinto 3.3V increases the VFB voltage by 5%, and connectingthe MARGIN pin to 0V reduces VFB by 5%. With theMARGIN pin floating, the VFB voltage is regulated to theinternal bandgap voltage.
The current limit transconductance amplifier ILIM providesthe secondary side average current limit function. Theaverage voltage drops across the RSECSEN resistor issensed and compared to the – 25mV threshold set by theinternal ILIM amplifier. Once ILIM detects high outputcurrent, the current amplifier output pulls high, overridesthe error amplifier, injects more current into the photodiode and forces a lower duty cycle. An RC networkconnected to the ICOMP pin is used to stabilize the second-ary current limit loop. Alternatively, if only overcurrentfault protection is required, ICOMP can float.
If under abnormal conditions the feedback path is broken,OVPIN provides another route for overvoltage fault pro-tection. If the voltage at OVPIN is higher than the bandgapvoltage, the OVP comparator forces OPTODRV high im-mediately. A simple external RC filter prevents a momen-tary overshoot at OVPIN from triggering the OVPcomparator. Short OVPIN to ground if this pin is not used.
The LTC1698 provides an open-drain PWRGD output. IfVFB is less than 94% of its nominal value for more than1ms, the PWRGD comparator pulls the PWRGD pin low.If VFB is higher than 94% of its nominal value for more than2ms, the transistor MPWRGD shuts off, and an externalresistor pulls the PWRGD pin high.
The LTC1698 provides an auxiliary 3.3V logic powersupply. This auxiliary power supply is externally compen-sated with a minimum 0.1µF bypass capacitor. It suppliesup to 10mA of current to any external devices.
OPERATIOU
(Refer to Block Diagram)
10
LTC1698
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APPLICATIO S I FOR ATIO
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Undervoltage Lockout
In UVLO (low VDD voltage) the drivers FG and CG are shutoff and the pins OPTODRV, VAUX, PWRGD and ICOMP areforced low. The LTC1698 allows the bandgap and theinternal bias currents to reach their steady-state valuesbefore releasing UVLO. Typically, this happens when VDDreaches approximately 4.0V. Beyond this threshold, thedrivers start switching. The OPTODRV, VAUX, PWRGD andICOMP pins return to their normal values and the chip isfully functional. However, if the VDD voltage is less than 7V,the OPTODRV and VAUX current sourcing capabilities arelimited. See the OPTO driver graphs in the Typical Perfor-mance Characteristics section.
VDD Regulator
The bias supply for the LTC1698 is generated by peakrectifying the isolated transformer secondary winding. Asshown in Figure 2, the zener diode Z1 is connected frombase of Q5 to ground such that the emitter of Q5 isregulated to one diode drop below the zener voltage. RZ isselected to bring Z1 into conduction and also provide basecurrent to Q5. A resistor (on the order of a few hundredohms), in series with the base of Q5, may be required tosurpress high frequency oscillations depending on Q5’sselection. A power MOSFET can also be used by increasingthe zener diode value to offset the drop of the gate-to-source voltage. VDD supply current varies linearly with thesupply voltage, driver load and clock frequency. A 4.7µFbypass capacitor for the VDD supply is sufficient for mostapplications. This capacitor must be large enough toprovide a stable DC voltage to meet the LTC1698 VDD
supply requirement. Under start-up conditions, it must besmall enough to power up instantaneously, enabling theLTC1698 to regulate the feedback loop. Using a largercapacitor requires evaluation of the start-up performance.
SYNC Input
Figure 3 shows the synchronous forward converter appli-cation. The primary controller LT3781 runs at a fixedfrequency and controls MOSFETs Q1 and Q2. The second-ary controller LTC1698 controls MOSFETs Q3 and Q4. Aninexpensive, small-size pulse transformer T2 synchro-nizes the primary and the secondary controllers. Figure 4shows the pulse transformer timing waveforms. When theLT3781 synchronization output SG goes low, MOSFET
VSECONDARY
1Ω
D3
RZ2k RB*
*RB IS OPTIONAL, SEE TEXT
Z110V
Q5FZT6900.47µF
4.7µF
1698 F02
VDD
Figure 2. VDD Regulator
• •
• •
D2T1
T2
VIN
D1
Q1
Q2 Q3
Q4
PRIMARYCONTROLLER
LT3781
TG
BGSG
SECONDARYCONTROLLER
LTC1698
CG
L1
COUT
VOUT
FG SYNC
CSG
ISOLATION BARRIER
SECONDARYPRIMARY
CSYNC
RSYNC
1698 F03
Figure 3. Synchronization Using Pulse Transformer
TG
BG
SG
SYNC
FG
CG
1698 F04
Figure 4. Primary Side and Secondary SideSynchronization Waveforms
11
LTC1698
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drivers TG and BG go high. The pulse transformer T2generates a negative slew at the SYNC pin and forces thesecondary MOSFET driver FG to go high and CG to go low.When TG and BG go low, SG goes high and the secondarycontroller forces CG high and FG low.
For a given pulse transformer, a bigger capacitor CSGgenerates a higher and wider SYNC pulse. The peak of thispulse should be much higher than the SYNC threshold.Amplitudes greater than ±5V help to speed up the SYNCcomparator and reduce the SYNC to FG and CG driverspropagation delay. The minimum pulse width is 75ns.Overshoot during the pulse transformer reset intervalmust be minimized and kept below the minimum com-parator thresholds of ±1V. The amount of overshoot canbe reduced by having a smaller reset resistor RSYNC. Fornonisolated applications, the SYNC input can be drivendirectly by a square pulse. To reduce the propagationdelay, make the positive and negative magnitude of thesquare wave much greater than the ±2.2V maximumthreshold.
In addition to the simple driver synchronization, the sec-ondary controller requires a driver disable signal. Loss ofsynchronization while CG is high will cause Q4 to dis-charge the output capacitor. This produces a negativeoutput voltage transient and possible damage to the loadcircuitry connected to VOUT. To overcome this problem,the LTC1698 comes with a unique adaptive time-outcircuit. It works well within the 50kHz to 400kHz frequencyrange. At every positive SYNC pulse, the internal timerresets. If the SYNC signal is missing, the internal timerloses its reset command, and eventually exceeds theinternal time-out limit. This forces both the FG and CGdrivers to go low immediately.
The time-out duration varies linearly with the LT3781primary controller clocking frequency. Upon power up,the time-out circuitry takes a few clock cycles to adapt tothe input clock frequency. During this time interval, thedrivers pulse width might be prematurely terminated, andthe inductor current flows through the MOSFETs bodydiode. Once the LTC1698 timer locks to the clockingfrequency, the LTC1698 drivers follow the SYNC signalwithout fail. Figure 5 shows the SYNC time-out wave-
forms. The time-out circuit guarantees that if the SYNCpulse is missing for more than one period, both thedrivers will be shut down preventing the output voltagefrom going below ground. The wide synchronizationfrequency range adds flexibility to the forward converterand allows this converter chip set to meet differentapplication requirements.
Under normal operating conditions, the time-out circuitryadapts to the switching frequency within a few cycles.Once synchronized, internal circuitry ensures the maxi-mum time that the Catch FET (Q4) could be left turned onis typically just over one switching period. This is particu-larly important with high output voltages that can generatesignificant negative output inductor currents if the CatchFET Q4 is left on. Poor feedback loop performance includ-ing output voltage overshoot can cause the primary con-troller to interrupt the synchronization pulse train. Whilethis generally is not a problem, it is possible that lowfrequency interruptions could lead to a time-out periodlonger than a switching period, limited only by the internaltimer clamp (50µs typical).
Output Voltage Programming
The switching regulator output voltage is programmedthrough a resistor feedback network (R1 and R2 inFigure 1) connected to VFB. If the output is at its nominalvalue, the divider output is regulated to the error amplifierthreshold of 1.233V.
The output voltage is thus set according to the relation:
VOUT = 1.233 • (1 + R2/R1)
APPLICATIO S I FOR ATIO
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SG
SYNC
FG
CG
RESET(INTERNAL)
DISDRI(INTERNAL)
1698 F05
Figure 5. SYNC Time-Out Waveforms
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MARGIN Adjustment
The MARGIN input is used for adjusting the programmedoutput voltage linearly by varying the current flowing intoand out of the pin. Forcing 100µA into the pin moves theoutput voltage 5% higher. Forcing 100µA out of the pinmoves the output voltage 5% lower. With the MARGIN pinfloating, the VFB pin is regulated to the bandgap voltage of1.233V. The MARGIN pin is a high impedance input. It isimportant to keep this pin away from any noise source likethe inductor switching node. Any stray signal coupled tothe MARGIN pin can affect the switching regulator outputvoltage.
This pin is internally connected to a 16.5k resistor thatfeeds the I-V converter. The I-V converter output linearlycontrols the error amplifier offset voltage. The input of theI-V converter is biased at 1.65V. This allows the ±100µAcurrent to be obtained by connecting the MARGIN pin tothe VAUX 3.3V supply (+5%) or GND (–5%). For outputvoltage adjustment smaller than ±5%, an external resistorREXT as shown in Figure 6 is added in series with theinternal resistor to lower the current flowing into or out ofthe MARGIN pin. The value of REXT is calculated as follow:
RREQUIRED
kEXT =
51 16 5
%%
– • .
VFB loop causes the error amplifier to drive the OPTODRVpin low, forcing the primary controller to increase the dutycycle. This causes the output voltage to increase to adangerously high level. To eliminate this fault condition,the OVP comparator monitors the output voltage with aresistive divider at OVPIN. A voltage at OVPIN higher thanthe VREF potential forces the OPTODRV pin high andreduces the duty cycle, thus preventing the output voltagefrom increasing further.
The OVPIN senses the output voltage through a resistordivider network (R4 and R5 in Figure 1). The divider isratioed such that the voltage at OVPIN equals 1.233V whenthe output voltage rises to the overvoltage level. Theovervoltage level is set following the relation:
VOVERVOLTAGE = 1.233 • (1 + R5/R4)
The OVP comparator is designed to respond quickly to anovervoltage condition. A small capacitor from OVPIN toground keeps any noise spikes from coupling to the OVPpin. This simple RC filter prevents a momentary overshootfrom triggering the OVP comparator.
The OVP comparator threshold is independent of thepotential at the MARGIN pin. If the OVP function is notused, connect OVPIN to ground.
Power Good
The PWRGD pin is an open-drain output for power goodindication. PWRGD floats if VFB is above 94% of thenominal value for more than 2ms. An external pull-upresistor is required for PWRGD to swing high. PWRGDpulls low if VFB drops below 94% of the nominal value formore than 1ms. The PWRGD threshold is referenced to the1.233V bandgap voltage, which remains unchanged if theMARGIN pin is exercised.
Opto Feedback and Frequency Compensation
For a forward converter to obtain good load and lineregulation, the output voltage must be sensed and com-pared to an accurate reference potential. Any error voltagemust be amplified and fed back to the supply’s controlcircuitry where the sensed error can be corrected. In anisolated supply, the control circuitry is frequently locatedon the primary. The output error signal in this type of
7 I-V CONVERTERRMARGIN
REXT(OPTIONAL)
REDUCEVFB
INCREASEVFB
MARGIN
14
BANDGAP
AUX GEN
VDD
VAUX3.3V VAUX
0.1µF
VREF
±5% VREF
–
+ERR
VFB
VCOMP
1698 F06
8
6
APPLICATIO S I FOR ATIO
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Figure 6. Output Voltage Adjustment
Overvoltage Function
The OVPIN is used for overvoltage protection and isdesigned to protect against an open VFB loop. Opening the
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supply must cross the isolation boundary. Coupling thissignal requires an element that will withstand the isolationpotentials and still transfer the loop error signal.Optocouplers are widely used for this function due to theirability to couple DC signals. To properly apply them, anumber of factors must be considered. The gain, orcurrent transfer ratio (CTR) through an optocoupler isloosely specified and is a strong function of the inputcurrent through the diode. It changes considerably as afunction of time (aging) and temperature. The amount ofaging accelerates with higher operating current. Thisvariation directly affects the overall loop gain of the sys-tem. To be an effective optical detector, the output transis-tor of the optocoupler must have a large base area tocollect the light energy. This gives it a large collector tobase capacitance which can introduce a pole into thefeedback loop. This pole varies considerably with thecurrent and interacts with the overall loop frequencycompensation network.
The common collector optocoupler configuration removesthe miller effect due to the parasitic capacitance and
increases the frequency response. Figure 7 shows theoptocoupler feedback circuitry using the common collec-tor approach. Note that the terms RD, CTR, CDE and rπ varyfrom part to part. They also change with bias current. Thedominant pole of the opto feedback is due to RF and CF. Thefeedforward capacitor CK at the optocoupler creates a lowfrequency zero. This zero should be chosen to provide aphase boost at the loop crossover frequency. The parallelcombination of RK and RD form a high frequency pole withCK. For most optocouplers, RD is 50Ω at a DC bias of 1mA,and 25Ω at a DC bias of 2mA. The CTR term is the smallsignal AC current transfer ratio. For the QT Optoelectron-ics MOC207 optocoupler used here, the AC CTR is around1, even though the DC CTR is much lower when biased at1mA or 2mA. The first denominator term in the VC/VOUTequation has been simplified and assumes that CFB<<CC.The actual term is:
s R C C s RC CC C
C FB CC FB
C FB• • ( )• • •
•2 1+ +
+
APPLICATIO S I FOR ATIO
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VV
s C Rs R C s R C
s R C
s CR RR R
R CTRR R s r C s R C
C
OUT
C C
C C FB
K K
KK D
K D
F
D K DE F F= +
++
++
+
+ +π–
( • • )( • • )• ( • • )
• •( • • )
• ••
••
•( • • )
•( • • )
12 1
51
1
11
11
wherewhereR Optocoupler diode equivalent small signal resis ceCTR Optocoupler current transfer ratioC Optocoupler nonlinear capacitor across base to emitterr Optocoupler small signal resis ce across the base emitter
D
DE
:tan
tan
= −=== −π
20k
VREF
VCOMP
CC
CFB
RC
VREF
R2
VOUT
LTC1698
VFB
1698 F07
100k
OPTODRV
RK CK
MOC207
–
+
–
+
VREF
LT3781
VFB
VCC
CF
VC
RF
R1
RE
–
+
Figure 7. Error Signal Feedback
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A series RC network can be added in parallel with R2(Figure 7) to provide a zero for the feedback loop fre-quency compensation.
The opto driver will drive a capacitive load up to 0.1µF. Foroptocouplers with a base pin, switching signal noise canget into this high impedance node. Connect a large resis-tor, 1M or 2M between the base and the emitter. Thisincreases the diode current and the overall feedbackbandwidth slightly, and decreases the optocoupler gain.
When designing the resistor in series with the optocouplerdiode, it is important to consider the part to part variationsin the current transfer ratio and its reduction over tem-perature and aging. The bigger the biasing current, thefaster the aging. The LTC1698 opto driver is designed tosource up to 10mA of current and swing between 0.4V to(VDD – 2.5V). This should meet the design considerationof most optocouplers.
Besides the voltage feedback function, the LTC1698 optodriver couples fault signals to the primary controller andprevents catastrophic damage to the circuit. Upon currentlimit or an overvoltage fault, the ILIM or OVP comparatoroverrides the error amplifier output and forces theOPTODRV pin high. This sources maximum current intothe external optodiode and reduces the forward converterduty cycle.
Average Current Limit
The secondary current limit function is implemented bymeasuring the negative voltage across the current senseresistor RSECSEN. The current limit transconductance
amplifier ILIM has a – 25mV threshold. As shown inFigure 8, if the secondary current is small, the ICOMP pingoes low and the transistor MILIM shuts off. The potentialat VCOMP determines the OPTODRV output. If the second-ary current is large, ICOMP pulls high and forces the tran-sistor MILIM to turn on hard. Thus the current limit circuitoverrides the voltage feedback and forces OPTODRV highand injects maximum current into the external optocoupler.The RILIM resistor provides a linear relationship betweenthe current sensed and the OPTODRV output.
The ISNS and ISNSGND pins allow a true Kelvin currentsense measurement and offer true differential measure-ment across the sense resistor. A differential lowpassfilter formed by R6 and C2 removes the pulse-to-pulseinductor current ripple and generates the average sec-ondary current which is equal to the load current. Thelowpass corner frequency is typically set to 1 to 2 ordersof magnitude below the switching frequency and followsthe relationship:
RmV
I
R
Cf
SECSENLMAX
SW
=
=
π
25
61
2 210
• • •
where:
RSECSEN = Secondary current sense resistorILMAX = Maximum allowed secondary currentfSW = Forward converter switching frequency
APPLICATIO S I FOR ATIO
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–
+
–
+
12
11
2
16OPTO
ILIM
+
OPTODRV
VOUT
RCILM
CCILM
VREF
VCOMP
LTC1698
ISNSGND
ISNS
FG
CGDRIVE
25mV
20k
100k
MILIM
RILIM3k
5
ICOMP13 C2
Q4
Q3
T1
RSECSEN
1698 F08
R6
R6RDIV(OPTIONAL)
Figure 8. Secondary Average Current Limit
15
LTC1698
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If the application generates a bigger current sense voltage,a potential divider can be easily obtained by adding aresistor across C2. With this additional resistor, the volt-age sensed by the current comparator becomes:
RR R
VDIV
DIVRSENSE+ ( • )
•2 6
An RC network formed by RCILM and CCILM between ICOMPand VOUT can be used to stabilize the current limit loop.Connecting the compensation network to VOUT minimizesoutput overshoot during start-up or short-circuit recov-ery. The RCILM and CCILM zero should be chosen to be wellwithin the closed-loop crossover frequency. This pin canbe left floating if current loop compensation is not re-quired. The forward converter secondary current limit func-tion can be disabled by shorting ISNS and ISNSGND to ground.
Auxiliary 3.3V Logic Power Supply
An internal P-channel LDO (low dropout regulator) pro-duces the 3.3V auxiliary supply that can power externaldevices or drive the MARGIN pin. This supply can sourceup to 10mA of current and the current limit is providedinternally. The pin requires at least a 0.1µF bypasscapacitor.
MOSFET Selection
Two logic-level N-channel power MOSFETs (Q3 and Q4 inFigure 1) are required for most LTC1698 circuits. They areselected based primarily on the on-resistance and bodydiode considerations. The required MOSFET RDS(ON) shouldbe determined based on input and output voltage, allow-able power dissipation and maximum required outputcurrent.
The average inductor (L1) current is equal to the outputload current. This current is always flowing through eitherQ3 or Q4 with the power dissipation split up according tothe duty cycle:
DC QVV
NN
DC QVV
NN
OUT
IN
P
S
OUT
IN
P
S
( ) •
( ) – •
3
4 1
=
=
where NP/NS is the turns ratio of the transformer T1.
The RDS(ON) required for a given conduction loss can nowbe calculated by rearranging the relation P = I2R.
P I R DC Q
RP
I DC Q
P I R DC Q
RP
I DC Q
MAX Q MAX DS ON Q
DS ON QMAX Q
MAX
MAX Q MAX DS ON Q
DS ON QMAX Q
MAX
( ) ( )
( )( )
( ) ( )
( )( )
• • ( )
• ( )
• • ( )
• ( )
32
3
33
2
42
4
44
2
3
3
4
4
=
⇒ =
=
⇒ =
where IMAX is the maximum load current and PMAX is theallowable conduction loss.
In a typical 2-transistor forward converter circuit, the dutycycle is less than 50% to prevent the transformer corefrom saturating. This results in the duty cycle of Q4 beinggreater than that of Q3. Q4 will dissipate more power dueto the higher duty cycle. A lower RDS(ON) MOSFET can beused for Q4. This will slow down the turn-on time of Q4since a lower RDS(ON) MOSFET will have a larger gatecapacitance.
The next consideration for the MOSFET is the characteris-tic of the body diode. The body diodes conduct during thepower-up phase, when the LTC1698 VDD supply is ramp-ing up and the time-out circuit is adapting to the SYNCinput frequency. The CG and FG signals terminate prema-turely and the inductor current flows through the bodydiodes. The body diodes must be able to take the compa-rable amount of current as the MOSFETs. Most powerMOSFETs have the same current rating for the body diodeand the MOSFET itself.
The LTC1698 CG and FG MOSFET drivers will dissipatepower. This will increase with higher switching frequency,higher VDD or larger MOSFETs. To calculate the driverdissipation, the total gate charge Qg is used. This param-eter is found on the MOSFET manufacturers data sheet.The power dissipated in each LTC1698 MOSFET driver is:
PDRIVER = Qg • VDD • fSW
where fSW is the switching frequency of the converter.
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Power Transformer Selection
The forward transformer provides DC isolation and deliv-ers energy from the primary to the secondary. Unlike theflyback topology, the transformer in the forward converteris not an energy storage device. As such, ungapped ferritematerial is typically used. Select a power material ratedwith low loss at the switching frequency. Many coremanufacturers have selection guides and application notesfor transformer design. A brief overview of the moreimportant design considerations is presented here.
For operating frequencies greater than 100kHz, the fluxin the core is usually limited by core loss, not saturation.It is important to review both criteria when selecting thetransformer. The AC operating flux density for core loss isgiven by:
BV DC
N A fAC
IN
P e SW= • •
• • •10
2
8
where:
BAC is the AC operating flux density (gauss)DC is the operating duty cycleAe is the effective cross sectional core area (cm2)fSW is the switching frequency
To prevent core saturation during a transient condition,the peak flux density is:
BV DC MAX
N A fPK
IN MAX
P e SW= ( ) • ( )•
• •
108
The minimum secondary turns count is:
N NV V
V DC MAXS MIN P
OUT D
IN MIN( )
( )•
• ( )=
+
where:
VOUT is the secondary output voltageVD is the voltage drop across the rectifier in the secondaryVIN(MIN) is the minimum input voltageDC(MAX) is the maximum duty cycle
The core must be sized to provide sufficient window areafor the amount of wire and insulation needed. The bestperformance is achieved by making each winding a singlelayer evenly distributed across the width of the bobbin.Multiple layers may be used to increase the copper area.Interleaving the primary and secondary windings willdecrease the leakage inductance.
In a single-ended forward converter, much of the energystored in the leakage inductance is dissipated in theprimary-side MOSFET during turn-off. It is good designpractice to sandwich the secondary winding between twoprimary windings.
For the 2-transistor forward converter shown in Figure 1,energy stored in the leakage inductance is returned to theinput by diodes D1 and D2. With this topology, additionalinsulation for higher isolation can be used without signifi-cant penalty.
For a more detailed discussion on transformer core andwinding losses, see Application Note AN19.
Inductor Selection
The output inductor in a typical LTC1698 circuit is chosenfor inductance value and saturation current rating. Theoutput inductor in a forward converter operates the sameas in a buck regulator. The inductance sets the ripplecurrent, which is commonly chosen to be 40% of the fullload current. Ripple current is set by:
IV t
LRIPPLE
OUT OFF MAX=• ( )
where:
tDC MIN
fOFF MAX
SW( )
– ( )=
( )1
and DC(MIN) is calculated based on the maximum inputvoltage.
DC MINNN
VV
P
S
OUT
IN MAX( ) •
( )=
APPLICATIO S I FOR ATIO
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Once the value of the inductor has been determined, aninductor with sufficient DC current rating is selected. Coresaturation must be avoided under all operating conditions.Under start-up conditions, the converter sees a shortcircuit while charging the output capacitor. If the inductorsaturates, the peak current will dramatically increase. Thecurrent will be limited only by the primary controllerminimum on time and the circuit impedances.
High efficiency converters generally cannot afford the coreloss found in low cost iron powder cores, forcing the useof more expensive ferrite, molypermalloy, or Kool Mµ®
cores. As inductance increases, core loss goes down.Increased inductance requires more turns of wire socopper losses will increase. The optimum inductor willhave equal core and copper loss.
Ferrite designs have very low core losses and are preferredat higher switching frequencies. Therefore, design goalsconcentrate on minimizing copper loss and preventingsaturation. Kool Mµ is a very good, low-loss powdermaterial with a “soft” saturation characteristic.Molypermalloy is more efficient at higher switching fre-quencies, but is also more expensive. Surface mountdesigns are available from many manufacturers using allof these materials.
Output Capacitor Selection
The output capacitor selection is primarily determined bythe effective series resistance (ESR) to minimize voltageripple. In a forward converter application, the inductorcurrent is constantly flowing to the output capacitor,therefore, the ripple current at the output capacitor issmall. The output ripple voltage is approximately given by:
V I ESRf C
RIPPLE RIPPLESW OUT
≈ +
•
• •1
8
The output ripple is highest at maximum input voltagesince IRIPPLE increases with input voltage. Typically, oncethe ESR requirement for COUT has been satisfied thecapacitance is adequate for filtering and has the requiredRMS current rating.
Fast load current transitions at the output will appear as avoltage across the ESR of the output capacitor until thefeedback loop can change the inductor current to matchthe new load current value. As an example: at 3.3V out, a10A load step with a 0.01Ω ESR output capacitor wouldexperience a 100mV step at the output, a 3% outputchange. In surface mount applications, multiple capaci-tors may have to be placed in parallel to meet the ESRrequirement.
PC Board Layout Checklist
When laying out the printed circuit board, the followingchecklist should be used to ensure proper operation of theLTC1698. These items are also illustrated graphically inFigure 9. Check the following for your layout:
1. Keep the power circuit and the signal circuit segre-gated. Place the power circuit, shown in bold, so thatthe two MOSFET drain connections are made directly atthe transformer. The two MOSFET sources should be asclose together as possible.
2. Connect PGND directly to the sense resistor with asshort a path as possible. The MOSFET gate drive returncurrents flow through this connection.
3. Connect the 4.7µF ceramic capacitor directly betweenVDD and PGND. This supplies the FG and CG drivers andmust supply the gate drive current.
4. Bypass the VAUX supply with a 0.1µF ceramic capacitorreturned to GND.
5. Place all signal components in close proximity to theirassociated LTC1698 pins. Return all signal componentgrounds directly to the GND pin. One common connec-tion can be made to VOUT
+ from R2, R5 and CCILM.
6. Make the connection between GND and PGND right atthe LTC1698 pins.
7. Use a Kelvin-sense connection from the ISNS and ISNSGNDpins to the secondary-side current-limit resistorRSECSEN.
APPLICATIO S I FOR ATIO
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APPLICATIO S I FOR ATIO
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CG
VDDLTC1698
PGNDGND
OPTODRV
VCOMP
MARGINCFBR1
BOLD LINES INDICATE HIGH CURRENT PATHS
RCCC
VFB
SYNC
FG
VAUX
ICOMP
ISNS
ISENSGND
PWRGD
OVPIN
2
1
3
4
5
6
7
8
15
16
COUT
VOUT+
VOUT–
14
13
12
11
10
9
R2R7
D3
RSECSEN
Q4
CK
RKMOC207
C4
0.1µF R41698 F09
1k
0.1µF
4.7µF
T2
T1
0.1µF
CCILM
RCILM R5
1k
+
Q31Ω
L1
••
••
Figure 9. LTC1698 Layout Diagram
Figure 10. Simplified Single Secondary Winding 3.3V and 1.8V Output Isolated DC/DC Converter
VCOMP
VDD
LTC1698
GND
VFB
CG
FG
ISNS
SYNC
OPTODRV
VCCBIAS
L1 VOUT13.3VAT 10A
BGLT3781
SG
ISOLATIONBOUNDARY
COUT2: POSCAP, 680µF/4VL2: SUMIDA CEP125-IR8MC-HQ1, Q2: SILICONIX Si7440DP
1698 F10
VIN36V
TO 72V
VREFVC
VFB
TG••
GBIAS
4.7µF
CMDSH-3
Q1
Q2 B340A
3.01k
2.32k
L21.8µH 0.006Ω
VCC BOOST
CL– CL+
LT3710
SYNC
TGCSET
ILCOMP
SS
••
–
+
0.1µF
3.3k
33nF
10pF
CS680pF
10k
10k
180pF0.01µF
BGS
PGND
SW
BG
VAOUT
VFB
4700pF
VOUT21.8VAT 10A
COUT2
+
220Ω
19
LTC1698
1698f
Fig
ure
11. 3
6VIN
-72V
IN to
5V/
30A
Isol
ated
Syn
chro
nous
For
war
d Co
nver
ter
TYPICAL APPLICATIO S
U
V CC
13 2 1
5
1µF
0.01
µF82
pF
OVLO
SHDN
1.24
k1%
10k
4.7µ
F16
V
1000
pF
5VRE
F
6
F SET
0.1µ
F
8
SS
10
12
T2PU
LSE
ENG
P203
3
BAS2
1
BAS2
1
BAT5
4
BAT5
4S
ZVN3
310F
9V C
PGND14 V F
B
37
4
THER
M
LT37
81
SYNC
SGND
52.3
k1%
10Ω
1k
3k
1k
3.3k
FZT6
90B
0.22
µF50
V
1
10k
220p
F
MOC
207
14
314
87
5 1415
8
567
233
00pF
2200
pF
4700
pF5V
REF
5VRE
F
SG
11
SENS
E
15
BG
18
BSTR
EF
19
TG
20
BAS2
1
0.1µ
F10
0V
1mH
DO16
08C-
105
COIL
CRAF
T
V BST
1.5µ
F10
0V
1.5µ
F10
0V
0.56
µHDO
1813
P-56
1HC
0.02
2µF
1000
pF
••
SYNC
V FB
OVPI
N
MAR
GIN
I COM
P
V DD
OPTO
DRV
V AUX
0.1µ
F
1612
11I S
NSI S
NSGN
DFG
2CG
PGND
GND
LTC1
698
PWRG
D
6
8 9 7 13
1.24
k1%
976Ω
1%
4.22
k1%
3.01
k1%
104
3
V COM
P
1698
F11
MM
BZ52
40B
0.00
8Ω1%
, 1W
1000
pF10
0V
2200
pF25
0VAC•
• • •T1PU
LSE
PA02
85
PULS
EPA
0265
100Ω
10Ω
V IN+
36V
TO 7
2V
V IN–
V OUT
+
5V /3
0A
V OUT
–
RTN
10Ω
1/4W
1000
pF10
0V 10Ω
1/4W
330p
F
+
+
+
+
3.3Ω
V IN
V IN
V CC
V CC
V OUT
V CC
V OUT
V CC
V IN
V CC
0Ω2.
43k
1%RT
110
0k
1µF
ON/O
FF
V OUT
TRIM
4.7µ
F16
V
470Ω
V OUT
FZT8
53
B054
0W10
0Ω0.
25W
2k 0.25
W
5241
B11
V
20k
FMM
T619
FMM
T718
Si74
56DP
Si74
56DP
Si74
56DP
Si78
84DP
Si78
84DP
Si78
84DP
Si78
84DP
Si78
84DP
Si74
56DP
0.04
7µFB2
100
B210
0
470µ
F6.
3VPO
SCAP
470µ
F6.
3VPO
SCAP
470µ
F6.
3VPO
SCAP
470µ
F6.
3VPO
SCAP
22µF
6.3V
1µF
16V
0Ω
B054
0W
MM
BD41
48
0Ω
270k
0.25
W73
.2k
1%
1 2 34
57
20
LTC1698
1698f
Fig
ure
12. L
T378
1/LT
C169
8 36
V IN-
72V I
N to
3.3
V/15
A Is
olat
ed S
ynch
rono
us F
orw
ard
Conv
erte
r-Qu
arte
r Bric
k
TYPICAL APPLICATIO S
U
V CC
13 2 1
5
1µF
0.01
µF82
pF
OVLO
SHDN
1.24
k1%
10k
270k
1/4W
100µ
F20
V
1000
pF
5VRE
F
6
F SET
4700
pF
8
SS
10
BAT5
4
BAT5
4
PULS
E EN
GPA
0184
BAS2
1
BAS2
1
BAT5
4ZE
TEX
ZVN3
310F
9V CPG
ND12 V FB
37
4
THER
M
LT37
81
SYNC
SGND
52.3
k1%
10Ω
1k
3k1k
1k
2k
FZT6
90B
4.7µ
F
0.22
µF
1
10k
5VRE
F
MOC
207
71
4381
54
5 1415
6 5
82
3300
pF47
00pF
220p
F
5VRE
F
14SG
+
11
SENS
EBG
18
BSTR
EF
1916
17
TGNC
NC
15
20
BAS2
1
0.1µ
F
1mH
DO16
08C-
105
COIL
CRAF
T
V BST
3.3µ
HD0
1608
C-33
2CO
ILCR
AFT
0.02
2µF
1000
pF
••
SYNC
V FB
OVPI
N
MAR
GIN
I COM
P
V DD
OPTO
DRV
V AUX
0.1µ
F
1612
11FG
2CG
PGND
GND
LTC1
698
PWRG
D
6
8 9 7 13
1.78
k1%
1.24
k1%
3.01
k1%
2.43
k1%
34
10
V COM
P
1698
F12
1k
0.22
µF
MBR
0540
0.03
Ω
Si74
56DP
Si74
56DP
1000
pF10
0V
1000
pF10
0V
2200
pF25
0V
MUR
S120
MUR
S120
10Ω
•• •
T138
431
SCHO
TT
10Ω
MM
BT39
06
MM
BD91
4
MM
BT39
06
V IN+
V IN–
0.82
µF10
0V0.
82µF
100V
×2
V OUT
+
V OUT
–
330p
F
+
+
+
330µ
F6.
3VKE
MET
T520
330µ
F6.
3VKE
MET
T520
330µ
F6.
3VKE
MET
T520
330µ
F6.
3VKE
MET
T520
+
3.3Ω
V CC
V IN
V CC
V CC
10k
2.43
k1
%RT
110
0k
0.1µ
F
ON/O
FF
TRIM
V OUT
+
4.7Ω
10V
MM
BZ52
40B 470Ω
–+
3.01
k1%
3.01
k1%3.
01k
1%3.01
k1%
100Ω
1/4W
100Ω
1/4W
9V
V OUT
V OUT
+
3 4
2
1LT
1783
CS5
+SEN
SE
–SEN
SE
OPTI
ONAL
DIF
FERE
NTIA
L SE
NSE*
*
V CC
V IN
5VRE
FFQT7
N10L
100Ω
1/4W
100Ω
1/4W
47k
62k
1/4W
4.7µ
F
MM
BT39
04
OPTI
ONAL
FAS
T ST
ART*
V IN
18V
MM
BZ52
48B
•0.
1µF
100Ω
9V
5
I SNS
I SNS
GND
0.1µ
F
1k
1k
Si78
92DP
Si78
92DP
Si78
92DP
Si78
92DP
10Ω
1/4W 10Ω
1/4W
R OUT
(OPT
IONA
L)
73.2
k1%
3300
pFR IN
(OPT
IONA
L)
1 2 34
5 678
21
LTC1698
1698f
TYPICAL APPLICATIO S
U
V CC
14 2 1
5
1µF
25V
82pF
OVLO
SHDN
1.24
k1%
73.2
k1%
24k
10k
270k
0.25
W
68µF
25V
1000
pF
56k
5VRE
F
6
F SET
4700
pF
8
SS
1013
BAT5
4
BAT5
4
T2M
IDCO
M, I
NC31
264R
BAS2
1LT1
BAS2
1LT1
BAT5
4
ZVN3
310F
9V C
PGND
12
I MAX
V FB
37
4
THER
M
LT37
81
SYNC
SGND
52.3
k1%
10Ω
1k
3k
1k
3.3k
20k
0.25
W10
0Ω0.
25W
FZT6
03ZE
TEX
4.7µ
F16
V
0.22
µF 50V
1
10k
5VRE
FIS
O1M
OC20
7
71
433 1
46
5
14
15
6 5
82
3300
pF
4700
pF
47Ω
0.01
µF50
V
5VRE
F
15SG
+
11
SENS
E
16
BG
18
BSTR
EF
19
TG
17
20
BAS2
1LT1
0.1µ
F10
0V
1mH
DO16
08C-
105
COIL
CRAF
T
BLKS
ENS
V BST
220p
F
1.5µ
F10
0V
4.7µ
HDO
1608
C-47
2CO
ILCR
AFT
0.02
2µF
1000
pF
•
•
SYNC
V FB
OVPI
N
MAR
GIN
I COM
P
V DD
OPTO
DRV
V AUX
0.1µ
F50
V
0.1µ
F50
V
16
I SNS
I SNS
GND
FG2
CG
PGND
GND
LTC1
698
PWRG
D6
8 9 7 13
909Ω
0.1%
8.25
k0.
1%
34
1110
12
V COM
P
1698
F13
1k
0.01
µF
MUR
S120
T3
0.02
5Ω1/
2W
3 67
54
SUD4
0N10
-25
SUD4
0N10
-25
SUD4
0N10
-25
470p
F10
0V
470p
F10
0V
2200
pF25
0V
MUR
S120
T3M
URS1
20T3
10Ω
1
81112 10 9
•• •
2
T1EF
D25
10Ω
V IN+
V IN–
1.5µ
F10
0V1.
5µF
100V
V OUT
+
V OUT
–
68µF
25V
AVX
68µF
25V
AVX
68µF
25V
AVX
68µF
25V
AVX
22Ω
0.25
W
22Ω
0.25
W
25µH
MAG
INC
CORE
5538
0-A2
18T
#18
AWG
330p
F
+
+
+
+
V TOP
3.3Ω
V IN
V CC
V IN
V CC
V TOP
V TOP
V OUT
–
V OUT
+V C
C15
VM
MBZ
5245
BLT1
20k
0.1µ
F50
V
0.33
µF 50V
V OUT
+
BAT5
4
10Ω
0.25
W
10V
MM
BZ52
40BL
T1
10k
1k
UNLE
SS N
OTED
:AL
L PN
Ps M
MBT
39O6
LT1
NC
0.01
5Ω
100p
F
200Ω
18V
MM
BZ52
48BL
T1
110Ω
0.1µ
F
T1 E
FD25
-3F3
LP =
120
µH2m
il GA
P EA
CH L
EG
2M POLY
ESTE
RFI
LM
SQUA
RE 0
.031
INCH
MAR
GIN
TAPE
PINS
9-1
0 5T
BIF
ILAR
33A
WG
PINS
2-5
12T
BIF
ILAR
33A
WG
PINS
4-3
7T
QUAD
FILA
R 26
AWG
PINS
7,8
-11,
12 1
2T B
IFIL
AR 2
4AW
GPI
NS 6
-4 8
T QU
ADFI
LAR
26AW
G
Si44
86EY
×2Si
4486
EY×2
•
215Ω
215Ω
0.03
3µF
Figu
re 1
3. 3
6VIN
-72V
IN to
12V
/5A
Isol
ated
Syn
chro
nous
For
war
d Co
nver
ter
22
LTC1698
1698f
GN16 (SSOP) 0502
1 2 3 4 5 6 7 8
.229 – .244(5.817 – 6.198)
.150 – .157**(3.810 – 3.988)
16 15 14 13
.189 – .196*(4.801 – 4.978)
12 11 10 9
.016 – .050(0.406 – 1.270)
.015 ± .004(0.38 ± 0.10)
× 45°
0° – 8° TYP.007 – .0098(0.178 – 0.249)
.053 – .068(1.351 – 1.727)
.008 – .012(0.203 – 0.305)
.004 – .0098(0.102 – 0.249)
.0250(0.635)
BSC
.009(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 TYP.0165 ± .0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES(MILLIMETERS)
NOTE:1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
GN Package16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
U
PACKAGE DESCRIPTIO
23
LTC1698
1698f
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
.016 – .050(0.406 – 1.270)
.010 – .020(0.254 – 0.508)
× 45°
0° – 8° TYP.008 – .010
(0.203 – 0.254)
1
N
2 3 4 5 6 7 8
N/2
.150 – .157(3.810 – 3.988)
NOTE 3
16 15 14 13
.386 – .394(9.804 – 10.008)
NOTE 3
.228 – .244(5.791 – 6.197)
12 11 10 9
S16 0502
.053 – .069(1.346 – 1.752)
.014 – .019(0.355 – 0.483)
TYP
.004 – .010(0.101 – 0.254)
.050(1.270)
BSC
.245MIN
N
1 2 3 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005 .050 BSC
.030 ±.005 TYP
INCHES(MILLIMETERS)
NOTE:1. DIMENSIONS IN
2. DRAWING NOT TO SCALE3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S Package16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
24
LTC1698
1698f
LINEAR TECHNOLOGY CORPORATION 2000
LT/TP 0203 2K • PRINTED IN THE USA
PART NUMBER DESCRIPTION COMMENTS
LT1339 High Power Synchronous DC/DC Controller Operation Up to 60V MaximumLT1425 Isolated Flyback Switching Regulator General Purpose with External Application Resistor
LT1431 Programmable Reference 0.4% Initial Voltage Tolerance
LT1680 High Power DC/DC Step-Up Controller Operation Up to 60V MaximumLT1681 Dual Transistor Synchronous Forward Controller Operation Up to 72V Maximum
LT1725 General Purpose Isolated Flyback Controller Drives External Power MOSFET with External ISENSE Resistor
LT1737 High Power Isolated Flyback Controller Sense Output Voltage Directly from Primary-Side WindingLT3710 Secondary Side Synchronous Post Regulator Generates a Regulated Auxiliary Output in Isolated DC/DC Converters, Dual
N-Channel MOSFET Synchronous Drivers
LT3781 Dual Transistor Synchronous Forward Controller Operation up to 72V Maximum
RELATED PARTS
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear.com
TYPICAL APPLICATIO S
U
LT3781/LTC1698 Isolated 3.3V/15A Converter
LT3781/LTC1698 Isolated 3.3V/15A Converter
LOAD CURRENT (A)0
EFFI
CIEN
CY (%
)
95
90
85
80
75
70
655 10 15 20
1698 TA01
25 30
VIN = 36V
VIN = 72V
VIN = 48V
IOUT (XX)0
EFFI
CIEN
CY (%
)95
90
85
80
75
7012
1698 TA02
3 6 9 15
VIN = 36V
VIN = 72V
VIN = 48V
LT3781/LTC1698 Isolated 3.3V/15A ConverterEfficiency vs Load Current
LT3781/LTC1698 Isolated 5V/30A ConverterEfficiency vs Load Current
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