First Timepix3 results
Wafer#0 → AAPVX6HAAPVX6H
11 36 35 34 33 32
10 31 30 29 28 27 26 25 24 23
9 22 21 20 19 18 17 16 15 14 13 12
8 11 10 9 8 7 6 5 4 3 2 1
7 69 68 67 66 65 64 63 62 61 60 59 58 57
6 56 55 54 53 52 51 50 49 48 47 46 45 44
5 43 42 41 40 39 38 37 36 35 34 33 32 31
4 30 29 28 27 26 25 24 23 22 21 20
3 19 18 17 16 15 14 13 12 11
2 10 9 8 7 6 5 4
1 3 2 1
A B C D E F G H I J K L M
B (No Pad Extenders)
A ( With Pad Extenders)
@NIKHEF
Chip Mounted @CERN W0_J6
Some photos
Diced chips in gelpack
First tests• Power ON -> “No Smoke”
– ~780mA after Reset (no clock)
• Blocks tested:– SLVS IO
• receiver at 40MHz (40Mbps) • Driver up to 320MHz (640Mbps)
– Command decoder• Receive commands • Sends control commands (END_CMD, ACK_CMD, WRG_CMD and OTHERCHIP_CMD) • Send periphery data output (DAC settings, Timer output…)
– PLL• Clearly see in the scope clock multiplication working 40, 80, 160 MHz
– Output block• Data received @640Mbps
– End Of Column• CTPR load
• CTPR read
Data Packet=0x00000 (40-bits)Timer:RequestTimeLow=0x44
END_CMD=0x71Timer:RequestTimeLow=0x44ChipID=0x0000
Summary
• Start testing on Monday morning• 2 chip mounted: 1 @CERN and 1 @Nikhef• Timepix3 periphery is working as expected– Periphery is ~80% tested
• Pixel Matrix not yet tested
• Spare
Basic Start-up SettingsOp Header
[Hex]PayloadIn
[Hex] Operation description
20 001EPLL ON ClkPM=40MHz and 1 phasePLLOut=OFF
10 0901Chan_mask=0000_00018b10b enabledDataOutput @ 640mbpsClk_Out disabled
30 0079
Polarity: holesOperation mode: TOA & TOTAcknowledge command enabledEOC gray counters enabledTest Pulse enabledSuper-pixel oscillator enabled