© 2017 Renesas Electronics Corporation. All rights reserved.
GATEWAY PROCESSORS
EVOLUTION IN AUTOMOTIVE NETWORKS
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
AUTOMOTIVECOMMUNICATION
• Increasing Feature Sets
• Increasing Data Rates
• Introduction of new
Communication Methods
• New Communication
Method as Island Solution
• Network
Architectural Changes
30 Years ago
Simple communication by voltage levels or serial (RS-232)
20 Years ago
CAN Bus introduction
Dedicated functionality per ECU
Few communication objects, diagnosis
10 Years ago
Increase of E/E functionality
Many more electric devices replace and expand mechanic ones
Upgrading of existing network types
Today
Centralization & integration phases
Introduction of backbone networks and overall system
Merging of ECUs: Functionality of several ECUs goes into one
Distribution of tasks among the system
Future
Internet, cloud computing, mobile maintenance and upgrade
Car-2-car communication
Autonomous driving
Ad-hoc, individually modifiable options
20 kbit/s
50 …500
kbit/s(CAN)
1 … 10 Mbit/s(CAN,
FlexRay)
2 … 100 Mbit/s
(CAN-FD, Ethernet)
100 Mbit/s … x Gbit/s
(HighspeedEthernet)
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GATEWAY PROCESSOR EVOLUTIONIN AUTOMOTIVE NETWORKS
Network challenges and architectural changes
Consequences on gateway processor architecture
Hardware based routing – a gateway processing peripheral
Tunneling of CAN(-FD)
The Renesas Prototype
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CHALLENGES AND
ARCHITECTURAL NETWORK CHANGES
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THE GATEWAY – WITHIN CARS ON THE MARKET TODAY
• Several Bus Systems are
attached to a Central
Gateway,
• Max. Busload: 50%,
Classical CAN Framing
Overhead: 1/3 of Data.
Central GatewayTotal Data Bit Rate (all interfaces): 1.5 Mbit/s
Total Data Transfers (excl. overhead): 125 kB/s
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
Diagnosis
Chassis Bus
FlexRay or CAN
Max. 10 Mbit/s,
500 kbit/s to GW
Powertrain Bus
CAN
Max. 500 kbit/s
Body / Infotainment Bus
CAN
Max. 500 kbit/s
LIN Bus
Max. 20 kbit/s
CAN-FD Bus
Mirrors all
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EVOLUTION – ADAPTATION OF ARCHITECTURE IS NEEDED HERE
• More Bus Systems are
attached to a Central
Gateway at higher rates
• CAN: SW-Update:
Max. Busload: 100%;
Regular Traffic: 50%
• Ethernet: SW-Update:
8 Mbit/s
[Program Speed];
Regular Traffic: CAN
max. rate of 2.5 Mbit/s
• Probably even
harder conditions?
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
Diagnosis
Chassis Bus
FlexRay or CAN-FD
Max. 10 Mbit/s,
5 Mbit/s to GW
Powertrain Bus
CAN-FD
Max. 5 Mbit/s
Body Bus
CAN-FD
Max. 5 Mbit/s
Diag. Ethernet
Mirrors all
ECU
ECU
Update via Mobile, only
Programming Speed Limit,
Copies to all
Mobile
Entertainment Ethernet
SW-Update: max. 8 Mbit/s per ECU,
Regular Traffic: max. 2.5 Mbit/s
ECULIN Bus
ECU
ECU
ECU
ECU
Comfort Bus
CAN-FD
Max. 5 Mbit/s
Central GatewaySW-Update Total Data Bit Rate (all interfaces): 72 Mbit/s
SW-Update Total Data Transfers (excl. overhead): 8.6 MB/s
Diagnosis operation: 30 Mbit/s (Data: 3.6 MB/s)
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
NEW NETWORK TOPOLOGY
Chassis Bus
FlexRay or CAN-FD
Powertrain Bus
CAN-FD
Body Bus
CAN-FD
Entertainment Bus
Ethernet
LIN Bus
Comfort Bus
CAN-FD
Backbone Ethernet
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
Diagnosis
ECU
ECU
Mobile
ECU
ECU
ECU
ECU
ECU
Backbone Router / Switch
Domain
SwitchDomain
Gateway
Domain
GatewayDomain
Gateway
Domain
Gateway
ECU
ECU
ECU
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
NEW NETWORK TOPOLOGY
Chassis Bus
FlexRay or CAN-FD
Powertrain Bus
CAN-FD
Body Bus
CAN-FD
Entertainment Bus
EthernetLIN Bus
Comfort Bus
CAN-FD
Backbone Ethernet Ring
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
Diagnosis
ECU
ECU
Mobile
ECU
ECU
ECU
ECU
ECU
External Gateway
ECU
ECU
ECU
Domain
SwitchDomain
Gateway
Domain
GatewayDomain
Gateway
Domain
Gateway
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
ETHERNET IN THE CAR?
Physical Layer
• Qualification of PHY devices
(temperature range, reliability, lifetime)
• Media to be used
(existing cable-tree, shielding)
• Second-Source Policy
BroadR-Reach technology (single twisted pair) –
more than one manufacturer is required
Data Link Layer
• Communication reliability of Latency and Jitter
Physical Layer Solutions
Qualification processes are in good progress
Single twisted pair Ethernet (BroadR-Reach
technology) is in focus to be used
Meanwhile more than one manufacturer of
BroadR-Reach Ethernet PHY devices is available
Data Link Layer Solutions
Introduction of Time Sensitive Networking (TSN)
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
ETHERNET PROTOCOL, DELAYS AND JITTER
Apart from pure signal run times through transceivers and cables,
Ethernet may have additional delay and jitter sources:
• Ethernet supports large frames, which may block urgent transmissions
• Queue (FIFO) handling in switches,
when a transmit port gets data from several reception ports
Measures in a switch for TSN (Time Sensitive Networking)
S1 S2 S3 S1 S2 S3 S1 S2 S3
Q2 Q3 Q1 Q2 Q1 Q3 Q2 Q1 Q2 Q3
AVB Queues with Priorities
AVB including Pre-emption Support
Time Aware Shaping
Not Optimized: “Best Effort”
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
CHALLENGES OF A GATEWAY PROCESSOR
Page 11
•Scalable architecture for several gateway applications
•Compact design tailored for individual product
•Gateway architecture must be QoS aware
•High priority messages must go through the system faster than low priority traffic
•Latency has to be guaranteed under all operation conditions, independently from CPU load
•Precise coordination of activities among connected ECU's
•Considered on Ethernet by IEEE1588PTP protocol.
•The gateway could play the role of a master clock device
•Ensure consistency of data tuples
•Tunnelling of one network domain to another
•Transport protocol support
•Mirroring of information for diagnostics
•Switching of Ethernet traffic (various protocols)
•Security issues (tailored solution required)
Flexibility,Integration
& Cost
Guaranteed Latency
Domain Support
Global Time Support
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ARCHITECTURAL CONSIDERATIONS
FOR GATEWAY PROCESSORS
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
ACTUAL ARCHITECTURE SITUATION
Data traffic situation
during a SW-Update
process, with typical
system speed
FR
Controller
CAN
Controller
CAN
Controller
ETH
Controller
Peripheral Bus: 8.6 MB/s
CPU Core
80 MHz
RAM
Signal Routing4 Instr./Signal
588 kB/s 588 kB/s 1.96 MB/s588 kB/s
Bus Performance: 40 MHz, 4 Bytes in 2 Cycles: 80 MB/s
Bus Load: 10.8% (for GW Traffic)
CPU Load:
43.0% (routing)
10.8% (I/O)
34.9% (IRQ)
88.7 % (total)
CAN
Controller
588 kB/s
FOTA ETH
Controller
FOTA Rate: 4.3 MB/s
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
ALTERNATIVES …
Increase the CPU
core speed …
FR
Controller
CAN
Controller
CAN
Controller
ETH
Controller
CPU Core 2
Local RAM
588 kB/s 588 kB/s 1.96 MB/s588 kB/s
CAN
Controller
588 kB/s
FOTA ETH
Controller
CPU Core 3
Local RAM
Or add additional
CPU cores …
The bottleneck stays
at the peripheral bus
CPU Core + RAM
160 … 300 MHz
Peripheral Bus: High data rate (Signal + Frame Routing)
Global RAM Global RAM
CPU Core + RAM
80 MHz
Peripheral Bus
CPU Core 1
Local RAM
Peripheral Bus 2Peripheral Bus 1
So multiplication of
all would be the best
we have seen so far
(with the limitation
that the splitting is a
binding factor)
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
Peripherals
COMMUNICATION-ORIENTED DESIGNEXTENSION OF BUS SYSTEM
• Application CPU core
• Reasonable calculation power for
• Higher level tasks (applications)
• Safety and Supervision
• Less Interrupt load
• Focus on main ECU tasks
S
L
A
V
E
S
L
A
V
E
Routing Engine /
RAM
Optimized Communication Bus
Application
CPU Core
Local RAM
M
S
T
R
S
H
A
R
E
D
R
A
M
Comm.
Peripherals
M
S
T
R
Peripheral Bus
Comm. CPU Core /
Global RAM
S
L
A
V
E
Peripherals
M
A
S
T
E
R
S
L
A
V
E
• Communication (Gateway-) CPU, Routing Engine and Communication Bus
• Optimized on speed and power for communication requirements
• Additional feature implementation
• Low latency
• Event Driven
M
S
T
R
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
GATEWAY IP SYSTEM
• Moving the load of faster &
increasing communication
• Frame Routing
• Peripheral direct usage,
Configuration
Communication / Gateway IP
Configuration
Application CPU System
CPU Agent
Peripheral Bus
P
E
R
I
P
H
E
R
A
L
P
E
R
I
P
H
E
R
A
L
P
E
R
I
P
H
E
R
A
L
Communication Bus (Data / Descriptors)
CPU Core 1
(Application / Supervision)
Comm. Agents
of Peripherals
M
S
T
R
Data
RAM
S
L
A
V
E
Other Peripherals,
Security IP
CPU Core 2
(Signal Gateway Application)
Global
RAM
D
M
A
M
S
T
R
Routing Engine
DE
SC
-
RIP
TO
RSD
ES
C
DE
SC
IRQ
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
GATEWAY IP PROTOTYPE
• Moving the load of faster &
increasing communication
• Frame Routing
• Configuration
Communication / Gateway IP
Configuration
Application CPU System
Peripheral Bus
P
E
R
I
P
H
E
R
A
L
P
E
R
I
P
H
E
R
A
L
Communication Bus (Data / Descriptors)
FPGA CPU Core
(Handshake, Configuration)
Comm. Agents
of Peripherals
M
S
T
R
Data
RAM
S
L
A
V
E
Configuration Peripherals
(USB, ETH)
Shared
RAM
CPU Agent
P
E
R
I
P
H
E
R
A
L
M
S
T
R
Routing Engine
DE
SC
-
RIP
TO
RSD
ES
C
DE
SC
IRQ(to FPGA
CPU Core)
Local
RAM
Application CPU Core
(Supervision, Signal Routing)
Local
RAM
PC Control Host
IRQ
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GATEWAY IP DETAILS
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
CPU Agent
Peripheral Bus
P
E
R
I
P
H
E
R
A
L
P
E
R
I
P
H
E
R
A
L
P
E
R
I
P
H
E
R
A
L
Communication Bus (Data / Descriptors)
CPU Core 1
(Application / Supervision)
Comm. Agents
of Peripherals
M
S
T
R
Data
RAM
S
L
A
V
E
Other Peripherals,
Security IP
CPU Core 2
(Gateway Application)
Global
RAM
D
M
A
M
S
T
R
Routing Engine
DE
SC
-
RIP
TO
RSD
ES
C
DE
SC
RENESAS AUTOMOTIVE GATEWAY UNIT
Page 19
Up to 8 TSN capable Eth interfaces
10/100/1000 Mbit/s full duplex
MAC Security Module available
Up to 16 CAN/CANFD interfaces
CPU
Agent
CAN
AgentEth
Agent
using 1722a
tunnel protocol
native Ethernet
frame switching
CAN
Agent… …
Communication Bus
Routing Engine Data RAM
Eth
Agent
MAC
SEC
Ethernet
Frames
DMA
PERIPHERAL
ACCESS
Physical Layer
IRQ
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
KEY FEATURES
Page 20
Autonomous routing based on
MAC
VLAN
IEEE 1722 (this includes CAN messages)
802.1AS support for time synchronisation (gPTP timer)
Prioritisation of time critical messages by integrated QoS
solution
Allow end to end QoS accross networks
Timestamping on all interfaces
Based on global 802.1AS (gPTP time, second + nano
second part)
SW optimised data interface based on flexible queues
structure
All data exchanged via integrated Data RAM
CAN/CANFD tunnelling over IEEE 1722a
Time period conversion (convert message repetition rate)
Message bunching (multiple CAN messages in one Eth
frame)
CAN messages are tunnelled in up to 64 streams
(shared by 8 interfaces)
Tunnelling concept expandable to other protocols (e.g.
FlexRay)
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
SCALING DOWN TO DOMAIN LEVEL PRODUCTS *
Next evolution step*: Gateway hardware support on a more cost-effective base for local domains at lower performance
• Routing through DMA and Global RAM
• CPU Agent integration into peripheral interfaces
• Some routing engine functionality moves into CPU agents
• CPU Signal routing case by case
Significant size reduction by removal of wide
communication bus system & data RAM
CAN Eth…
Global RAM
Ethernet
Frames & Descriptors
PERIPHERAL
ACCESS
IRQCPU
Agent
DM
A
CPU
Agent
DM
A
CAN
CPU
Agent
DM
A
CPU
Agent
CAN
AgentEth
Agent
CAN
Agent
… …
Routing Engine / RAM
Eth
Agent
MAC
SEC
DMA
PERIPH.
IRQ
Concentration* &
Integration*
CPU Core 1 CPU Core 2
* Implementation under discussion.
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
SCALABLE DESIGNS – MULTIPLE APPLICATIONS *
Amount of Ethernet and CAN / other peripheral connections can be flexibly created – for dedicated product lines
ECU
ECU
ECU
ECU
ECU
ECU
ECU
ECU
Diagnosis
ECU
ECU
FOTA
ECU
ECU
ECU
ECU
ECU
Router / Switch
Switch Gateway Gateway Gateway Gateway
ECU
ECU
ECU
Eth Eth
Routing Engine / Agent / RAM / Comm. Bus
Eth Eth
Eth
MAC
SEC
TSN Switch of
Backbone
SoC* with GW-IP
Gateway of Domain
µC* with GW-IP
End-Station components
MAC
SEC
CAN Eth…
CPU
Agent
CPU
Agent
CAN
CPU
Agent
* Implementation under discussion.
© 2017 Renesas Electronics Corporation. All rights reserved. BIG IDEAS FOR EVERY SPACE
USING THE GATEWAY IP – SW VIEW POINT (END-STATION)*
Global RAM
contains RX and TX Queues
Rx0
Rx1
Rx..
Tx1
Tx0
Tx..
• Global RAM:
Fast access by CPU
Descriptors for
routing information
• Peripheral access
required only to set
Tx-Request and for
configuration
• Signal routing by
CPU software
• Frame routing with
hardware support
GW-IP
Components
CAN Eth…
Ethernet
Frames & Descriptors
PERIPHERAL
ACCESS
IRQ
CPU
Agent
DM
A
CPU
Agent
DM
A
CAN
CPU
Agent
DM
A
CPU
Core CPU
Core
PERIPHERAL ACCESS
* Implementation under discussion.
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EXECUTION FLOW: TRANSMISSION BY SOFTWARE (FULL GW-IP)
24
Example flow of a
transmission:
• All data handling
beyond the CPU
RAM area is done
by hardware
• Transmit Request
is the only
peripheral access
CPU sub system
Global RAM
Handling for 16 Tx
Queues
Handling for64 Rx
Queues
0 1 15
16 Tx queues (cyclic or linear) consisting on descriptor and data. Size under SW control.
... 0 1 63
64 Rx queues (cyclic or linear) consisting on descriptor and data. Size under SW control
...
AXI
GW-CPU
Master
Master
APBInterrupts
16
TxR
eqb
its
64
Dat
a av
aila
ble
Data RAM
1. SW places one or more frames into a queue (data and
descriptor)
2. SW sets transmit request for this
queue (peripheral access)
3. HW (Agent) reads descriptor(s) from
Global RAM
4. HW (Agent) reads data from URAM
5. Data is available in Gateway IP for further processing
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FRAME ORGANIZATION IN RAM
All kind of data is handled within IEEE 1722a Ethernet frames (Example: CAN Payload)
MAC SA/DA
VLAN Tag
Type AVTP
SubType TSCF
Sequence #
Stream ID
Timestamp
Total Payload Length Reserved
Payload
Type (CAN), Frame Length, Flags, Bus ID
Timestamp
Identifier
CAN Data (Payload)
Type (CAN), Frame Length, Flags, Bus ID
Timestamp
Identifier
CAN Data (Payload)
…
Header
(42 B
yte
s)
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EXAMPLE ROUTING SCHEME(TUNNELING OF CAN FRAMES)
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SOURCE(GW1)
AVB Stream #1
AVB Stream #2
AVB Stream #3
GW1: Classification in CAN A AFLCAN-A 100 to 110 #1CAN-A 200 to 2FF #2CAN-A 153, 1017 #3CAN-A 100 to 1FF #4
GW1: GW Forwarding Table#1 1722-StreamId=0x3302_2104, target=Eth-0#2 1722-StreamId=0xAB60_0177, target=Eth-0#3 1722-StreamId=0x87A1_bF87, target=Eth-0#4 1722-StreamId=don’t care, target=CAN-B
These are example CAN IDs used for communication on CAN-A
CAN Eth 1 CANCAN Eth N CANs (on different destination GWs)GW1 to GW2 and GW3
CAN Eth N CANs (on same destination GW)GW1 to GW2
Inside the GW hash numbers (#x) are used to distinguish streams
Here only local CAN is target, so Stream Id is not required (but possible if stream is also required in other GW)
CAN
-A
CAN
-B
Source100104127153223224
10081017
ETH-0
CAN CAN
GW3
CAN
-F
CAN
-G
ETH-0
CAN CAN
GW2
CAN
-C
CAN
-D
CAN
-E
ETH-0
C N
The forwarding engine applies the 1722 header containing the Stream Id. This stream Id is used by Ethernet backbone to identify the end points (target DCs) of this stream. The shown numbers are examples only.
A
System DefinitionCAN-A 100 to 110 CAN-C, ECAN-A 200 to 2FF CAN-GCAN-A 153, 1017 CAN-D, E, F, GCAN-A 100 to 1FF CAN-B
GW1
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DESTINATIONS(GW2, GW3)
AVB Stream #10x3302_2104
AVB Stream #20xAB60_0177
AVB Stream #30x87A1_bF87
CAN
-A
CAN
-B
Source100104127153223224
10081017
ETH-0
CAN CAN
CAN
-F
CAN
-G
ETH-0
CAN CAN
CAN
-C
CAN
-D
CAN
-E
ETH-0
C NA
GW1: GW Forwarding Table#4 target=CAN-B
GW2: GW Forwarding Table#1 CAN-C, CAN-E#3 CAN-D, CAN-E
GW3: GW Forwarding Table#2 CAN-G#3 CAN-F, CAN-G
GW2: Classification by Eth filter1722-StreamId=0x3302_2104 #11722-StreamId=0x87A1_bF87 #3
GW3: Classification by Eth filter1722-StreamId=0xAB60_0177 #21722-StreamId=0x87A1_bF87 #3
There is no requirement to use unique hash (#x) numbers in all GWs
GW3GW2
System DefinitionCAN-A 100 to 110 – AVB#1 CAN-C, ECAN-A 200 to 2FF – AVB#2 CAN-GCAN-A 153, 1017 – AVB#3 CAN-D, E, F, GCAN-A 100 to 1FF CAN-B
GW1
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OVERALL RESULT(GW1, GW2, GW3)
AVB Stream #10x3302_2104
AVB Stream #20xAB60_0177
AVB Stream #30x87A1_bF87
CAN
-A
CAN
-B
Source100104127153223224
10081017
ETH-0
CAN CAN
CAN
-F
CAN
-G
ETH-0
CAN CAN
CAN
-C
CAN
-D
CAN
-E
ETH-0
C NA
GW3GW2
System DefinitionCAN-A 100 to 110 – AVB#1 CAN-C, ECAN-A 200 to 2FF – AVB#2 CAN-GCAN-A 153, 1017 – AVB#3 CAN-D, E, F, GCAN-A 100 to 1FF CAN-B
Sink CAN-B100104 127153
Sink CAN-C
100104
Sink CAN-D
1531017
Sink CAN-E1001041531017
Sink CAN-F
1531017
Sink CAN-G2232241531017
GW1
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FPGA BASED PROTOTYPE
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GATEWAY IP FPGA BASED PROTOTYPE
31
Prototype Kit:
Evaluation of Gateway-IP using Ethernet TSN
(including security support by MACSEC) and CAN-FD
Evaluation of new network
architectures
(feasibility studies)
Implementation using two
high density FPGA types.
Prototype versions:
Under development,
continuous improvement is
ongoing.
Prototype Board
Gateway / Switch
Ethernet Time Sensitive Networking (AVB)
CAN FD
AVB/TSN Switch Port 1
AVB/TSN Switch Port 2
AVB/TSN Switch Port 5
CAN-FD 6CAN-FD 1 CAN-FD 2
FPGA
Gateway-IP:
Engine
CAN-FD
Ethernet TSN
Power unit
CAN
TransceiverCAN
TransceiverCAN
Transceiver
CAN
TransceiverCAN
TransceiverEthernet
PHY
App. CPU
Shared RAM
USB Serial Host I/F
E1 Debugger I/F…
…
CPU
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BIG IDEAS FOR EVERY SPACE
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