Gedae Portability: From Simulation to Gedae Portability: From Simulation to DSPs to the Cell Broadband EngineDSPs to the Cell Broadband Engine
James Steed, William Lundgren, Kerry BarnesJames Steed, William Lundgren, Kerry Barnes
Gedae, Inc.Gedae, Inc.www.gedae.com856 - 231- 4458856 - 231- 4458
HPEC 2007: Multicore Processors and Their Impact on DoD HPEC Systems
The Software Architecture Makes The Software Architecture Makes Hardware Refreshes DifficultHardware Refreshes Difficult
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PE-0PE-0
Code0
PE-1PE-1
Code1
PE-2PE-2
Code2
PE-3PE-3
Code3
PE-APE-A
CodeA
PE-BPE-B
CodeB
PE-CPE-C
CodeC
PE-DPE-D
CodeD
PE-EPE-E
CodeE
PE-FPE-F
CodeF
Old System
New System
Problems that Reduce Software Problems that Reduce Software PortabilityPortability
Languages and compilers are based on serial processorsLanguages and compilers are based on serial processors
Software architecture is buried in the codeSoftware architecture is buried in the code
Differences in multiprocessor/multicore hardware necessitate Differences in multiprocessor/multicore hardware necessitate changes to the software architecturechanges to the software architecture– Number of processorsNumber of processors
– InterconnectionInterconnection
– BandwidthBandwidth
– Processor speedProcessor speed
– Memory sizeMemory size
– Memory structureMemory structure
Gedae mitigates the risk of porting software by automating the Gedae mitigates the risk of porting software by automating the incorporation of the software architecture incorporation of the software architecture
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Application EnvironmentApplication Environment
Search and track using four audio channelsSearch and track using four audio channels
Display using camera directed by pan-tilt unitDisplay using camera directed by pan-tilt unit
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Playstation 3
PPEPPE
USB AudioUSB
Audio
USBUSBGimbalGimbal
SysMemSysMem
SPESPE
SPESPE
SPESPE
SPESPE
SPESPE SPESPE
BUS
BUS
Stages in DevelopmentStages in Development
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System SpecificationsSystem Specifications
Simulation Mercury AdapDev Playstation 3
Processors 1 4 PowerPC AltiVec (500 MHz), 1 Pentium
1 PPE, 6 SPEs
Sensors Datafile of 4 recorded channels
ICS 610 ADC PCI Board, 4 microphones
M-Audio Quattro USB Device, 4 microphones
Output Constellation display
Directed Perception D46-17 Pan-Tilt Unit
Directed Perception D46-17 Pan-Tilt Unit
UI Rendered scene
Matrix Vision BlueFOX USB Camera displayed using Video for Gedae
Matrix Vision BlueFOX USB Camera displayed using Video for Gedae
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Algorithm Specified in GedaeAlgorithm Specified in Gedae
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4 Channel Audio Input
Low Pass Filtering
Correlate the 4 Channels
Detection Algorithm
Pan and Tilt Camera
Same flow graph used for simulation, quad DSP board, and Cell/B.E. processor
Simulation Using Gedae-SimSimulation Using Gedae-Sim
Audio data captured from actual Audio data captured from actual model train, recorded to filemodel train, recorded to file
Simulated 3-d environment Simulated 3-d environment created with train, track, camera, created with train, track, camera, and light and light
Scene renderedScene rendered
from vantage-from vantage-
point of camerapoint of camera
Gedae-Sim usedGedae-Sim used
to verify algorithmto verify algorithm
and run onand run on
multiple virtualmultiple virtual
processorsprocessors
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Spot Formation Output
Rendered Scene
Mercury AdapDevMercury AdapDev
Pentium III development hostPentium III development host– 1.26 GHz1.26 GHz
– 1 GB SDRAM1 GB SDRAM
Quad PowerPC 500MHz Quad PowerPC 500MHz (MCP7410)(MCP7410)– AltiVec instruction setAltiVec instruction set
– 2 MB L2 cache2 MB L2 cache
– 256 MB SDRAM256 MB SDRAM
– DMA enginesDMA engines
RACE++ switched-fabric RACE++ switched-fabric architecturearchitecture
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Mercury AdapDev Mercury AdapDev Implementation Implementation
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Put Preprocessing of 4 channels in 4 partitions
Add Correlation to 0-th partition
DMA between
processors
Map partitions to 4 PowerPCs
Nonblocking transfer of audio data from host to PowerPCs
Strip mine for cache performance
Cell/B.E. ArchitectureCell/B.E. Architecture
Power Processing Power Processing Element (PPE)Element (PPE)
8 Synergistic 8 Synergistic Processing Elements Processing Elements (SPE)(SPE)– VMX SIMD VMX SIMD
instruction setinstruction set
– DMA enginesDMA engines
– 256 kB Local 256 kB Local Storage (LS)Storage (LS)
System MemorySystem Memory
Element Interconnect Element Interconnect Bus (EIB)Bus (EIB)– Over 200 GB/sOver 200 GB/s
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Cell/B.E. ImplementationCell/B.E. Implementation
Alter implementation to use 6 Alter implementation to use 6 SPEsSPEs
Alter implementation to fit in Alter implementation to fit in the SPEs’ 256KB Local Storagethe SPEs’ 256KB Local Storage
Maximize use of SPEsMaximize use of SPEs
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Put Preprocessing of 4 channels in 4 partitions
Strip mine to reduce memory footprint
Map partitions to 6 SPEs
Use 2 SPEs to perform 1st stage of correlation
Gedae was used to easily move the application to new Gedae was used to easily move the application to new hardwarehardware
Changes to the implementation were handled by automation Changes to the implementation were handled by automation and simple GUIs, not changes to codeand simple GUIs, not changes to code
High performance gains were realized with minimal effortHigh performance gains were realized with minimal effort
ResultsResults
Target Programmer Hours Performance
Simulation 4 weeks -
Mercury AdapDev 6 hours 3 Hz
Cell/B.E. 2 hours 15 Hz
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