December 2017 DocID031369 Rev 1 1/27
www.st.com
AN5121 Application note
HDMI ESD protection and signal conditioning products for STBs
Introduction HDMI™ (High Definition Multimedia Interface) is a proprietary audio/video digital interface for transferring uncompressed video data and compressed or uncompressed audio data. This link is composed of one HDMI source and one HDMI sink linked together by an HDMI cable. As shown below, HDMI link is composed of 4 physically separate communication channels, which are TMDS, DDC, CEC (optional) and HEAC (optional).
Figure 1: HDMI block diagram
The TMDS channel is composed of 4 differential pairs, used to carry video, audio and auxiliary data with a maximum data throughput of 18 Gbps for HDMI 2.0, from the HDMI source to the HDMI sink.
The VESA DDC channel is composed of 2 lines based on I²C protocol. It is used for configuration and status exchange between a single source and a single sink. HDMI requires a maximum data rate of 100 kbps corresponding to I²C standard mode speed operation.
The optional CEC channel provides control functions between up to 10 HDMI devices. It is a one-wire bidirectional communication bus, based on CENELEC AV-link protocol.
The HEAC channel, composed of HEC and/or ARC channel, use the utility pin and the HPD pin to provide bidirectional 100 Mbps Ethernet link (HDMI Ethernet channel) and an audio channel (audio return channel) from the sink to the source.
This application note presents the HDMI™ port electrical characteristics for each channel and the constraints induced on ESD protection device choice.
Finally, ST offering in ESD protection for HDMI port and signal conditioning for DDC/CEC lines is presented.
Contents AN5121
2/27 DocID031369 Rev 1
Contents
1 EMI/EMC for STB: ESD test on system .......................................... 3
2 TMDS lines ....................................................................................... 4
2.1 HDMI 1.4 and 2.0 requirements ........................................................ 4
2.1.1 Data rate ............................................................................................. 4
2.1.2 Differential impedance ........................................................................ 4
2.1.3 Eye diagram ....................................................................................... 4
2.2 PCB layout design ............................................................................. 6
3 Control lines .................................................................................... 8
3.1 DDC bus ........................................................................................... 8
3.1.1 HDMI standard requirements ............................................................. 8
3.1.2 Benefits of switched pull-up on DDC bus ........................................... 9
3.2 +5 V power pin .................................................................................. 9
3.3 HPD line .......................................................................................... 10
4 ST offering for ESD protection of TMDS lanes: ........................... 11
4.1 HSP051-4M10 ................................................................................. 11
4.2 HSP053-4M5 ................................................................................... 13
5 ST offer for control lines ............................................................... 15
5.1 HDMI2Cx family features ................................................................ 15
5.2 HDMI2Cx for HDMI™ source devices ............................................. 15
5.2.1 Control lines only .............................................................................. 15
5.2.2 Full port protection ............................................................................ 18
5.3 HDMI2Cx for HDMI™ sink device ................................................... 22
5.3.1 Control lines: HDMI2C2-5F2 ............................................................ 22
5.3.2 Full port protection: HDMI2C2-14HD ............................................... 23
6 Conclusion ..................................................................................... 25
7 Revision history ............................................................................ 26
AN5121 EMI/EMC for STB: ESD test on system
DocID031369 Rev 1 3/27
1 EMI/EMC for STB: ESD test on system
All equipment that needs to comply with CISPR20:2006/EN55020:2006 or CISPR24:2010/EN55024:2010 standards must be able to withstand up to ±8 kV air discharge or ±4 kV contact discharge according to IEC61000-4-2 standard. The surge current waveform is given in the following figure and table.
Figure 2: IEC61000-4-2 typical current waveform, contact discharge
Table 1: IEC61000-4-2 ESD level, contact discharge
Level Indicated
voltage kV First peak current of
discharge ±15% A Rise time
tr(±25%) ns
Current (±30%)
at 30 ns A
Current (±30%)
at 60 ns A
1 2 7.5 0.8 4 2
2 4 15 0.8 8 4
3 6 22.5 0.8 12 6
4 8 30 0.8 16 8
The reference point to measure the time for the current at 30 ns and 60 ns is the moment when the current first reached 10% of the discharge current first peak. The rise time, tr is the time interval between 10% and 90% value of first peak current.
The equipment must keep on operating properly after the test. No loss of function is allowed after the test when the system is used properly, only failures, causing temporary delay in processing and recovering automatically, are acceptable. No change of actual operating state, such as change of channel or stored data and settings, is allowed as a result of the application of the test. During the test, degradation of performance is allowed.
TMDS lines AN5121
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2 TMDS lines
2.1 HDMI 1.4 and 2.0 requirements
2.1.1 Data rate
HDMI link is composed of 4 high speed TMDS lanes: 3 dedicated to data, 1 dedicated to clock synchronization. The clock lane speed is 1/10th of data lane speed for a data rate lower than 3.4 Gbps, and 1/40th of data lane speed for a data rate between 3.4 Gbps and 6 Gbps. The data rate on HDMI TMDS lanes depends on video resolution, frame rate and color depth. The pixel clock rate versus video resolution is given in EIA/CEA 861 standard (Table 2: "HDMI Source and Sink TMDS lane characteristic impedance" in EIA/CEA 861-D).
2.1.2 Differential impedance
To ensure a good signal propagation minimizing signal distortion, the entire transmission channel must be impedance matched. The impedance is checked through TDR measurements for HDMI sink and cable. It is also checked on source side since HDMI 2.0 specification. The TDR rise time must be set to 200 ps defined between 10% and 90%.
Table 2: HDMI Source and Sink TMDS lane characteristic impedance
Data rate
Source Sink
Through
connector
Termination
impedance
Through
connector
Termination
impedance
RD ≤ 3.4 Gbps NA NA 100 Ω ±15 %(1) 100 Ω ±10%
3.4 Gbps < RD
≤ 6 Gbps 100 Ω ±10%
75 Ω min.150 Ω
max. 100 Ω ±15% (1) 100 Ω ±10%
Notes:
(1)Single excursion of 100 Ω ±25% for a duration less than 250 µs is admitted.
2.1.3 Eye diagram
The signal quality transmission is evaluated through eye diagram measurement. HDMI standard defines the eye diagram mask function of TMDS data rate. Eye diagrams are measured at HDMI connector output (TP1) for data rate lower than 3.4 Gbps, and at the end of reference cable (TP2_EQ) for data rate between 3.4 Gbps and 6 Gbps.
AN5121 TMDS lines
DocID031369 Rev 1 5/27
Figure 3: HDMI source test point for eye diagram
Figure 4: HDMI source eye diagram mask at TP1, Rbit ≤ 3.4 Gbps
Signal Characteristics Minimal Nominal Maximum Units
Eye Height 400 1560 mV
Eye Width 0.700 UI
UI
-250
-500
-750
0
250
500
750
Diffe
rentialV
oltage,m
V
0 0.25 0.5 0.75 1
Minimum
Eye Height
Minimum
Eye Width
TMDS lines AN5121
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Figure 5: HDMI source eye diagram mask at TP2_EQ, 3.4 Gbps < Rbit ≤ 6.0 Gbps
2.2 PCB layout design
To ensure a good signal propagation minimizing signal distortion, the TMDS channel must be impedance matching. The PCB layout must be carefully designed with a differential impedance without ESD protection device as close as possible to 100 Ω unless specific requirements.
The ESD protection/EMI filter must be placed as close as possible to the connector for ESD safety reasons.
The tracks between ESD protection device and the line to be protected and between the protection device and the ground plane must be also as short as possible in order to minimize inductor effect on clamping voltage value. Indeed the track parasitic inductor adds an extra voltage to the clamping voltage of the ESD protection device.
-250
-500
-750
0
250
500
750
Diffe
rentialV
oltage,m
V
UI
0 0.25 0.5 0.75 1
Minimum
Eye Height
Minimum
Eye Width
Signal characteristics
TMDS bit rate (Gbps)
Unit
3.4<Rbit<3.712 3.712<Rbit<5.94 5.94<Rbit<6.0
Eye Height 335 -19.66Rbit²+106.74Rbit+209.58 150 mV
Eye Width 0.6-0.0332Rbit²+0.2312Rbit+0.1998
0.4 UI
AN5121 TMDS lines
DocID031369 Rev 1 7/27
Figure 6: Unoptimized ESD protection layout
Figure 7: Optimized ESD protection layout
DAT2+
GND
DAT2-
DAT1+
GND
DAT1-
DAT0+
GND
DAT1-
CLK+
GND
CLK-
CEC
UTILITY
SCL
SDA
GND
+5V
HPDI
VCL_IO-ESD=L IO-GND.dI/dt
VCL_ESD-GND=LESD-GND.dI/dt
VCL_ESD
+
+
VCL_IO-GND
GND connection
LESD-GND
LIO-ESD
≅
≅
Tracks between IO and ESD protection
and between ESD protection
and ground connection add extra
voltage during ESD event DAT2+
GND
DAT2-
DAT1+
GND
DAT1-
DAT0+
GND
DAT1-
CLK+
GND
CLK-
CEC
UTILITY
SCL
SDA
GND
+5V
HPD
VCL_IO-GNDVCL_ESD
Multiple GND connection
≅
Control lines AN5121
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3 Control lines
3.1 DDC bus
3.1.1 HDMI standard requirements
The HDMI DDC bus is a point-to-point bidirectional communication link based on I²C bus specification. DDC bus meets I²C specifications in standard mode, meaning a maximum data rate of 100 kbit/s. I²C standard mode timing specifications are shown in Table 3: "I²C timing requirements in standard mode (I²C specification, UM10204 rev.5)".
Table 3: I²C timing requirements in standard mode (I²C specification, UM10204 rev.5)
Symbol Parameter Min. Max. Unit
fSCL SCL clock frequency 0 100 kHz
tr Rise time
1000 ns
tf Fall time
300 ns
All values are referenced to VIL(max.)(0.3 x VDD) and VIH(min.)(0.7 x VDD) levels.
HDMI devices must have DDC electrical characteristics complying with the values shown in Table 4: "Maximum capacitance of DDC lines (HDMI 1.4, table 4-35)", Table 5: "Maximum capacitance of DDC lines for automotive (HDMI 1.4, table 4-36)" and Table 6: "HDMI 1.4 pull-up resistors on DDC lines (HDMI 1.4, table 4-37)". That means a maximum total DDC bus capacitance of 1.5 nF in automotive applications (HDMI source + automotive cable + CE relay cable + automotive relay cable + HDMI sink), with SDA/SCL pull-up resistor between 1.5 kΩ and 2.0 kΩ on source side, and with SCL pull-up resistor of 47 kΩ ±10% on sink side.
Although HDMI standard specifies a maximum capacitance of 700 pF on DDC bus for cable, some on the market can have a higher capacitance value.
For instance, the capacitance SDA to ground or SCL to ground has been measured at 1.7 nF on a 15 meter cable.
Table 4: Maximum capacitance of DDC lines (HDMI 1.4, table 4-35)
Item HDMI source Cable assembly HDMI sink
SDA-DDC/CEC ground 50 pF 700 pF 50 pF
SCL-DDC/CEC ground 50 pF 700 pF 50 pF
Table 5: Maximum capacitance of DDC lines for automotive (HDMI 1.4, table 4-36)
Item HDMI
source
Cable assembly HDMI
sink Automotive
cable
CE relay
cable
Automotive
relay cable
SDA-DDC/CEC ground 50 pF 700 pF 210 pF 490 pF 50 pF
SCL-DDC/CEC ground 50 pF 700 pF 210 pF 490 pF 50 pF
AN5121 Control lines
DocID031369 Rev 1 9/27
Table 6: HDMI 1.4 pull-up resistors on DDC lines (HDMI 1.4, table 4-37)
Item Min. Typ. Max.
SDA and SCL source pull-up resistors 1.5 kΩ
2.0 kΩ
SCL sink pull-up resistor 42.3 kΩ 47 kΩ 51.7 kΩ
The failure to respect I²C timing and electrical requirements can generate interoperability issues at end customer side.
3.1.2 Benefits of switched pull-up on DDC bus
It is difficult to fulfill I²C timing specifications according to HDMI requirements in the worst conditions of DDC bus capacitance. The below equation gives the relation between rise time, pull-up resistor and bus capacitance for a rise time defined between 0.3 VDD and 0.7 VDD.
𝑡𝑟 = 0.85 ∗ 𝑅𝑃𝑈 ∗ 𝐶𝐷𝐷𝐶𝐵𝑈𝑆
Considering a pull-up resistor of 2.0 kΩ with a bus capacitance of 800 pF, the rise time is 1.36 µs, higher than the 1 µs maximum value specified in HDMI standard.
Whereas a 1.5 kΩ pull-up resistor with the same 800 pF bus capacitance, the rise time is 1.02 µs, higher than the maximum allowed value.
HDMI standard allows the use of a switched pull-up circuit to manage high capacitance buses as described in I²C standard.
A switched pull-up circuit helps to fulfill HDMI and I²C timing requirements on DDC bus by temporarily decreasing the pull-up resistor value. Also it reduces the interoperability risk.
Figure 8: Rise time measurement with and without dynamic pull-up resistor,
CLOAD = 450 pF
Figure 9: Rise time measurement with and without dynamic pull-up resistor,
CLOAD = 1.5 nF
3.2 +5 V power pin
The HDMI connector provides a pin allowing the source to supply +5 V to the cable and sink. All HDMI sources must be able to supply a minimum of 55 mA to the +5 V power pin, with an overcurrent protection of no more than 0.5 A. The voltage on the source output must be between 4.8 V and 5.3 V.
An HDMI sink must draw no more than 50 mA when powered off from +5 V power pin, and no more than 10 mA when powered on. The voltage on the sink input must be between 4.7 V and 5.3 V.
Control lines AN5121
10/27 DocID031369 Rev 1
Figure 10: HDMI test points
Table 7: +5 V power pin voltage
Item Min. Max.
Source output (TP1) 4.8 V 5.3 V
Sink input (TP2) 4.7 V 5.3 V
The +5 V power pin is used to supply power to the sink E-EDID EEPROM even if the sink is powered off or in standby mode.
3.3 HPD line
An HDMI source device uses an HPD line to detect if a sink device is connected to the end of HDMI cable. The HPD line is set to high level by the sink, sometimes through a 1 kΩ resistor connected to +5 V power pin.
On sink side, the HDP high level must be between 2.4 V and 5.3 V, on source side between 2.0 V and 5.3 V.
HEAC (HDMI Ethernet and audio return channel) optional feature can also use the HPD line.
AN5121 ST offering for ESD protection of TMDS lanes:
DocID031369 Rev 1 11/27
4 ST offering for ESD protection of TMDS lanes:
4.1 HSP051-4M10
The HSP051-4M10 is a 4-line diode array ESD protection, suitable to protect TMDS lanes of HDMI connector. Its ultra-low IO/GND parasitic capacitance helps to minimize the impact of ESD protection device on TDR response as shown in Figure 11: "HSP051-4M10 TDR measurements, tr 10%-90% = 200 ps (typical value)". The very high frequency bandwidth ensures a non-noticeable impact on eye diagram up to 3.4 Gbps (Figure 12: "Eye diagram at 3.4 Gbps, without HSP051-4M10"), and a small impact at 5.94 Gbps.
Figure 11: HSP051-4M10 TDR measurements, tr 10%-90% = 200 ps (typical value)
ST offering for ESD protection of TMDS lanes: AN5121
12/27 DocID031369 Rev 1
Figure 12: Eye diagram at 3.4 Gbps, without HSP051-4M10
Figure 13: Eye diagram at 3.4 Gbps, with HSP051-4M10
Figure 14: Eye diagram at 5.94 Gbps, without HSP051-4M10
Figure 15: Eye diagram at 5.94 Gbps, with HSP051-4M10
HDMI TMDS lanes require two HSP051-4M10 for ESD protection. The typical electrical schematic is given in Figure 16: "HSP051-4M10 electrical schematic" and an example of layout in Figure 17: "Layout example with 2 x HSP051-4M10".
Figure 16: HSP051-4M10 electrical schematic
Figure 17: Layout example with 2 x HSP051-4M10
28.1 ps/div
200 mV/div
28.1 ps/div
200 mV/div
SCL
HPD
DAT1+DAT2-
DAT0-
DAT0+DAT1-
0
CLK-
CLK+
HDMI_A
CN5
TDMS DATA2+1
TMDS DATA2 SHIELD2
TDMS DATA2-3
TDMS DATA1+4
TMDS DATA1 SHIELD5
TDMS DATA1-6
TDMS DATA0+7
TMDS DATA0 SHIELD8
TDMS DATA0-9
TMDS CLOCK+10
TMDS CLOCK SHIELD11
TMDS CLOCK-12
CEC13
UTILITY14
SCL15
SDA16
DDC/C EC GND17
+5V18
HPD19
SH
IE
LD
20
SH
IE
LD
21
SH
IE
LD
23
SH
IE
LD
22
0
DAT2+
U2
HSP051-4M10
IO11IO22GND3IO34IO45
NC10 NC9 GND8 NC7 NC6
5V_HDMI
00
U5
HSP051-4M10
IO11IO22GND3IO34IO45
NC10 NC9 GND8 NC7 NC6
00CEC
UTILITY
SDA
DAT2+
GND
DAT2-
DAT1+
GND
DAT1-
DAT0+
GND
DAT1-
CLK+
GND
CLK-
CEC
UTILITY
SCL
SDA
GND
+5V
HPD
AN5121 ST offering for ESD protection of TMDS lanes:
DocID031369 Rev 1 13/27
4.2 HSP053-4M5
The HSP053-4M5 is a 4-line diode array ESD protection, suitable to protect TMDS lanes of HDMI connector. Its ultra-low IO/GND parasitic capacitance helps to minimize the impact of ESD protection device on TDR response as shown in Figure 18: "HSP053-4M5 TDR measurements, tr 10%-90% = 200 ps (typical value)". The very high frequency bandwidth ensures a non-noticeable impact on eye diagram up to 3.4 Gbps (Figure 19: "Eye diagram at 3.4 Gbps, without HSP053-4M5"), and a small impact at 5.94 Gbps.
Figure 18: HSP053-4M5 TDR measurements, tr 10%-90% = 200 ps (typical value)
ST offering for ESD protection of TMDS lanes: AN5121
14/27 DocID031369 Rev 1
Figure 19: Eye diagram at 3.4 Gbps, without HSP053-4M5
Figure 20: Eye diagram at 3.4 Gbps, with HSP053-4M5
Figure 21: Eye diagram at 5.94 Gbps, without HSP053-4M5
Figure 22: Eye diagram at 5.94 Gbps, with HSP053-4M5
HDMI TMDS lanes require two HSP053-4M5 for ESD protection. The typical electrical schematic is given in Figure 23: "HSP053-4M5 electrical schematic" and an example of layout in Figure 24: "Layout example with 2 x HSP053-4M5".
Figure 23: HSP053-4M5 electrical schematic
Figure 24: Layout example with 2 x HSP053-4M5
AN5121 ST offer for control lines
DocID031369 Rev 1 15/27
5 ST offer for control lines
5.1 HDMI2Cx family features
ESD protection The HDMI2Cx product family able to withstand ± 8 kV contact discharge according to IEC61000-4-2 standard on connector pins and ± 2 kV HBM on other pins.
DDC bus The HDMI2Cx product family integrates level shifter on DDC bus, allowing translating high level voltage from 5 V on cable side down to VDD_IC on system side. It integrates dynamic pull-up resistors on DDC bus, allowing high capacitive cables to exceed HDMI standard specifications. Those dynamic pull-ups on cable side help to improve interoperability by ensuring a rise time on SDA and SCL lines compliant with HDMI and I²C specifications even with a capacitive load twice higher than HDMI requirements. The buffers on DDC bus ensure signal reshaping to improve signal quality transmission and ensure the compliance with capacitance measurements.
HPD Unless specified, the HDMI2Cx product integrates a level shifter on HPD line, ensuring signal reshaping and voltage translation from 5 V on cable side to VDD_IC on system side. The HPD line is pulled down through an integrated current source.
+5 V power pin All HDMI2Cx products dedicated to source devices integrates on the +5 V power line a current limiter and a thermal protection to manage short circuit event on the +5 V HDMI connector pin.
5.2 HDMI2Cx for HDMI™ source devices
5.2.1 Control lines only
5.2.1.1 HDMI2C1-6C1
The HDMI2C1-6C1 is an integrated ESD protection and a signal-conditioning device for control lines of HDMI source. It provides current limitation and short-circuit protection on 5 V power pin. The HDMI2C1-6C1 is available in QFN18 leads, 500 µm pitch package.
ST offer for control lines AN5121
16/27 DocID031369 Rev 1
Figure 25: HDMI2C1-6C1 package
Figure 26: HDMI2C1-6C1 pinout, top view
The active low fault pin is used to indicate a short-circuit or an overtemperature protection activation on 5V_OUT pin.
The HDMI2C1-6C1 (Figure 26: "HDMI2C1-6C1 pinout, top view") pinout provides an easy routing. The typical electrical schematic is given in Figure 27: "HDMI2C1-6C1 electrical schematic" and a layout example in Figure 28: "HDMI2C1-6C1 layout example".
Either HSP053-4M5, HSP051-4M10 or ECMF04-4HSWM10 can be used to protect TMDS lanes against ESD.
Figure 27: HDMI2C1-6C1 electrical schematic
Figure 28: HDMI2C1-6C1 layout example
The HDMI2C1-6C1 is fully compliant with HDMI 1.4b standard requirements.
5.2.1.2 HDMI2C4-5F2
The HDMI2C4-5F2 provides ESD protection on all HDMI connector control pins, and integrates level shifter, signal conditioning and dynamic pull-up on DDC pin in Flip Chip package. It also integrates current limiter and short-circuit protection on + 5 V power pin.
The HDMI2C4-5F2 is dedicated to HDMI source device.
DAT2+
GND
DAT2-
DAT1+
GND
DAT1-
DAT0+
GND
DAT1-
CLK+
GND
CLK-
CEC
UTILITY
SCL
SDA
GND
+5V
HPD
VDD_CEC
VD
D_I
C
VDD_5V
HP
D_I
C
FA
ULT
_IC
CE
C_I
C
SC
L_IC
SD
A_IC
10
14
1 551
10
14
15
18
9
6
VD
D_C
EC
_IC
HE
AC
-
HE
AC
+
HDMI2C1-6C1
DC E C
RP
U_
CE
C
RP
U_
SC
L
RP
U_
SD
A
RP
U_
FA
UL
T_
IC
RP
U_
CE
C_
IC
RP
U_
SC
L_
IC
RP
U_
SD
A_
IC
CV D D _ IC
CV D D _C E C _ IC
CV D D _ 5V
CV D D _C E C
C5 V _O U T
AN5121 ST offer for control lines
DocID031369 Rev 1 17/27
Figure 29: HDMI2C4-5F2 package
Figure 30: HDMI2C4-5F2 pin-out, bump side
The ENABLE_IC pin is used to enable or disable level shifters on DDC bus and on HPD line to reduce power consumption in standby mode. Setting the ENABLE_IC pin to low level disables all integrated level shifter and disconnects 5V_OUT pin from VDD_5V.
The HDMI2C4-5F2 provides ESD protection on CEC line without level shifting.
The typical electrical layout and an example of layout are shown in Figure 31: "HDMI2C4-5F2 electrical schematic" and Figure 32: "HDMI2C4-5F2 layout example".
Either HSP053-4M5, HSP051-4M10 or ECMF04-4HSWM10 can be used to protect TMDS lanes against ESD.
Figure 31: HDMI2C4-5F2 electrical schematic
Figure 32: HDMI2C4-5F2 layout example
The HDMI2C4-5F2 is fully compliant with HDMI 2.0 standard requirements.
C B A
1
2
3
4
GND
SDA
SCL
VDD_5V SDA_IC
SCL_IC
VDD_IC
HPD_IC
ENABLE_IC
CEC
5V_OUT
HPD
500
500
650
0
DAT2-DAT1+
DAT1-DAT0+
DAT0-CLK+
CLK-
VDD_IC
R627k
CEC
D1SCHOTTKY DIODE
VDD_5V
R1
10k
C31u
R61k
HPD_IC
3V3
ENABLE_IC
C1100n
0
HDMI_A
CN2
TDMS DATA2+1
TMDS DATA2 SHIELD2
TDMS DATA2-3
TDMS DATA1+4
TMDS DATA1 SHIELD5
TDMS DATA1-6
TDMS DATA0+7
TMDS DATA0 SHIELD8
TDMS DATA0-9
TMDS CLOCK+10
TMDS CLOCK SHIELD11
TMDS CLOCK-12
CEC13
UTILITY14
SCL15
SDA16
DDC/C EC GND17
+5V18
HPD19
SH
IE
LD
20
SH
IE
LD
21
SH
IE
LD
23
SH
IE
LD
22
00
SCL_SYS
SDA_SYS
U2
HDMI2C3-5F2
SDAA1SCLA2CECB2SDA_ICA3SCL_ICA4
GN
DB
1V
DD
_IC
B4
HPDC1 5V_OUTC2 EN_ICB3 VDD_5VC3 HPD_ICC4
R2
10k
R3
10k
R4
1.8k
R5
1.8k
C21u
0
DAT2+
SCL_IC
SDA_IC
HP
D_
IC
EN
AB
LE
_IC
CEC_IC
VDD_5V
VDD_IC
RP U _ S C L _ IC
RP U _ S D A _ IC
RP U _ E N A B L E
CV D D _ IC
CV
DD
_5
V
C5 V _ O U T
R5 V _ O U T
RP U _ S C L
RP U _ S D A
HDMI2C3-5F2
A1
C1
A4
C4
DAT2+
GND
DAT2-
DAT1+
GND
DAT1-
DAT0+
GND
DAT1-
CLK+
GND
CLK-
CEC
UTILITY
SCL
SDA
GND
+5V
HPD
RP
U_
CE
C
DC E C
VDD_3V3
ST offer for control lines AN5121
18/27 DocID031369 Rev 1
5.2.2 Full port protection
5.2.2.1 HDMI2C1-14HD
The HDMI2C1-14HD provides ESD protection for all HDMI connector pins and provides signal conditioning for control link of HDMI source in a single QFN36 lead package with 500 µm pitch. It integrates a current limiter and short-circuit protection on the + 5 V power pin.
Figure 33: HDMI2C1-14HD package
Figure 34: HDMI2C1-14HD pinout, top view
Its high frequency bandwidth and low clamping voltage on TMDS lines ensure the compatibility with the highest resolution of HDMI standard.
Figure 35: HDMI2C1-14HD, differential attenuation Sdd 21 typical value
Figure 36: HDMI2C1-14HD, TDR on TDMS lane tr 10%-90% = 200 ps,typical value
The eye diagrams shown in Figure 37: "Eye diagram at 3.4 Gbps, without HDMI2C1-14HD" and Figure 38: "Eye diagram at 3.4 Gbps, with HDMI2C1-14HD" highlight a very low impact on signal transmission ensuring a good signal integrity.
100k 1M 10M 100M 1G 10G
-6
-5
-4
-3
-2
-1
0
f/Hz
AN5121 ST offer for control lines
DocID031369 Rev 1 19/27
Figure 37: Eye diagram at 3.4 Gbps, without HDMI2C1-14HD
Figure 38: Eye diagram at 3.4 Gbps, with HDMI2C1-14HD
Figure 39: Eye diagram at 5.94 Gbps, without HDMI2C1-14HD
Figure 40: Eye diagram at 5.94 Gbps, with HDMI2C1-14HD
The active low fault pin is used to indicate a short-circuit or an overtemperature protection activation on 5V_OUT pin.
The typical electrical schematic is given in Figure 41: "HDMI2C1-14HD electrical schematic" and a layout example in Figure 42: "HDMI2C1-14HD layout example".
Figure 41: HDMI2C1-14HD electrical schematic
Figure 42: HDMI2C1-14HD layout example
The HDMI2C1-14HD is compliant with HDMI 2.0 standard requirements.
28.1ps/div
200mV/div
28.1ps/div
200mV/div
1
1 1 1 9
2 9
DAT2+
GND
DAT2-
DAT1+
GND
DAT1-
DAT0+
GND
DAT1-
CLK+
GND
CLK-
CEC
UTILITY
SCL
SDA
GND
+5V
HPD
SCL_IC
SDA_IC
CEC_IC
VD
D_5V
VD
D_IC
FAULT
CEC_IC
VD
D_C
EC
_IC
VD
D_C
EC
HEAC+
HEAC-
DC
EC
RP
U_
CE
C_
IC
RP
U_
SC
L
RP
U_
SD
A
C5
V_
OU
T
RP
U_
SC
L_
IC
RP
U_
SD
A_
I C
RP U _ C E C
CV
DD
_IC
CV
DD
_5
V
CV
DD
_C
EC
RP
U_
FA
UL
T
CV
DD
_C
EC
_I C
CE S D _D IS H
HDMI2C1-14HD
ST offer for control lines AN5121
20/27 DocID031369 Rev 1
5.2.2.2 HDMI2C1-14HDS
The HDMI2C1-14HDS provides ESD protection for all HDMI connector pins and provides signal conditioning for control link of HDMI source in a single QFN24 lead package with 500 µm pitch. It integrates a current limiter and short-circuit protection on the +5 V power pin.
The HDMI2C1-14HDS is dedicated to HDMI source devices.
Figure 43: HDMI2C1-14HDS package
Figure 44: HDMI2C1-14HDS pinout, top view
Its high frequency bandwidth and low clamping voltage on TMDS lines ensure the compatibility with the highest resolution of HDMI standard.
Figure 45: HDMI2C1-14HDS differential attenuation Sdd21 typical value
Figure 46: HDMI2C1-14HDS, TDR on TDMS lane tr 10%-90%= 200 ps, typical value
The eye diagrams shown from Figure 47: "Eye diagram at 3.4 Gbps, without HDMI2C1-14HDS" to Figure 50: "Eye diagram at 5.94 Gbps, with HDMI2C1-14HDS" highlight a very low impact on signal transmission ensuring a good signal integrity.
100k 1M 10M 100M 1G 10G
-6
-5
-4
-3
-2
-1
0
f/Hz
AN5121 ST offer for control lines
DocID031369 Rev 1 21/27
Figure 47: Eye diagram at 3.4 Gbps, without HDMI2C1-14HDS
Figure 48: Eye diagram at 3.4 Gbps, with HDMI2C1-14HDS
Figure 49: Eye diagram at 5.94 Gbps, without HDMI2C1-14HDS
Figure 50: Eye diagram at 5.94 Gbps, with HDMI2C1-14HDS
The active low fault pin is used to indicate a short-circuit or an overtemperature protection activation on 5V_OUT pin.
The typical electrical schematic is given in Figure 51: "HDMI2C1-14HDS electrical schematic".
Figure 51: HDMI2C1-14HDS electrical schematic
Figure 52: HDMI2C1-14HDS layout example
The HDMI2C1-14HDS is compliant with HDMI 2.0 standard requirements.
28.1ps/div
200mV/div
28.1ps/div
200mV/div
DAT2+
GND
DAT2-
DAT1+
GND
DAT1-
DAT0+
GND
DAT1-
CLK+
GND
CLK-
CEC
UTILITY
SCL
SDA
GND
+5V
HPD
SC
L_
IC
SD
A_
IC
VD
D_
5V
VD
D_
IC
FAULT
CEC_IC
VD
D_
CE
C_
IC
VD
D_
CE
C
1
6 13
18
1924
127
HP
D_
IC
CV
DD
_5
V
RP
U_
SC
L
RP U _ S C L _ IC
RP U _ S D A _ IC
RP U _ F A U L T
CV
DD
_IC
RP
U_
SD
A
RP
U_
CE
C
DC
EC
CV
DD
_C
EC
_IC
VD
D_
CE
C_
CO
N
C5
V_
OU
T
RP U _ C E C _ IC
HDMI2C1-14HDS
ST offer for control lines AN5121
22/27 DocID031369 Rev 1
5.3 HDMI2Cx for HDMI™ sink device
5.3.1 Control lines: HDMI2C2-5F2
The HDMI2C2-5F2 provides ESD protection on all HDMI connector control pins, and integrates level shifter, signal conditioning and dynamic pull-up on DDC pin in Flip Chip package.
The HDMI2C2-5F2 is dedicated to HDMI sink device.
Figure 53: HDMI2C2-5F2 package
Figure 54: HDMI2C2-5F2 pinout, bump side
The enable pin allows the + 5 V power pin to be sensed and/or the HDMI2C2-5F2 to be disabled so to reduce power consumption in standby mode. Setting the ENABLE_IC pin to low level disables all integrated level shifters and disconnects 5V_OUT pin from VDD_5V.
The typical electrical schematic is given in Figure 55: "HDMI2C2-5F2 electrical schematic" and a layout example in Figure 56: "HDMI2C2-5F2 layout example"
Either HSP053-4M5, HSP051-4M10 or ECMF04-4HSWM10 can be used to protect TMDS lanes against ESD.
Figure 55: HDMI2C2-5F2 electrical schematic
Figure 56: HDMI2C2-5F2 layout example
0
D AT1+
D A T2-
D A T0+
D A T1-
C LK -
C LK +
D AT0-
VD D _IC
R 4
27k
C EC
D 1
S C H O TTK Y D IO D E
5V_S Y S
R 1
10k
H PD
3V 3
E N A B LE _IC
C 1
100n
0
0
H D MI_A
C N 1
TD MS D A TA2+1
TMD S D A TA2 S H IE LD2
TD MS D A TA2-3
TD MS D ATA1+4
TMD S D A TA1 S H IE LD5
TD MS D ATA1-6
TD MS D A TA0+7
TMD S D A TA0 S H IE LD8
TD MS D A TA0-9
TMD S C LO C K +10
TMD S C LO C K SH IELD11
TMD S C LO C K -12
C E C13
U TILITY14
S C L15
SD A16
D D C /C E C G N D17
+5V18
H P D19
SH
IEL
D2
0
SH
IEL
D2
1
SH
IEL
D2
3S
HIE
LD
22
0
S C L_SY S
S D A _SY S
R 2
10k
R 3
10k
C 3
100n
0
D A T2+
U 1
H D MI2C 2-5F 2
SC
LA
1C
EC
A2
SD
A_
ICA
3S
CL
_IC
A4
SD AB 1
G N DB 2
5V
_IN
C1
HP
DC
2
EN
_IC
C3
VD
D_
ICC
4
R 5
47k
R 6
47k
D 2
SC H O TTKY D IO D ES
C 2
1u
0
S C L_IC
S D A _IC
HP
D_
IC
CEC _IC
VD
D_
IC
C5V
_IN
H D M I2C 2-5F2
D A T2+
G ND
DAT2-
D A T1+
G ND
DAT1-
D A T0+
G N D
D A T1-
C LK +
G ND
C LK -
C E C
U TILITY
S C L
S D A
G N D
+5V
HPD
RPU
_SC
L
RPU_SCL_IC
R PU_SDA_IC
R PU_ENABLEC VDD_IC
EN
AB
LE
_IC
RPU
_SD
A
RPU
_CEC
V D D _C E C
5V
_IN
A1
B1
C1
A4
C4
D CEC
AN5121 ST offer for control lines
DocID031369 Rev 1 23/27
The HDMI2C2-5F2 is fully compliant with HDMI 2.0 standard requirements.
5.3.2 Full port protection: HDMI2C2-14HD
The HDMI2C1-14HD provides ESD protection for all HDMI connector pins and provides signal conditioning for control link of HDMI sink in a single QFN36 lead package with 500 µm pitch
Figure 57: HDMI2C2-14HD package
Figure 58: HDMI2C2-14HD pinout, top view
Its high frequency bandwidth and low clamping voltage on TMDS lines ensure the compatibility with the highest resolution of HDMI standard.
Figure 59: HDMI2C2-14HD, differential attenuation Sdd 21 typical value
Figure 60: HDMI2C2-14HD, TDR on TDMS lane tr 10%-90% = 200 ps, typical value
The eye diagrams shown from Figure 61: "Eye diagram at 3.4 Gbps, without HDMI2C2-14HD" to Figure 64: "Eye diagram at 5.94 Gbps, with HDMI2C2-14HD" highlight a very low impact on signal transmission ensuring a good signal integrity.
100k 1M 10M 100M 1G 10G
-6
-5
-4
-3
-2
-1
0
f/Hz
ST offer for control lines AN5121
24/27 DocID031369 Rev 1
Figure 61: Eye diagram at 3.4 Gbps, without HDMI2C2-14HD
Figure 62: Eye diagram at 3.4 Gbps, with HDMI2C2-14HD
Figure 63: Eye diagram at 5.94 Gbps, without HDMI2C2-14HD
Figure 64: Eye diagram at 5.94 Gbps, with HDMI2C2-14HD
The active low fault pin is used to indicate a short-circuit or an overtemperature protection activation on 5V_OUT pin.
The typical electrical schematic and an example of layout are shown below, see Figure 65: "HDMI2C2-14HD electrical schematic" and Figure 66: "HDMI2C2-14HD layout example".
Figure 65: HDMI2C2-14HD electrical schematic
Figure 66: HDMI2C2-14HD layout example
The HDMI2C2-14HD is fully compliant with HDMI 2.0 standard requirements.
28.1ps/div
200mV/div
28.1ps/div
200mV/div
1
11 19
29
DAT2+
GND
DAT2-
DAT1+
GND
DAT1-
DAT0+
GND
DAT1-
CLK+
GND
CLK-
CEC
UTILITY
SCL
SDA
GND
+5V
HPD
SCL_IC
SDA_IC
CEC_IC
5V
_IN
VD
D_
IC
CEC_IC
VD
D_
CE
C_
IC
VD
D_
CE
C
HEAC+
HEAC-
EN
AB
LE
DC
EC
RP
U_
CE
C_
IC
RP
U_
SC
L
RP
U_
SD
A
C5
V_
IN
RP
U_
SC
L_
IC
RP
U_
SD
A_
IC
RP U _ C E C
CV
DD
_IC
CV
DD
_C
EC
CV
DD
_C
EC
_IC
CE S D _ D IS H
RP
U_
EN
AB
LE
HDMI2C2-14HD
AN5121 Conclusion
DocID031369 Rev 1 25/27
6 Conclusion
Consumer applications as set-top boxes fulfill EMC requirements as described in CISPR 20/EN 55020 or CISPR 24/EN 55024. In particular ESD robustness test has to be performed on HDMI port.
An HDMI port is composed of several links with different electrical characteristics introducing specific constraints on ESD protection devices.
This application note presents STMicroelectronics offering for HDMI port: standalone ESD protection for TMDS lines and ESD protection with signal conditioning for control lines or for the whole HDMI port. The high frequency bandwidth of ESD protection for TMDS line ensures a low impact of the protection device on signal integrity. The signal conditioning and the dynamic pull-up on the DDC bus help the system to drive high capacitive cables by respecting the standard requirements.
Revision history AN5121
26/27 DocID031369 Rev 1
7 Revision history Table 8: Document revision history
Date Revision Changes
04-Dec-2017 1 Initial release.
AN5121
DocID031369 Rev 1 27/27
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