Contact: [email protected]
1
High Voltage Devices on Scaled
Technologies for RF and Power
Management
Seth J. Wilk,
William Lepkowski, Trevor J. Thornton
Contact: [email protected]
2
• SJT Micropower and the SBIR program
• Silicon MESFET Overview
• High Voltage Capability
• Modeling and Measured MESFETs
• Power Management Applications
• RF Applications
Outline
Contact: [email protected]
3
Company:
• SJT Micropower is a fabless design house based in Phoenix,
AZ
• Startup out of Arizona State University
• Multiple SBIR and STTR contracts awarded in past 4 years
(~$3M)
Technology:
• Patented high voltage MESFETs which can be fabricated on
SOI CMOS with no additional cost
Status:
• Devices taped out down to 45nm
• Technology has been demonstrated at multiple foundries on
both partially and fully depleted SOI and on both SOI and SOS
• Cutoff Frequency ~40GHz on 150nm technology, suitable for
RF
SJT Micropower Overview
Contact: [email protected]
4 SBIR Funding
Small Business Innovative Research:
Each year, Federal agencies with extramural research and development
(R&D) budgets that exceed $100 million are required to allocate 2.5 percent
of their R&D budget to these programs. Currently, eleven Federal agencies
participate in the program:
Three Phase Program:
• Phase I. The objective of Phase I is to establish the technical merit,
feasibility, and commercial potential of the proposed R/R&D efforts $150,000
total costs for 6 months.
• Phase II. The objective of Phase II is to continue the R/R&D efforts initiated
in Phase I. $1,000,000 total costs for 2 years.
• Phase III. The objective of Phase III, where appropriate, is for the small
business to pursue commercialization objectives resulting from the Phase
I/II R/R&D activities. The SBIR program does not fund Phase III
http://www.sbir.gov/
Contact: [email protected]
5
The Problem
Existing Scaled Transistors
are Low Voltage <1V
5V
1.5V 9V
5V and 12V
How do you connect
these common items
to new chips?
How do you make
these common items
work with new chips? <1V
1.5V 1.5V 1.5V
The Problem with CMOS
Contact: [email protected]
6
0.000
0.010
0.020
0.030
0.040
0.050
0 5 10 15
Dra
in C
urr
ent
(A)
Drain Voltage (V)
Vg = -0.75 to 0.75V
in 0.25V Steps
High Voltage on Low Voltage CMOS
Device fabricated on a 45nm process where CMOS limited to ~1V drain voltage
No changes required to the CMOS Process Flow
Main Technology and Talk Focus
Contact: [email protected]
7 ASU/SJT Micropower Si-MESFET Milestones
• Successful at 5 different foundries & 6 CMOS processes
(45nm – 800nm) without changing any of the process flow
• IBM, Honeywell, Peregrine, SPAWAR, MIT Lincoln Labs
• Highest breakdown 55 V (350nm PD-SOI CMOS)
• Peak fT ~ 45 GHz (150nm PD-SOI CMOS)
• Peak fmax > 55 GHz (45nm PD-SOI CMOS)
• Have developed calibrated TOM3 and VerilogA models
• MESFETs based circuits that we have designed and tested:
• LNA, LDO, Buck Regulator, PA, Polar Modulated PA,
opamp, and voltage reference
Contact: [email protected]
8
Helps combat obsolescence Easy to Implement with
existing SOI CMOS
Extreme Environment Simpler RF PA
Development
• No additional cost to use
technology
• Existing CMOS already has
steps required to fabricate
device
• Use existing, older technology
high voltage parts with modern
low voltage digital CMOS
• Use Existing 5V supply rails
• Conversion of voltages on chip
• High Temperature
• Radiation Hardened,
Schottky interface is less
susceptible to radiation
induced damage than
MOSFET metal-oxide-
semiconductor interface
• Larger voltage swing
allows higher power and
easier, more efficient
matching to 50Ω
Technology Benefits
Contact: [email protected]
9
• SJT Micropower and the SBIR program
• Silicon MESFET Overview
• High Voltage Capability
• Modeling and Measured MESFETs
• Power Management Applications
• RF Applications
Outline
Contact: [email protected]
10 What is a MESFET
MESFET: Metal Semiconductor Field Effect Transistor
More common to have SiC or GaAs but a MESFET can be Silicon as well
Contact: [email protected]
11 Si-MESFET Structure and Background
• Majority carrier device—does not suffer from floating body effects
• Schottky gate created by a silicided contact on lightly doped n-well
• Controlled by vertically depleting the channel
• Depletion Mode—Vt is usually in the range of -0.5V to -1V
• Gate Length (Lg) is limited by the separation of the oxide spacers
– Typically contact the gate outside of LaS & LaD to shorten Lg
• Can size LaS and LaD to give optimal RF performance and breakdown
Top View
LaS
LaD Lg
Gate
Contact
Cross-Sectional View
Contact: [email protected]
12
a) Fabrication steps are the same through
the LOCOS step
b) MOS gate is defined
c) SB used to pattern the oxide spacers of a
MOSFET is used to define the gate
length of the MESFET
d) Source/drain implant step is same for the
MOSFET & MESFET.
e) CoSi2 salicide used to form the low-
resistance contacts is used to form a
Schottky contact over the lightly doped
channel
***Back-end processing steps same as
SOI/SOS CMOS
Fabrication: n-MOSFETs vs.n-MESFETs
Contact: [email protected]
13
VGS = 0 V & VDS = 0 V
Linear Region:
VGS = 0 V & small VDS
Pinch-off:
VGS = 0 V & VDS =
VDSAT
Saturation Region:
VGS = 0 V & VDS > VDSAT
Subthreshold Region:
VGS < Vt & VDS = 0 V
Regions of Operation
*Note: Due to the relatively
thin buried oxide layer, a
depletion region controlled
by VBS will form at the
bottom interface
Cross-Section MESFETs
Contact: [email protected]
14
MOSFET MESFET MESFET Advantages
Threshold
Voltage, Vth
Enhancement mode
(normally-off) e.g. Vth = +0.6V for
N-MOSFET
Depletion mode
(normally-on) e.g. Vth = -0.5V for
N-MESFET
The availability of depletion
mode devices alongside
traditional enhancement mode
devices allows for greater
flexibility in circuit design
Conduction
Type
Minority carrier,
inversion channel
Majority carrier,
depletion channel
MESFET does not suffer from
floating body effects such as the
kink effect. It does not require
the body-tie contacts often used
as part of SOI CMOS.
Self-aligned Yes No The extended drift region from
the gate to the drain (LaD) gives
the MESFET a high breakdown
voltage.
Gate Material Metal-Oxide-Semi Metal Silicide The Schottky gate of the
MESFET can support
significant current flow. It is
tolerant of high voltage
excursions, radiation and wide
temperature variations
Major Differences between SOI MOSFETs and MESFETs
Contact: [email protected]
15
LaS=LaD=200nm
gives highest
current drive
LaS=LaD=1000nm
allows for higher
voltage drive (>20V)
but
Family of Curves
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0 5 10 15 20
IBM MESFET Family of Curves
Id (
A/m
m)
Vd (V)
Lg=200nm
Lad=Las=1000nm
Lg=200nm
Lad=Las=200nm
Vg = -0.5 to 0.5 in 0.25V steps
Note that the red line
shows an approximate
breakdown voltage of a
MOSFET
Contact: [email protected]
16
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
-1.5 -1 -0.5 0 0.5 1
Lg = 200nm LaS = 200nm LaD = 200nm
Cu
rre
nt
(A/m
m)
Gate Voltage (V)
Vd = 2V
Drain
current
MAG(IG)
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
-1.5 -1 -0.5 0 0.5 1
Lg = 200nm LaS = 1000nm LaD = 1000nm
Cu
rre
nt
(A/m
m)
Gate Voltage (V)
Vd = 2V
Drain
current
MAG(IG)
The threshold voltage is relatively independent of LaS and LaD
Vth close to -0.5V for both LaS=LaD=200nm and LaS=LaD=1000nm
Turn-on Characteristics / Gummel Curves
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
-1.5 -1 -0.5 0 0.5 1
Lg = 200nm LaS = 1000nm LaD = 1000nm
Cu
rre
nt
(A/m
m)
Gate Voltage (V)
Vd = 10V
Contact: [email protected]
17
-0.8 -0.7 -0.6 -0.5 -0.4
Threshold Voltage (V)
0
1
2
3
4
5
6
7
Fre
quen
cy
Mean = -0.6287
Std. Dev. = 0.03538
N = 31
-0.8 -0.7 -0.6 -0.5 -0.4
Threshold Voltage (V)
0
1
2
3
4
5
6
7
Fre
quen
cy
Mean = -0.6353
Std. Dev. = 0.03701
N = 15
-0.8 -0.7 -0.6 -0.5 -0.4
Threshold Voltage (V)
0
1
2
3
4
5
6
7
Fre
quen
cy
Mean = -0.6225
Std. Dev. = 0.03376
N = 16
Statistical Analysis
The threshold voltage distributions for (a) Run 1 (b) Run 2. The
distribution across all 31 devices is shown in (c). We are currently
adding to these statistics.
a) b) c)
MESFETs structures have been fabricated on multiple foundry runs. Key
parameters such as Vt (shown here) have been measured across the
different runs on multiple die.
Mean = -0.635
Std. Dev = 0.037
N=15
Mean = -0.623
Std. Dev = 0.034
N=16
Mean = -0.629
Std. Dev = 0.035
N=31
Contact: [email protected]
18
5
10
15
20
25
30
35
40
45
0 1000 2000 3000 4000 5000
Trend
Las=200nm
Las=300nm
Las=500nm
Las=2000nmSoft
Bre
akd
ow
n V
oltage
(V
)
Drain Access Length, LaD (nm)
• The (soft) breakdown voltage appears to be proportional
to LaD/ln(LaD) which suggests avalanche breakdown
Soft Breakdown Characteristics – 45nm Technology
Breakdown remained the same
before and after stress testing
• Largest LaD fabricated was 2µm
• Predicting VBD > 40V for
LaD=5µm
• Longer LaD recently fabricated
Contact: [email protected]
19 Ft of MESFETs at different Nodes
2
4
6
810
30
50
0.1 1.0
Peak C
ut-
off F
requency, f T
(G
Hz)
Gate Length (m)
20
2.00.2 0.3 0.4 0.6
350 nm SOI CMOS Process
LaS
= LaD
= 1 m
150 nm SOI CMOS ProcessL
aS =L
aD = 300 nm
Contact: [email protected]
20
• MESFET measured had Lg=200nm and LaS=LaD=2000nm
• Stress Conditions: 160ºC at a fixed bias of Vd=10V, Vg=0.5V for 168 hours.
• Small increase in drain current and marginal shift in Vt was observed after stress
but otherwise there were few changes in the MESFET’s operation.
• Off-state breakdown voltage remained at ~25V after the stress test.
Accelerated Lifetime Test
10-11
10-9
10-7
10-5
10-3
10-1
-1.5 -1 -0.5 0 0.5 1
Gate Voltage (V)
After StressBefore Stress
Cu
rren
t (A
)
Drain Current
MAG (IG)
0
2
4
6
8
10
0 5 10 15 20
Drain Voltage (V)
Vgs
= -0.5 to + 0.5V in 0.25V steps
After StressBefore Stress
Dra
in C
urr
ent
(mA
)
Vd=2V
Contact: [email protected]
21
• SJT Micropower and the SBIR program
• Silicon MESFET Overview
• High Voltage Capability
• Modeling and Measured MESFETs
• Power Management Applications
• RF Applications
Outline
Contact: [email protected]
22
• Square-law model [IDS α(VGS-Vth)2] in saturation.
• Exponential characteristics [IDS α exp (VGS-Vth)]
in sub-threshold.
• Well-defined extraction procedure.
• Correlated to analytical models to ease the
development of higher level models.
• Sub-circuits for leakage effects, breakdown
voltage and short-channel effects.
• Charge-based capacitance model.
SPICE Model
Contact: [email protected]
23 TOM3 Model
)1( dsk
Q
Gds VfVI MESFET modeling consists of :
• DC Measurements
• S-parameter measurements of GSG
devices at different bias conditions
• Pad de-embedding
• Extrinsic parameters extraction using
a ColdFET method
• VDS=0 and gate is turned on
very hard
• Intrinsic parameter extraction based
on DC and S-parameters
measurements
dsk Vf tanh
Availability of Model in Cadence and ADS Important
Contact: [email protected]
24 Turn-on Characteristics
-50
0
50
100
150
-1 -0.5 0 0.5
gm
(m
S/m
m)
Gate Voltage (V)
Vd=4V
Vd=2V
Vd=0.5V
Vd=0.1V
Black = Measured
Red = Simulation
0
0.5
1
1.5
0 1 2 3 4
f K
Drain Voltage (V)
Vg=0.5V
10-10
10-8
10-6
10-4
10-2
-1 -0.5 0 0.5
Dra
in C
urr
ent (A
)
Gate Voltage (V)
Vd=4V
Vd=0.1V
TOM3 Model shows a good fit across different drain and gate bias
conditions
S. J. Wilk et al., "Characterization and modeling of enhanced voltage RF
MESFETs on 45nm CMOS for RF applications," IEEE Radio Frequency
Integrated Circuits Symposium (RFIC), 2012, pp.413-416, 17-19 June 2012
Contact: [email protected]
25
0.000
0.020
0.040
0.060
0.080
0.100
0.00 1.00 2.00 3.00 4.00
Dra
in C
urr
ent
(A)
Drain Voltage (V)
Vg = -0.5 to 0.5 in 0.25V Steps
Family of Curves
Black = Measured
Red = Simulation
S. J. Wilk et al., "Characterization and modeling of enhanced voltage RF
MESFETs on 45nm CMOS for RF applications," IEEE Radio Frequency
Integrated Circuits Symposium (RFIC), 2012, pp.413-416, 17-19 June 2012
Contact: [email protected]
26
• LaS=LaD=200nm gives higher
fT and fmax,
• LaS=LaD=1000nm allows for
higher drain bias
0
5
10
15
20
25
30
35
0.1 1 10 100
Fre
qu
en
cy (
GH
z)
Drain Current (A/mm)
LaS=LaD=200nm
VD=3V
LaS=LaD=1000nm
VD = 10V
solid symbols = fmax
open symbols = fT
RF Characteristics
(mA/mm)
2
4
6
810
30
50
0.1 1.0
Peak C
ut-
off F
requency, f T
(G
Hz)
Gate Length (m)
20
2.00.2 0.3 0.4 0.6
350 nm SOI CMOS Process
LaS
= LaD
= 1 m
150 nm SOI CMOS ProcessL
aS =L
aD = 300 nm
Contact: [email protected]
27
• All MESFETs measured thus far have more than 15 dB gain below 2.5GHz
• Can improve fmax by optimizing LaS
• LaS can be equated to source degeneration of an amplifier
Maximum Available Gain of MESFETs on 45nm Process
0
5
10
15
20
25
30
35
40
108
109
1010
1011
LaS=LaD=200nmLaS=LaD=500nmLaS=LaD=2000nmLaS=LaD=1000nm
Max
imu
m A
va
ilab
le G
ain
(M
AG
) (d
B)
Frequency (Hz)
Contact: [email protected]
28
-50
-40
-30
-20
-10
0
0.0 10 20 30 40
S11
and S
12
(dB
)
Frequency (GHz)
S11
S12
-10
-5
0
5
10
15
0.0 10 20 30 40
S22
and S
21 (
dB
)
Frequency (GHz)
S21
S22
0.0
10
20
30
40
50
108
109
1010
1011
H21 a
nd M
AG
(d
B)
Frequency (GHz)
H21
MAG
S Parameter Measurements and Model
Vd=2V and Vg=0.25V
)1( TQTQQ GHGLGG
)exp( dsdsGGB VIQT
Model the Gate Charge
Where
QGL is the low power region
And
QGH is the highpower region
T describes the transition
between regions
Black = Measured
Red = Simulation
GG
TC
gmf
2
Cut-off Frequency
Contact: [email protected]
29
• SJT Micropower and the SBIR program
• Silicon MESFET Overview
• High Voltage Capability
• Modeling and Measured MESFETs
• Power Management Applications
• RF Applications
Outline
Contact: [email protected]
30 Power Management
Buck Converter Linear Regulator Buck Converter
and Low Dropout
Linear Regulator
linear regulator is a
circuit used to maintain a
steady output voltage
Pros:
Steady Output Voltage
High PSRR
Cons:
Inefficient as input
voltage becomes much
higher than output
voltage because
transistor must dissipate
the difference
A buck converter is a step-
down DC to DC converter
Pros:
Efficient for larger voltage
steps
Cons:
High ripple and noise can
be too much for system
requirements
Efficient for larger
voltage steps and
can maintain output
voltage
Want low dropout
regulator so that the
buck output can be
close to the desired
output voltage for
best efficiency
Contact: [email protected]
31 Why Low Dropout?
The less overhead your power management needs, the longer the device
can work on a single battery charge
Contact: [email protected]
32
SJT Solution Pinpoint Load Placement
MICRO-
PROCESSOR
(ARM, 8-bit
Microcontroller,
etc)
LDO
VoutVin
Cout
MICRO-
PROCESSOR
(ARM, 8-bit
Microcontroller,
etc)
VinSJT
LDO
MICRO-
PROCESSOR
(ARM, 8-bit
Microcontroller,
etc)
SJT
LDO
SJT
LDO
SJT
LDO
Vin
Integrating Power Management - Processors
Ideally, integrate
power management
because designers are
pin constrained
How to connect the
supply to the
integrated circuit if the
on chip transistors are
low voltage?
Pin constrained if you
need a specific
capacitor at the output
Contact: [email protected]
33
ZL
VOUT
VIN
MP
G
+
-VREF
PMOS Voltage Regulator
Common Source
Error
Amplifier
AV
IL
S
D
ZL
VOUT
VIN
VREFMN
G+
-
NMOS Voltage Regulator
Source Follower
Error
Amplifier
AV
IL
D
S
Common Linear Regulator Topologies
Zener Diode
Contact: [email protected]
34 PMOS LDO Implementation
Advantages
• Common source (CS) configuration allows
error amp to drive gate of PMOS below Vout
• Can achieve very low dropout voltages
– VDO = Ron* Iload = VDSAT
• Note: Ideal dropout—does not
include the parasitic voltage drop
from metal lines
Disadvantages
• Stability concerns arise from CS
configuration
– High Rout at Vout node
– Need load cap with its associated ESR
• PMOS has 2-3x lower mobility than NMOS
– Need 2-3x larger pass device to
achieve a given current drive
Contact: [email protected]
35
)(2
11
ESRoutload
PRRC
f
11
22
1
Opar
PRC
f
ESRload
ZRC
f2
11
22
32
1
Opar
PRC
f
211 // IOpar CCC
PMOSOpar CCC //22
PMOS LDO Implementation (Cont)
)(11)( //)//( pmosoloadpmosoout rRRRrR
Common source (CS)
Contact: [email protected]
36 NMOS (Enhancement Mode) LDO Implementation
Advantages
• Source follower configuration
– Rout ~ 1/gm
• Significantly improves stability
• NMOS device has higher current drive
than PMOS
• Smaller input capacitance since smaller
device is needed for given current drive
– Improved transient response
Disadvantages
• Without charge pump (CP), gate must be
driven to overcome Vt
– Dropout is dependent on Vt
• VDO = Vt + VDSAT
• Including CP negates dependence of Vt
but increases die size and noise
or
Contact: [email protected]
37
Vin
+
_
Vout
RL
R1
R2
RO1 CO1 CI2 RO2 CO2CNMOS
OTA Buffer
BGR1/gm(NMOS)
11
12
1
Opar
PRC
f
22
22
1
Opar
PRC
f
211 // IOpar CCC
NMOSOpar CCC //22
NMOS (Enhancement Mode) LDO Implementation
Source
follower
configuration
Contact: [email protected]
38
ZL
VOUT
VIN
VREFMN
G+
-
NMOS Voltage Regulator
Source Follower
Error
Amplifier
AV
IL
D
S
MESFET LDO
Advantages
• Combines attributes of NMOS and PMOS LDOs
• Depletion mode operation allows pass transistor to be orientated in source
follower configuration without a charge pump
• Closed loop frequency response is similar to NMOS LDO
Disadvantages
• Depletion mode means MESFET will conduct under most bias conditions
• Gate leakage of MESFET
MESFE T Regulator
Source Follower Configuration
Contact: [email protected]
39 MESFET LDO (Cont)
121
1)(2
1
OICO
PRCCC
f
22
2)(2
1
OMESO
PRCC
f
Simulated Gain/Phase
• Can be treated as single pole system if:
• P1 is appropriately placed
• Output capacitance is not large
-20
0
20
40
60
80
Gain
(d
B)
10mA
1A
-120
-100
-80
-60
-40
-20
0
101
102
103
104
105
106
107
Pha
se (
o)
Frequency (Hz)
27oC
Vout = 1.5VVin = 2V
10mA
1A
Contact: [email protected]
40
• Design includes a high current drive MESFET integrated with a CMOS error
amplifier
• MESFET width of 152.2 mm with gate length of 200nm and LaD=LaS=200nm
• Die size of ~ 0.5mm x 1mm
• Regulator area is 0.245 mm2 without the bond pads
CMOS error amplifier
CAD Layout Die Photograph
IBM MESFET Linear Regulator
Contact: [email protected]
41
Summary of Measurements
• High current drive > 3A
• Low on resistance, Ron < 10 mW·mm2
• Low dropout voltage VDO< 170mV for a 1A load
• Low quiescent current, IQ < 75 A
N-MESFET
Pass Device
R1
RL
R2
Vout
Vin
Vref
Vbp1
Vbp2
Vbn2
Vbn1
Cc
Folded Cascode Buffer Stage
SFBExternal feedback
resistors R1 and R2
chosen to give
Vout =1.5V
off-chip components
MESFET Linear Regulator
Contact: [email protected]
42
Line Regulation
MESFET Linear Regulator (cont.)
W. Lepkowski, et al., "An integrated MESFET voltage follower LDO for high power and PSR RF
and analog applications," Custom Integrated Circuits Conference (CICC), 2012 IEEE , vol., no.,
pp.1-4, 9-12 Sept. 2012
1.5
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.5 1.6 1.7 1.8 1.9 2 2.1
LDO Vin-Vout at 1.8V output voltage
10mA100mA250mA500mA
Outp
ut V
oltage (
V)
Vin (V)
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
0.8 1 1.2 1.4 1.6 1.8 2 2.2
LDO Vin-Vout at 1.2V output voltage
10mA100mA250mA500mA
Outp
ut
Voltage (
V)
Vin (V)
Contact: [email protected]
43 MESFET Linear Regulator (cont.)
0
25
50
75
100
0 200 400 600 800 1000
Gro
und C
urr
ent
(A
)
Load Current (mA)
27oC
Vout = 1.5V
Vin = 2V
Vin = 1.8V
Quiescent current
W. Lepkowski, et al., "An integrated MESFET voltage follower LDO for high power and PSR RF
and analog applications," Custom Integrated Circuits Conference (CICC), 2012 IEEE , vol., no.,
pp.1-4, 9-12 Sept. 2012
Contact: [email protected]
44 MESFET LDO: Transient Line Regulation
1.4
1.5
1.6
1.7
1.8
1.2
1.4
1.6
1.8
2
0 5 10 15 20
Ou
tput
Vo
ltag
e (
V) In
put V
olta
ge
(V)
Time (s)
27oC
Iout = 75mAtr = t
f = 100ns
• Vout settles in ~2µs w/ single overshoot and undershoot
• Suggests high level of phase margin
• No output cap other than 12pF parasitic cap from scope probe
W. Lepkowski, et al., "An integrated MESFET voltage follower LDO for high power and PSR RF
and analog applications," Custom Integrated Circuits Conference (CICC), 2012 IEEE , vol., no.,
pp.1-4, 9-12 Sept. 2012
Contact: [email protected]
45 MESFET LDO: PSR
• PSR measurement includes integrated BGR
• > 40dB performance at 80mA load.
• Expect PSR to be higher at increased load currents due to higher simulated
open loop gain
10
15
20
25
30
35
40
45
102
103
104
105
PS
R (
dB
)
Frequency (Hz)
27oC
Iout = 80mAVout = 1.2V
W. Lepkowski, et al., "An integrated MESFET voltage follower LDO for high power and PSR RF
and analog applications," Custom Integrated Circuits Conference (CICC), 2012 IEEE , vol., no.,
pp.1-4, 9-12 Sept. 2012
Contact: [email protected]
46
• SJT Micropower and the SBIR program
• Silicon MESFET Overview
• High Voltage Capability
• Modeling and Measured MESFETs
• Power Applications
• RF Applications
Outline
Contact: [email protected]
47
47
0.1
Max Output
Power (Watt)
Frequency
(GHz)1 10 100
10
1000
100
1
0.1
GaAs HBT, HEM
T
GaN HEM
T
SiCSi LDM
OS
InP HBTCMOS
10
100
1000
0.1
1
10
0.01 0.1 1
fT VDD
Cu
t-o
ff F
req
uen
cy,
f T (G
Hz) S
up
ply
Vo
ltag
e, V
DD, (V
olts
)
Gate Length (m)
Standard CMOS scaling trend
(Data collected from different sources)
CMOS technology is drawing more
attention for handset applications:
Low cost solutions
High integration with digital circuits
Single chip transceiver solutions
Easy to redesign after technology scaling
Good modeling of silicon based components
But …It has power limitations
PA Integration
Contact: [email protected]
48
2 4 6 8 10 12 14 16 180 20
-0
100
200
300
400
500
-100
600
Drain Voltage (V)
Dra
in C
urre
nt (
A)
Simple Class A Amplifier Design
• Pout Class A = ½*idc*Vdc = ½* 0.2A*10V= 1W, Rload = Vdc/idc = 50Ω
• Note that if Vd of the transistor goes down, current must go up and Rload goes down
• For 1W if Vdc = 1V, idc = 2A and Rload = 0.5 Ω
Drain Voltage (V)
Dra
in C
urr
en
t (m
A)
Contact: [email protected]
49 PA Efficiency Reduced by Large Impedance Transformations
Class-A amplifier
• CMOS PAs may need to use
large transformation ratios,
r = RL/ROUT > 10
• A MESFET PA with Pout > 1W can
be designed to have ROUT ~ 50 W
1 Watt output
power from a
single silicon die
20
30
40
50
60
70
80
90
100
1 10 100
Q=5Q=10Q=15Q=20
Ma
tch
ing
Netw
ork
Eff
icie
nc
y (
%)
Transformation Ratio (r)
RL = 50Ω
VDD
RF+DCbias
ROUT
Contact: [email protected]
50
There are several techniques to overcome VBD issue in CMOS
technology:
• Cascode architecture (less than ~2 times improvement)
• Thick oxide transistors (~factor of 2 improvement)
• Parallel amplification ( lowers the PAE)
• High voltage devices such as BiCMOS ( cost, not always
available on digital processes )
Proposed SOI-MESFET
• ~2-to-10 times improvement in VBD
• No additional cost
• Available on any SOI digital process
• High enough cut-off frequency for PA design at f0<5GHz
Overcoming Low Voltage Design Constraints
Contact: [email protected]
51
• There is a tradeoff between VBD and fT
– Optimum device geometries found to be
• LaD=LaS=500nm, LaS=200nm =>> fT=24GHz, VBD=15V
• LaD=LaS=2000nm, Lg=200nm =>> fT=9GHz, VBD=28V
Parameter
LAS=LAD=
500NM
LaS=LaD=
1000nm LaS=LaD=
2000nm
Gate oxide No Gate
Oxide
No Gate
Oxide
No Gate
Oxide
LG (nm) 200 200 200
Lext/LSpacer (nm) 500 1000 2000
Wfinger (µm) 15 15 15
VBD (V) 15 21 28
fT (GHz) 24 17.5 9
fMAX (GHz) 35 25 20
VT (V) -0.5 -0.5 -0.5
MESFET Breakdown Voltage and Cutoff Frequency
Contact: [email protected]
53 MESFET 433MHz PA Demonstration – Cont.
• Gain of 16.8dB
• Peak Pout of 17dBm with PAE
of 42.5%
0
5
10
15
20
0
10
20
30
40
50
60
-10 -5 0 5 10
Pou
t (d
Bm
), G
ain
(dB
)E
fficie
ncy (%
)
Pin (dBm)
PAE
DEGAIN
POUT
• Peak PAE 46% at Pout of 15.9dBm
Black = Measured
Red = Simulation
Contact: [email protected]
54
DC
Drain
Bias
Microstrip (Width/Length)
Z1 = (0.11", 1.50")
Z2 = (0.11", 0.20")
Z3 = (0.11", 0.42")
Z4 = (0.05", 1.68")
Z5 = (0.11", 1.00")
Packaged
MESFET
Lambda / 4
Bias Line
6.8 pF RF
OUT100 pF
L Match
Z1 Z2
Z3
Z4
Z5
1 uF
3.9 pF
51 nH 4.7 pF
10 uF
MESFET 900MHz PA Demonstration
S. J. Wilk, W. Lepkowski and T. J. Thornton, “32 dBm Power Amplifier on 45 nm SOI CMOS,” IEEE Microwave
and Wireless Components Letters, Accepted for publication Jan 2013.
Contact: [email protected]
55
-40
-20
0
20
40
10
30
50
70
90
-5 0 5 10 15 20 25
Pout
Gain
IM3
PAE
DE
Pou
t, I
M3
(dB
m),
Ga
in (
dB
)
PA
E (%
)
Pin (dBm)
0
5
10
15
20
25
30
35
40
45
0
10
20
30
40
50
60
70
80
90
2 3 4 5 6 7 8 9
Pout
Gain
OIP3
PAE
DE
Pou
t a
nd O
IP3 (
dB
m),
Ga
in (
dB
)
PA
E (%
), DE
(%)
Drain Voltage (V)
MESFET 900MHz PA Demonstration – 1.5W
• Gain of 11.1dB
• Peak Pout of 32dBm
• Peak PAE 37.6%
• OIP3 of 39.3dBm
S. J. Wilk, W. Lepkowski and T. J. Thornton, “32 dBm Power Amplifier on 45 nm SOI CMOS,” IEEE Microwave
and Wireless Components Letters, Accepted for publication Jan 2013.
Contact: [email protected]
56 Ongoing Research and Development Efforts
• Higher Frequency PA Measurements – Working on >2GHz
and 1W PA designs along with Polar Modulation
• Development of integrated low dropout linear regulators for
defense applications (supported by NASA and DARPA Phase
2 SBIR projects)
• Continued development of MESFETs on 45nm and 32nm
process nodes
• Continued statistical analysis of MESFET devices and model
development.
Contact: [email protected]
57 References
S. J. Wilk, W. Lepkowski and T. J. Thornton, “32 dBm Power Amplifier on 45 nm SOI CMOS,” IEEE Microwave
and Wireless Components Letters, Accepted for publication Jan 2013.
M.R.Ghajar, S. J. Wilk, W. Lepkowski, B. Bakkaloglu and T. J. Thornton “Backgate Modulation Technique for
Higher Efficiency Envelope Tracking” IEEE Transactions on Microwave Theory and Techniques, accepted for
publication Jan 2013.
W. Lepkowski, S. J. Wilk, M.R.Ghajar, T. J. Thornton, "High Voltage SOI MESFETs at the 45nm Technology
Node," IEEE International SOI Conference, 2012 , October 2012
W. Lepkowski, Wilk, S.J. Ghajar, M.R.; Bakkaloglu, B., Thornton, T.J. , "An integrated MESFET voltage follower
LDO for high power and PSR RF and analog applications," Custom Integrated Circuits Conference (CICC), 2012
IEEE , vol., no., pp.1-4, 9-12 Sept. 2012
S. J. Wilk et al., "Characterization and modeling of enhanced voltage RF MESFETs on 45nm CMOS for RF
applications," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2012, pp.413-416, 17-19 June 2012.
Lepkowski, W., Ghajar, M.R., Wilk, S.J., Summers, N., Thornton, T.J., Fechner, P.S., , "Scaling SOI MESFETs to
150-nm CMOS Technologies," Electron Devices, IEEE Transactions on , vol.58, no.6, pp.1628-1634, June 2011
Lepkowski, W., Goryll, M., Wilk, S.J., Zhang, Y., Sochacki, J., Thornton, T.J., , "SOI MESFETs for extreme
environment buck regulators," SOI Conference (SOI), 2011 IEEE International , vol., no., pp.1-2, 3-6 Oct. 2011
J. Ervin, A. Balijepalli, P.J. Joshi, V. Kushner, J. Yang, T.J. Thornton, "CMOS-Compatible SOI MESFETs with High
Breakdown Voltage," IEEE Trans. Elec. Dev., vol. 53, p. 3129, 2006.
Contact: [email protected]
58
Contact Information:
Seth Wilk
Phone: 602-703-3730
http://sjtmicropower.com/
QUESTIONS?