hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 11
Memory & IO Interfacing to CPU
Lec note 3
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 22
outline
Z80 Minimal Configuration Z80 Memory connection Address Bit Map Memory Map Full and Partial Decoding 1 Bit Memory With Separated I/O Z80 Input Output Simplified Drawing of 8088 Minimum Mode 8088 Memory connection
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 33
Minimal Configuration of a Z80 Microcomputer
MemoryClock Power
InputZ - 80 CPU
Supply
Output(I/O)
(ROM, RAM)Generator
Address Bus
Data Bus
Control Bus
Out
In
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 44
Z80 Memory connection
CPU 16 bit address bus 64 k memory(max)
CPU 8 bit data bus 8 bit data widthGenerally should be connected
Data to dataAddress to addressWr to wrRd to rdMreq to cs
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 55
Memory connection (cont.)
WR
RD
RD WR
RAM64 kb
CSZ80 CPU
D7~D0D7~D0
A15~A0A15~A0
MREQ
If only one RAM chip Full size (64 kb capacity)
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 66
Memory connection (cont.)
WR
RD
RD WR
RAM32 kb
CSZ80 CPU
D7~D0D7~D0
A14~A0A14~A0
MREQA15
If RAM capacity was 32 kb A15 composed with MREQ RAM area is from 0000h to 7FFFh
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 77
Memory connection (cont.)
There is two 32 kb RAMProblem: Bus Conflict. The two memory chips
will provide data at the same time when microprocessor performs a memory read.
Solution: Use address line A15 as an “arbiter”. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 88
Memory connection (cont.)
WR
RD
RD WR
RAM32 kb
CSZ80 CPU
D7~D0D7~D0
A14~A0A14~A0
MREQ
RAM32 kb
D7~D0
A14~A0
RD WR CS
A15
There is two 32 kb RAM A15 applied to select one RAM chip Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh (RAM1)
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 99
Memory connection (cont.)
WR
RD
OE
ROM32 kb
CSZ80 CPU
D7~D0D7~D0
A14~A0A14~A0
MREQ
RAM32 kb
D7~D0
A14~A0
RD WR CS
A15
32 kb ROM and 32 kb RAM ROM doesn’t have wr signal
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1010
Memory connection (cont.)
Z80 CPU
WR
RD
MREQ
OE
ROM16 kb
CS
D7~D0D7~D0
A13~A0A13~A0
RAM16 kb
D7~D0
A13~A0
RD WR CS
A15
RAM16 kb
RD WR CS
D7~D0
A13~A0
RAM16 kb
RD WR CS
D7~D0
A13~A0
A14 En
S0S1
There is 4 memory chipA14 and A15 applied to chip selection
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1111
Address Bit Map
A15 to A0
(HEX)
AA AA
11 11
54 32
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0000h
3FFFh
00 00
00 11
0000
1111
0000
1111
0000
1111ROM
4000h
7FFFh
01 00
01 11
0000
1111
0000
1111
0000
1111RAM
1
8000h
BFFFh
10 00
10 11
0000
1111
0000
1111
0000
1111RAM2
C000h
FFFFh
11 00
11 11
0000
1111
0000
1111
0000
1111RAM3
Selects location within chipsSelects chip
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1212
Memory Map Represents the memory type
Address area of each memory chip
Empty area
0000h
3FFFh
ROM16k
4000h
7FFFh
RAM1
16k
8000h
BFFFh
RAM2
16k
C000h
FFFFh
RAM3
16k
WR
RD
MREQ
OE
ROM16 kb
CS
D7~D0D7~D0
A13~A0A13~A0
RAM16 kb
D7~D0
A13~A0
RD WR CS
A15
RAM16 kb
RD WR CS
D7~D0
A13~A0
RAM16 kb
RD WR CS
D7~D0
A13~A0
A14 En
S0
S1
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1313
Memory Map Empty Area cann’t write and read
Read op. returns FFh value (usualy)
Write op. cann’t store any value on it
0000h
3FFFh
ROM
4000h
7FFFh
Empty
8000h
BFFFh
RAM2
C000h
FFFFh
RAM3
WR
RD
MREQ
OE
ROM16 kb
CS
D7~D0D7~D0
A13~A0A13~A0
A15
RAM16 kb
RD WR CS
D7~D0
A13~A0
RAM16 kb
RD WR CS
D7~D0
A13~A0
A14 En
S0
S1
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1414
Memory Map Empty Area cann’t write and read
Read op. returns FFh value (usualy)
Write op. cann’t store any value on it
0000h
3FFFh
ROM
4000h
7FFFh
Empty
8000h
BFFFh
RAM
C000h
FFFFh
Empty
WR
RD
MREQ
OE
ROM16 kb
CS
D7~D0D7~D0
A13~A0A13~A0
A15
RAM16 kb
RD WR CS
D7~D0
A13~A0
A14 En
S0
S1
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1515
Full and Partial Decoding
Full (exhaust) Decoding All of the address lines are connected to any
memory/device to perform selection Absolute address : any memory location has one
address
Partial Decoding When some of the address lines are connected the
memory/device to perform selection Using this type of decoding results into roll-over
addresses (fold back or shading). roll-over address : any memory location has more than
one address
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1616
Partial Decoding A15~A12 has no connection Then doesn’t play any role in addressing What is the Memory and Address Bit map?
WR
RD
RD WR
RAM4 kb
CS
Z80 CPU
D7~D0D7~D0
A11~A0A11~A0
MREQ
XA15~A12
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1717
Partial Decoding
A15 to A0
(HEX)
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
X000h
XFFFh
xxxx
xxxx
0000
1111
0000
1111
0000
1111RAM WR
RD
RD WR
RAM4 kb
CS
Z80 CPU
D7~D0D7~D0
A11~A0A11~A0
MREQ
XA15~A12
0000h
0FFFhRAM
1000h
1FFFhRAM’
2000h
2FFFhRAM’
3000h
3FFFhRAM’
F000h
FFFFhRAM’
Every memory location has more than one address For example first RAM location has addresses:
0000h1000h2000h3000h ……………. …………….
F000h
Roll-over Address
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1818
Partial Decoding A12 only connected to RAM A13 has no connection What is the memory map?
WR
RD
OE
ROM4 kb
CS
Z80 CPU
D7~D0D7~D0
A11~A0A12~A0
MREQ
RAM8 kb
D7~D0
A12~A0
RD WR CS
A14
A15
XA13
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 1919
Partial Decoding
8 roll-over address for ROM 4 roll-over address for RAM
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0xxx
0xxx
0000
1111
0000
1111
0000
1111ROM
X0x0
X0x1
0000
1111
0000
1111
0000
1111RAM
WR
RD
OE
ROM4 kb
CSZ80 CPU
D7~D0D7~D0
A11~A0A12~A0
MREQ
RAM8 kb
D7~D0
A12~A0
RD WR CS
A14
A15
XA13
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2020
Partial Decoding
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0xxx
0xxx
0000
1111
0000
1111
0000
1111
4k
ROM
X0x0
X0x1
0000
1111
0000
1111
0000
1111
8k
RAM
0000h
1FFFh
RAM’
0000h
0FFFhROM
1000h
1FFFhROM’
2000h
3FFFh
RAM’
2000h
2FFFhROM’
3000h
3FFFhROM’
4000h
5FFFh
4000h
4FFFhROM’
5000h
5FFFhROM’
6000h
7FFFh
6000h
6FFFhROM’
7000h7FFFh
ROM’
8000h
9FFFh
RAM
F000h
FFFFh
A000h
BFFFh
RAM’
C000h
DFFFh
E000h
FFFFh
WR
RD
OE
ROM4 kb
CSZ80 CPU
D7~D0D7~D0
A11~A0A12~A0
MREQ
RAM8 kb
D7~D0
A12~A0
RD WR CS
A14
A15
XA13
Conflict
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2121
Partial Decoding
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0xxx
0xxx
0000
1111
0000
1111
0000
1111
4k
ROM
X1x0
X1x1
0000
1111
0000
1111
0000
1111
8k
RAM
0000h
1FFFh
0000h
0FFFhROM
1000h
1FFFhROM’
2000h
3FFFh
2000h
2FFFhROM’
3000h
3FFFhROM’
4000h
5FFFh
RAM’
4000h
4FFFhROM’
5000h
5FFFhROM’
6000h
7FFFh
RAM’
6000h
6FFFhROM’
7000h7FFFh
ROM’
8000h
9FFFh
F000h
FFFFh
A000h
BFFFh
C000h
DFFFh
RAM
E000h
FFFFh
RAM’
WR
RD
OE
ROM4 kb
CSZ80 CPU
D7~D0D7~D0
A11~A0A12~A0
MREQ
RAM8 kb
D7~D0
A12~A0
RD WR CS
A14
A15
XA13
Conflict
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2222
Full (exhaustive) decoding
MREQ
WR
RD
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
OE
2764EPROM
8k8
CE
D7~D0
A12~A0
RD
6116RWM2k8
CS
D7~D0A10~A0
WR
D7~D0
A12~A0
A10~A0
A13
A12
A11
A15
A14
RD
7421
0000h-07FFh
0800h-0FFFh
1000h-17FFh
1800h-1FFFh
2000h-27FFh
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0000
0001
0000
1111
0000
1111
0000
1111ROM
0010
0010
0000
0111
0000
1111
0000
1111RAM
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2323
Partial decoding
MREQ
WR
RD
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
OE
2764EPROM
8k8
CE
D7~D0
A12~A0
RD
6116RWM2k8
CS
D7~D0A10~A0
WR
D7~D0
A12~A0
A10~A0
A15
A14
A13
RD
0000h-1FFFh
2000h-3FFFh
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0000
0001
0000
1111
0000
1111
0000
1111ROM
001x
001x
x000
x111
0000
1111
0000
1111RAM
GND
VCC
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2424
1 Bit Memory With Separated I/O
RDWR /
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
D0D1D7
D7-D0
A11-A0A11-A0A11-A0
CS
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2525
What is the memory(addr. bit) map
WR
RD
D0
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
2147RWM4k1
CS
DoutA11~A0
RDWR /
Din
D1D7D7-D0
A11-A0A11-A0A11-A0
RD
OE
2764EPROM
8k8
CE
D7~D0
A12~A0
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
0000h-1FFFh
2000h-3FFFh
MREQ
A15
A14
A13
GND
VCC
WR
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2626
Adding RAM & ROM
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2727
Minimum Z80 Computer System
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2828
Z80-µP-Family (Typical Environment)
+5V
Z80 CPU+5V IEI IEI
IEI
IEOINT -
IEO
INT -
INT - RDY
W/RDYB -INT -
INT -
RxCA -TxCA -
RxCB -TxCB -
ZC/TO2ZC/TO1
CTC SIO
PIO DMA
System Buses (Address, Data, Control)
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 2929
Z80 Input Output
Z80 at most could have 256 input port and 256 output 8 bit port address is placed on A7–A0 pin to select the I/O device OUT (n), A
n is 8 bit port address Content of A is data
OUT (C), r
Content of C is a port address r is a data register
IN A, (n) n is 8 bit port address Data is transfered to A
IN r (C) Content of Reg C is a port address Input data is transfered to r (data reg)
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3030
Remember IO read/write cycle
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3131
Z80 and simple output port
Z80CPU
A14
A0:
D7D6
WR
IORQ
A15
D5D4D3D2D1D0
A7A6A5A4A3A2A1A0IOWR
74LS373
Q0Q1Q2Q3Q4Q5Q6Q7
D0D1D2D3D4D5D6D7
OELE
OUT (03), A
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3232
Z80 and simple input port
Z80CPU
A14
A0:
D7D6
RD
IORQ
A15
D5D4D3D2D1D0
A7A6A5A4A3A2A1A0IORD
74LS244
A0A1A2A3A4A5A6A7
Y0Y1Y2Y3Y4Y5Y6Y7
G1 G2
5V
IN A, (02)
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3333
8088 and simple output port
A15
8088Minimum
Mode
A18
A0:
D7D6
IORIOW
A19
D5D4D3D2D1D0
A14
A13
A12
A11
A10
A9A8A7A6A5A4A3A2A1A0IOW
74LS373
Q0Q1Q2Q3Q4Q5Q6Q7
D0D1D2D3D4D5D6D7
OELE
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3434
8088 and simple input port
A15
8088Minimum
Mode
A18
A0:
D7D6
IORIOW
A19
D5D4D3D2D1D0
A14
A13
A12
A11
A10
A9A8A7A6A5A4A3A2A1A0IOW
What is this?
74LS244
A0A1A2A3A4A5A6A7
Y0Y1Y2Y3Y4Y5Y6Y7
G1 G2
5V
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3535
Simplified Drawing of 8088 Minimum Mode
D7 - D0 Q7 - Q0
OELE 74LS373
D7 - D0 Q7 - Q0
OELE 74LS3738088
AD7 - AD0
A15 - A8
A19/S6-A16/S3
DENDT/R
IO / M
RD
WR
ALE
D7 - D4 Q7 - Q4
OELE 74LS373
D3 - D0 Q3 - Q0
GND
GND
GND
A7 - A0 B7 - B0
EDIR 74LS245
MEMR
MEMW
IOR
IOW
A7-A0
A15-A8
A19-A16
D7-D0
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3636
Minimum Mode
220 bytes or 1MB memory
1 MBMemory
D7 - D0
A19 - A0
RD
WR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A19 - A0
MEMR
MEMW
CS
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3737
Memory location
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
Example: 34FD0 0011 0100 11111 1101 0000
What is the memory location of a 1MB (220 bytes) Memory?
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3838
Minimum Mode
512 kB memory
512 kBMemory
D7 - D0
A18 - A0
RD
WR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A18 - A0
MEMR
MEMW
CS
A19What do we do with A19?
1) Don’t connect it2) Connect to cs
What is the difference?
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 3939
512 kB Memory Map
Don’t connect it A19 is not connected
to the memory so even if the 8088 microprocessor outputs a logic “1”,the memory cannot “see” it.
A19=0 is the same as A19=1 for Memory
Connect to cs If A19=0 Memory chip
act normal fanction
00000h
7FFFFh
512kMem
80000h
FFFFFh
512kMem’
00000h
7FFFFh
512kMem
80000h
FFFFFh Empty
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4040
2 512 kB memory
512 kBRAM1
D7 - D0
A18 - A0
RDWR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A18 - A0
MEMR
MEMW
CS
A19
512 kBRAM2
D7 - D0
A18 - A0
RD
WR
MEMR
MEMW
CS
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4141
2512 kB memory
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210Memory
Chip
0000
0111
0000
1111
0000
1111
0000
1111
0000
1111 ROM
1000
1111
0000
1111
0000
1111
0000
1111
0000
1111 RAM
00000h
7FFFFh
512kRAM1
80000h
FFFFFh
512kRAM2
What are the memory locations of two consecutive 512KB (219 bytes) Memory?
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4242
Interfacing four 256K Memory Chips to 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4343
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
Interfacing four 256K Memory Chips to 8088 Microprocessor
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4444
Memory chip#__ is mapped to:
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210 MemoryChip
RAM#1
RAM#2
RAM#3
RAM#4
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4545
Interfacing several 8K Memory Chips to 8088 P
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#?
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4646
Interfacing 1288K Memory Chips to 8088 P
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4747
Interfacing 1288K Memory Chips to 8088 P
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4848
Memory chip#__ is mapped to:
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210 MemoryChip
RAM#1
RAM#2
RAM#126
RAM#127
RAM#128
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 4949
Memory map & Address Bit map
MREQ
WR
RD
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
OE
2764EPROM
8k8
CE
D7~D0
A12~A0
RD
6116RWM2k8
CS
D7~D0A10~A0
WR
D7~D0
A12~A0
A10~A0
A14
A13
A12
A15
RD
7408
VCC
74244 input21GG
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 5050
8255Programmable Peripheral Interface (PPI)
Has 3 8_bit ports A, B and CPort C can be used as two 4 bit ports CL and
ChTwo address lines A0, A1 and a Chip select CS8255 can be configured by writing a control-
word in CR register
hsabaghianb @ kashanu.ac.irhsabaghianb @ kashanu.ac.ir Microprocessors Microprocessors 33- - 5151
Interfacing with 8255
8255
D7-D0
/CS
A0A1
/RD/WR
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
IOEQ
A2
A3
A4
A5
A6
A0
A1
/WR/RD
D7-D0